arch/powerpc/boot/dts/fsl/t2080qds.dts

   1 /*
   2  * T2080QDS Device Tree Source
   3  *
   4  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /include/ "t208xsi-pre.dtsi"
  36 /include/ "t208xqds.dtsi"
  37
  38 / {
  39         model = "fsl,T2080QDS";
  40         compatible = "fsl,T2080QDS";
  41         #address-cells = <2>;
  42         #size-cells = <2>;
  43         interrupt-parent = <&mpic>;
  44
  45         aliases {
  46                 emi1_slot1 = &t2080mdio2;
  47                 emi1_slot2 = &t2080mdio3;
  48                 emi1_slot3 = &t2080mdio4;
  49         };
  50
  51         rio: rapidio@ffe0c0000 {
  52                 reg = <0xf 0xfe0c0000 0 0x11000>;
  53
  54                 port1 {
  55                         ranges = <0 0 0xc 0x20000000 0 0x10000000>;
  56                 };
  57                 port2 {
  58                         ranges = <0 0 0xc 0x30000000 0 0x10000000>;
  59                 };
  60         };
  61 };
  62
  63 &soc {
  64         fman@400000 {
  65                 ethernet@e0000 {
  66                         phy-handle = <&phy_sgmii_s3_1e>;
  67                         phy-connection-type = "xgmii";
  68                 };
  69
  70                 ethernet@e2000 {
  71                         phy-handle = <&phy_sgmii_s3_1f>;
  72                         phy-connection-type = "xgmii";
  73                 };
  74
  75                 ethernet@e4000 {
  76                         phy-handle = <&rgmii_phy1>;
  77                         phy-connection-type = "rgmii";
  78                 };
  79
  80                 ethernet@e6000 {
  81                         phy-handle = <&rgmii_phy2>;
  82                         phy-connection-type = "rgmii";
  83                 };
  84
  85                 ethernet@e8000 {
  86                         phy-handle = <&phy_sgmii_s2_1e>;
  87                         phy-connection-type = "sgmii";
  88                 };
  89
  90                 ethernet@ea000 {
  91                         phy-handle = <&phy_sgmii_s2_1d>;
  92                         phy-connection-type = "sgmii";
  93                 };
  94
  95                 ethernet@f0000 {
  96                         phy-handle = <&phy_xaui_slot3>;
  97                         phy-connection-type = "xgmii";
  98                 };
  99
 100                 ethernet@f2000 {
 101                         phy-handle = <&phy_sgmii_s3_1f>;
 102                         phy-connection-type = "xgmii";
 103                 };
 104
 105                 mdio@fd000 {
 106                         phy_xaui_slot3: ethernet-phy@3 {
 107                                 compatible = "ethernet-phy-ieee802.3-c45";
 108                                 reg = <0x3>;
 109                         };
 110                 };
 111         };
 112 };
 113
 114 &boardctrl {
 115         mdio-mux-emi1 {
 116                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 117                 mdio-parent-bus = <&mdio0>;
 118                 #address-cells = <1>;
 119                 #size-cells = <0>;
 120                 reg = <0x54 1>;
 121                 mux-mask = <0xe0>;
 122
 123                 t2080mdio0: mdio@0 {
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         reg = <0>;
 127
 128                         rgmii_phy1: ethernet-phy@1 {
 129                                 reg = <0x1>;
 130                         };
 131                 };
 132
 133                 t2080mdio1: mdio@20 {
 134                         #address-cells = <1>;
 135                         #size-cells = <0>;
 136                         reg = <0x20>;
 137
 138                         rgmii_phy2: ethernet-phy@2 {
 139                                 reg = <0x2>;
 140                         };
 141                 };
 142
 143                 t2080mdio2: mdio@40 {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         reg = <0x40>;
 147                         status = "disabled";
 148
 149                         phy_sgmii_s1_1c: ethernet-phy@1c {
 150                                 reg = <0x1c>;
 151                         };
 152
 153                         phy_sgmii_s1_1d: ethernet-phy@1d {
 154                                 reg = <0x1d>;
 155                         };
 156
 157                         phy_sgmii_s1_1e: ethernet-phy@1e {
 158                                 reg = <0x1e>;
 159                         };
 160
 161                         phy_sgmii_s1_1f: ethernet-phy@1f {
 162                                 reg = <0x1f>;
 163                         };
 164                 };
 165
 166                 t2080mdio3: mdio@c0 {
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169                         reg = <0xc0>;
 170
 171                         phy_sgmii_s2_1c: ethernet-phy@1c {
 172                                 reg = <0x1c>;
 173                         };
 174
 175                         phy_sgmii_s2_1d: ethernet-phy@1d {
 176                                 reg = <0x1d>;
 177                         };
 178
 179                         phy_sgmii_s2_1e: ethernet-phy@1e {
 180                                 reg = <0x1e>;
 181                         };
 182
 183                         phy_sgmii_s2_1f: ethernet-phy@1f {
 184                                 reg = <0x1f>;
 185                         };
 186                 };
 187
 188                 t2080mdio4: mdio@60 {
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         reg = <0x60>;
 192                         status = "disabled";
 193
 194                         phy_sgmii_s3_1c: ethernet-phy@1c {
 195                                 reg = <0x1c>;
 196                         };
 197
 198                         phy_sgmii_s3_1d: ethernet-phy@1d {
 199                                 reg = <0x1d>;
 200                         };
 201
 202                         phy_sgmii_s3_1e: ethernet-phy@1e {
 203                                 reg = <0x1e>;
 204                         };
 205
 206                         phy_sgmii_s3_1f: ethernet-phy@1f {
 207                                 reg = <0x1f>;
 208                         };
 209                 };
 210         };
 211 };
 212
 213 /include/ "t2080si-post.dtsi"