| blob | 54f3e82907d699b34bfdd321e3210e93a11a318c |
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TQM 8555 Device Tree Source
4 *
5 * Copyright 2008 Freescale Semiconductor Inc.
6 */
8 /dts-v1/;
10 / {
11 model = "tqc,tqm8555";
12 compatible = "tqc,tqm8555";
13 #address-cells = <1>;
14 #size-cells = <1>;
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet1;
19 serial0 = &serial0;
20 serial1 = &serial1;
21 pci0 = &pci0;
22 };
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
28 PowerPC,8555@0 {
29 device_type = "cpu";
30 reg = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <32768>;
34 i-cache-size = <32768>;
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
38 next-level-cache = <&L2>;
39 };
40 };
42 memory {
43 device_type = "memory";
44 reg = <0x00000000 0x10000000>;
45 };
47 soc@e0000000 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 device_type = "soc";
51 ranges = <0x0 0xe0000000 0x100000>;
52 bus-frequency = <0>;
53 compatible = "fsl,mpc8555-immr", "simple-bus";
55 ecm-law@0 {
56 compatible = "fsl,ecm-law";
57 reg = <0x0 0x1000>;
58 fsl,num-laws = <8>;
59 };
61 ecm@1000 {
62 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
63 reg = <0x1000 0x1000>;
64 interrupts = <17 2>;
65 interrupt-parent = <&mpic>;
66 };
68 memory-controller@2000 {
69 compatible = "fsl,mpc8540-memory-controller";
70 reg = <0x2000 0x1000>;
71 interrupt-parent = <&mpic>;
72 interrupts = <18 2>;
73 };
75 L2: l2-cache-controller@20000 {
76 compatible = "fsl,mpc8540-l2-cache-controller";
77 reg = <0x20000 0x1000>;
78 cache-line-size = <32>;
79 cache-size = <0x40000>; // L2, 256K
80 interrupt-parent = <&mpic>;
81 interrupts = <16 2>;
82 };
84 i2c@3000 {
85 #address-cells = <1>;
86 #size-cells = <0>;
87 cell-index = <0>;
88 compatible = "fsl-i2c";
89 reg = <0x3000 0x100>;
90 interrupts = <43 2>;
91 interrupt-parent = <&mpic>;
92 dfsrr;
94 dtt@48 {
95 compatible = "national,lm75";
96 reg = <0x48>;
97 };
99 rtc@68 {
100 compatible = "dallas,ds1337";
101 reg = <0x68>;
102 };
103 };
105 dma@21300 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
109 reg = <0x21300 0x4>;
110 ranges = <0x0 0x21100 0x200>;
111 cell-index = <0>;
112 dma-channel@0 {
113 compatible = "fsl,mpc8555-dma-channel",
114 "fsl,eloplus-dma-channel";
115 reg = <0x0 0x80>;
116 cell-index = <0>;
117 interrupt-parent = <&mpic>;
118 interrupts = <20 2>;
119 };
120 dma-channel@80 {
121 compatible = "fsl,mpc8555-dma-channel",
122 "fsl,eloplus-dma-channel";
123 reg = <0x80 0x80>;
124 cell-index = <1>;
125 interrupt-parent = <&mpic>;
126 interrupts = <21 2>;
127 };
128 dma-channel@100 {
129 compatible = "fsl,mpc8555-dma-channel",
130 "fsl,eloplus-dma-channel";
131 reg = <0x100 0x80>;
132 cell-index = <2>;
133 interrupt-parent = <&mpic>;
134 interrupts = <22 2>;
135 };
136 dma-channel@180 {
137 compatible = "fsl,mpc8555-dma-channel",
138 "fsl,eloplus-dma-channel";
139 reg = <0x180 0x80>;
140 cell-index = <3>;
141 interrupt-parent = <&mpic>;
142 interrupts = <23 2>;
143 };
144 };
146 enet0: ethernet@24000 {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 cell-index = <0>;
150 device_type = "network";
151 model = "TSEC";
152 compatible = "gianfar";
153 reg = <0x24000 0x1000>;
154 ranges = <0x0 0x24000 0x1000>;
155 local-mac-address = [ 00 00 00 00 00 00 ];
156 interrupts = <29 2 30 2 34 2>;
157 interrupt-parent = <&mpic>;
158 tbi-handle = <&tbi0>;
159 phy-handle = <&phy2>;
161 mdio@520 {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 compatible = "fsl,gianfar-mdio";
165 reg = <0x520 0x20>;
167 phy1: ethernet-phy@1 {
168 interrupt-parent = <&mpic>;
169 interrupts = <8 1>;
170 reg = <1>;
171 };
172 phy2: ethernet-phy@2 {
173 interrupt-parent = <&mpic>;
174 interrupts = <8 1>;
175 reg = <2>;
176 };
177 phy3: ethernet-phy@3 {
178 interrupt-parent = <&mpic>;
179 interrupts = <8 1>;
180 reg = <3>;
181 };
182 tbi0: tbi-phy@11 {
183 reg = <0x11>;
184 device_type = "tbi-phy";
185 };
186 };
187 };
189 enet1: ethernet@25000 {
190 #address-cells = <1>;
191 #size-cells = <1>;
192 cell-index = <1>;
193 device_type = "network";
194 model = "TSEC";
195 compatible = "gianfar";
196 reg = <0x25000 0x1000>;
197 ranges = <0x0 0x25000 0x1000>;
198 local-mac-address = [ 00 00 00 00 00 00 ];
199 interrupts = <35 2 36 2 40 2>;
200 interrupt-parent = <&mpic>;
201 tbi-handle = <&tbi1>;
202 phy-handle = <&phy1>;
204 mdio@520 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,gianfar-tbi";
208 reg = <0x520 0x20>;
210 tbi1: tbi-phy@11 {
211 reg = <0x11>;
212 device_type = "tbi-phy";
213 };
214 };
215 };
217 serial0: serial@4500 {
218 cell-index = <0>;
219 device_type = "serial";
220 compatible = "fsl,ns16550", "ns16550";
221 reg = <0x4500 0x100>; // reg base, size
222 clock-frequency = <0>; // should we fill in in uboot?
223 interrupts = <42 2>;
224 interrupt-parent = <&mpic>;
225 };
227 serial1: serial@4600 {
228 cell-index = <1>;
229 device_type = "serial";
230 compatible = "fsl,ns16550", "ns16550";
231 reg = <0x4600 0x100>; // reg base, size
232 clock-frequency = <0>; // should we fill in in uboot?
233 interrupts = <42 2>;
234 interrupt-parent = <&mpic>;
235 };
237 crypto@30000 {
238 compatible = "fsl,sec2.0";
239 reg = <0x30000 0x10000>;
240 interrupts = <45 2>;
241 interrupt-parent = <&mpic>;
242 fsl,num-channels = <4>;
243 fsl,channel-fifo-len = <24>;
244 fsl,exec-units-mask = <0x7e>;
245 fsl,descriptor-types-mask = <0x01010ebf>;
246 };
248 mpic: pic@40000 {
249 interrupt-controller;
250 #address-cells = <0>;
251 #interrupt-cells = <2>;
252 reg = <0x40000 0x40000>;
253 device_type = "open-pic";
254 compatible = "chrp,open-pic";
255 };
257 cpm@919c0 {
258 #address-cells = <1>;
259 #size-cells = <1>;
260 compatible = "fsl,mpc8555-cpm", "fsl,cpm2", "simple-bus";
261 reg = <0x919c0 0x30>;
262 ranges;
264 muram@80000 {
265 #address-cells = <1>;
266 #size-cells = <1>;
267 ranges = <0 0x80000 0x10000>;
269 data@0 {
270 compatible = "fsl,cpm-muram-data";
271 reg = <0 0x2000 0x9000 0x1000>;
272 };
273 };
275 brg@919f0 {
276 compatible = "fsl,mpc8555-brg",
277 "fsl,cpm2-brg",
278 "fsl,cpm-brg";
279 reg = <0x919f0 0x10 0x915f0 0x10>;
280 clock-frequency = <0>;
281 };
283 cpmpic: pic@90c00 {
284 interrupt-controller;
285 #address-cells = <0>;
286 #interrupt-cells = <2>;
287 interrupts = <46 2>;
288 interrupt-parent = <&mpic>;
289 reg = <0x90c00 0x80>;
290 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
291 };
292 };
293 };
295 pci0: pci@e0008000 {
296 #interrupt-cells = <1>;
297 #size-cells = <2>;
298 #address-cells = <3>;
299 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
300 device_type = "pci";
301 reg = <0xe0008000 0x1000>;
302 clock-frequency = <66666666>;
303 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
304 interrupt-map = <
305 /* IDSEL 28 */
306 0xe000 0 0 1 &mpic 2 1
307 0xe000 0 0 2 &mpic 3 1
308 0xe000 0 0 3 &mpic 6 1
309 0xe000 0 0 4 &mpic 5 1
311 /* IDSEL 11 */
312 0x5800 0 0 1 &mpic 6 1
313 0x5800 0 0 2 &mpic 5 1
314 >;
316 interrupt-parent = <&mpic>;
317 interrupts = <24 2>;
318 bus-range = <0 0>;
319 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
320 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
321 };
322 };