1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright 2017 IBM Corp.
3 #ifndef _ASM_PNV_OCXL_H
4 #define _ASM_PNV_OCXL_H
8 #define PNV_OCXL_TL_MAX_TEMPLATE 63
9 #define PNV_OCXL_TL_BITS_PER_RATE 4
10 #define PNV_OCXL_TL_RATE_BUF_SIZE ((PNV_OCXL_TL_MAX_TEMPLATE+1) * PNV_OCXL_TL_BITS_PER_RATE / 8)
12 extern int pnv_ocxl_get_actag(struct pci_dev
*dev
, u16
*base
, u16
*enabled
,
14 extern int pnv_ocxl_get_pasid_count(struct pci_dev
*dev
, int *count
);
16 extern int pnv_ocxl_get_tl_cap(struct pci_dev
*dev
, long *cap
,
17 char *rate_buf
, int rate_buf_size
);
18 extern int pnv_ocxl_set_tl_conf(struct pci_dev
*dev
, long cap
,
19 uint64_t rate_buf_phys
, int rate_buf_size
);
21 extern int pnv_ocxl_get_xsl_irq(struct pci_dev
*dev
, int *hwirq
);
22 extern void pnv_ocxl_unmap_xsl_regs(void __iomem
*dsisr
, void __iomem
*dar
,
23 void __iomem
*tfc
, void __iomem
*pe_handle
);
24 extern int pnv_ocxl_map_xsl_regs(struct pci_dev
*dev
, void __iomem
**dsisr
,
25 void __iomem
**dar
, void __iomem
**tfc
,
26 void __iomem
**pe_handle
);
28 extern int pnv_ocxl_spa_setup(struct pci_dev
*dev
, void *spa_mem
, int PE_mask
,
29 void **platform_data
);
30 extern void pnv_ocxl_spa_release(void *platform_data
);
31 extern int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data
, int pe_handle
);
33 extern int pnv_ocxl_alloc_xive_irq(u32
*irq
, u64
*trigger_addr
);
34 extern void pnv_ocxl_free_xive_irq(u32 irq
);
36 #endif /* _ASM_PNV_OCXL_H */