| blob | c1df75edde441c0269b57a2c24f75c5b44747f56 |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright 2009 Freescale Semiconductor, Inc.
4 *
5 * provides masks and opcode images for use by code generation, emulation
6 * and for instructions that older assemblers might not know about
7 */
8 #ifndef _ASM_POWERPC_PPC_OPCODE_H
9 #define _ASM_POWERPC_PPC_OPCODE_H
11 #include <asm/asm-const.h>
13 #define __REG_R0 0
14 #define __REG_R1 1
15 #define __REG_R2 2
16 #define __REG_R3 3
17 #define __REG_R4 4
18 #define __REG_R5 5
19 #define __REG_R6 6
20 #define __REG_R7 7
21 #define __REG_R8 8
22 #define __REG_R9 9
23 #define __REG_R10 10
24 #define __REG_R11 11
25 #define __REG_R12 12
26 #define __REG_R13 13
27 #define __REG_R14 14
28 #define __REG_R15 15
29 #define __REG_R16 16
30 #define __REG_R17 17
31 #define __REG_R18 18
32 #define __REG_R19 19
33 #define __REG_R20 20
34 #define __REG_R21 21
35 #define __REG_R22 22
36 #define __REG_R23 23
37 #define __REG_R24 24
38 #define __REG_R25 25
39 #define __REG_R26 26
40 #define __REG_R27 27
41 #define __REG_R28 28
42 #define __REG_R29 29
43 #define __REG_R30 30
44 #define __REG_R31 31
46 #define __REGA0_0 0
47 #define __REGA0_R1 1
48 #define __REGA0_R2 2
49 #define __REGA0_R3 3
50 #define __REGA0_R4 4
51 #define __REGA0_R5 5
52 #define __REGA0_R6 6
53 #define __REGA0_R7 7
54 #define __REGA0_R8 8
55 #define __REGA0_R9 9
56 #define __REGA0_R10 10
57 #define __REGA0_R11 11
58 #define __REGA0_R12 12
59 #define __REGA0_R13 13
60 #define __REGA0_R14 14
61 #define __REGA0_R15 15
62 #define __REGA0_R16 16
63 #define __REGA0_R17 17
64 #define __REGA0_R18 18
65 #define __REGA0_R19 19
66 #define __REGA0_R20 20
67 #define __REGA0_R21 21
68 #define __REGA0_R22 22
69 #define __REGA0_R23 23
70 #define __REGA0_R24 24
71 #define __REGA0_R25 25
72 #define __REGA0_R26 26
73 #define __REGA0_R27 27
74 #define __REGA0_R28 28
75 #define __REGA0_R29 29
76 #define __REGA0_R30 30
77 #define __REGA0_R31 31
79 /* opcode and xopcode for instructions */
80 #define OP_TRAP 3
81 #define OP_TRAP_64 2
83 #define OP_31_XOP_TRAP 4
84 #define OP_31_XOP_LDX 21
85 #define OP_31_XOP_LWZX 23
86 #define OP_31_XOP_LDUX 53
87 #define OP_31_XOP_DCBST 54
88 #define OP_31_XOP_LWZUX 55
89 #define OP_31_XOP_TRAP_64 68
90 #define OP_31_XOP_DCBF 86
91 #define OP_31_XOP_LBZX 87
92 #define OP_31_XOP_STDX 149
93 #define OP_31_XOP_STWX 151
94 #define OP_31_XOP_STDUX 181
95 #define OP_31_XOP_STWUX 183
96 #define OP_31_XOP_STBX 215
97 #define OP_31_XOP_LBZUX 119
98 #define OP_31_XOP_STBUX 247
99 #define OP_31_XOP_LHZX 279
100 #define OP_31_XOP_LHZUX 311
101 #define OP_31_XOP_MSGSNDP 142
102 #define OP_31_XOP_MSGCLRP 174
103 #define OP_31_XOP_TLBIE 306
104 #define OP_31_XOP_MFSPR 339
105 #define OP_31_XOP_LWAX 341
106 #define OP_31_XOP_LHAX 343
107 #define OP_31_XOP_LWAUX 373
108 #define OP_31_XOP_LHAUX 375
109 #define OP_31_XOP_STHX 407
110 #define OP_31_XOP_STHUX 439
111 #define OP_31_XOP_MTSPR 467
112 #define OP_31_XOP_DCBI 470
113 #define OP_31_XOP_LDBRX 532
114 #define OP_31_XOP_LWBRX 534
115 #define OP_31_XOP_TLBSYNC 566
116 #define OP_31_XOP_STDBRX 660
117 #define OP_31_XOP_STWBRX 662
118 #define OP_31_XOP_STFSX 663
119 #define OP_31_XOP_STFSUX 695
120 #define OP_31_XOP_STFDX 727
121 #define OP_31_XOP_STFDUX 759
122 #define OP_31_XOP_LHBRX 790
123 #define OP_31_XOP_LFIWAX 855
124 #define OP_31_XOP_LFIWZX 887
125 #define OP_31_XOP_STHBRX 918
126 #define OP_31_XOP_STFIWX 983
128 /* VSX Scalar Load Instructions */
129 #define OP_31_XOP_LXSDX 588
130 #define OP_31_XOP_LXSSPX 524
131 #define OP_31_XOP_LXSIWAX 76
132 #define OP_31_XOP_LXSIWZX 12
134 /* VSX Scalar Store Instructions */
135 #define OP_31_XOP_STXSDX 716
136 #define OP_31_XOP_STXSSPX 652
137 #define OP_31_XOP_STXSIWX 140
139 /* VSX Vector Load Instructions */
140 #define OP_31_XOP_LXVD2X 844
141 #define OP_31_XOP_LXVW4X 780
143 /* VSX Vector Load and Splat Instruction */
144 #define OP_31_XOP_LXVDSX 332
146 /* VSX Vector Store Instructions */
147 #define OP_31_XOP_STXVD2X 972
148 #define OP_31_XOP_STXVW4X 908
150 #define OP_31_XOP_LFSX 535
151 #define OP_31_XOP_LFSUX 567
152 #define OP_31_XOP_LFDX 599
153 #define OP_31_XOP_LFDUX 631
155 /* VMX Vector Load Instructions */
156 #define OP_31_XOP_LVX 103
158 /* VMX Vector Store Instructions */
159 #define OP_31_XOP_STVX 231
161 #define OP_31 31
162 #define OP_LWZ 32
163 #define OP_STFS 52
164 #define OP_STFSU 53
165 #define OP_STFD 54
166 #define OP_STFDU 55
167 #define OP_LD 58
168 #define OP_LWZU 33
169 #define OP_LBZ 34
170 #define OP_LBZU 35
171 #define OP_STW 36
172 #define OP_STWU 37
173 #define OP_STD 62
174 #define OP_STB 38
175 #define OP_STBU 39
176 #define OP_LHZ 40
177 #define OP_LHZU 41
178 #define OP_LHA 42
179 #define OP_LHAU 43
180 #define OP_STH 44
181 #define OP_STHU 45
182 #define OP_LMW 46
183 #define OP_STMW 47
184 #define OP_LFS 48
185 #define OP_LFSU 49
186 #define OP_LFD 50
187 #define OP_LFDU 51
188 #define OP_STFS 52
189 #define OP_STFSU 53
190 #define OP_STFD 54
191 #define OP_STFDU 55
192 #define OP_LQ 56
194 /* sorted alphabetically */
195 #define PPC_INST_BHRBE 0x7c00025c
196 #define PPC_INST_CLRBHRB 0x7c00035c
197 #define PPC_INST_COPY 0x7c20060c
198 #define PPC_INST_CP_ABORT 0x7c00068c
199 #define PPC_INST_DARN 0x7c0005e6
200 #define PPC_INST_DCBA 0x7c0005ec
201 #define PPC_INST_DCBA_MASK 0xfc0007fe
202 #define PPC_INST_DCBAL 0x7c2005ec
203 #define PPC_INST_DCBZL 0x7c2007ec
204 #define PPC_INST_ICBT 0x7c00002c
205 #define PPC_INST_ICSWX 0x7c00032d
206 #define PPC_INST_ICSWEPX 0x7c00076d
207 #define PPC_INST_ISEL 0x7c00001e
208 #define PPC_INST_ISEL_MASK 0xfc00003e
209 #define PPC_INST_LDARX 0x7c0000a8
210 #define PPC_INST_STDCX 0x7c0001ad
211 #define PPC_INST_LQARX 0x7c000228
212 #define PPC_INST_STQCX 0x7c00016d
213 #define PPC_INST_LSWI 0x7c0004aa
214 #define PPC_INST_LSWX 0x7c00042a
215 #define PPC_INST_LWARX 0x7c000028
216 #define PPC_INST_STWCX 0x7c00012d
217 #define PPC_INST_LWSYNC 0x7c2004ac
218 #define PPC_INST_SYNC 0x7c0004ac
219 #define PPC_INST_SYNC_MASK 0xfc0007fe
220 #define PPC_INST_ISYNC 0x4c00012c
221 #define PPC_INST_LXVD2X 0x7c000698
222 #define PPC_INST_MCRXR 0x7c000400
223 #define PPC_INST_MCRXR_MASK 0xfc0007fe
224 #define PPC_INST_MFSPR_PVR 0x7c1f42a6
225 #define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe
226 #define PPC_INST_MFTMR 0x7c0002dc
227 #define PPC_INST_MSGSND 0x7c00019c
228 #define PPC_INST_MSGCLR 0x7c0001dc
229 #define PPC_INST_MSGSYNC 0x7c0006ec
230 #define PPC_INST_MSGSNDP 0x7c00011c
231 #define PPC_INST_MSGCLRP 0x7c00015c
232 #define PPC_INST_MTMSRD 0x7c000164
233 #define PPC_INST_MTTMR 0x7c0003dc
234 #define PPC_INST_NOP 0x60000000
235 #define PPC_INST_PASTE 0x7c20070d
236 #define PPC_INST_POPCNTB 0x7c0000f4
237 #define PPC_INST_POPCNTB_MASK 0xfc0007fe
238 #define PPC_INST_POPCNTD 0x7c0003f4
239 #define PPC_INST_POPCNTW 0x7c0002f4
240 #define PPC_INST_RFEBB 0x4c000124
241 #define PPC_INST_RFCI 0x4c000066
242 #define PPC_INST_RFDI 0x4c00004e
243 #define PPC_INST_RFID 0x4c000024
244 #define PPC_INST_RFMCI 0x4c00004c
245 #define PPC_INST_MFSPR 0x7c0002a6
246 #define PPC_INST_MFSPR_DSCR 0x7c1102a6
247 #define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe
248 #define PPC_INST_MTSPR_DSCR 0x7c1103a6
249 #define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe
250 #define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
251 #define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe
252 #define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
253 #define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe
254 #define PPC_INST_MFVSRD 0x7c000066
255 #define PPC_INST_MTVSRD 0x7c000166
256 #define PPC_INST_SC 0x44000002
257 #define PPC_INST_SLBFEE 0x7c0007a7
258 #define PPC_INST_SLBIA 0x7c0003e4
260 #define PPC_INST_STRING 0x7c00042a
261 #define PPC_INST_STRING_MASK 0xfc0007fe
262 #define PPC_INST_STRING_GEN_MASK 0xfc00067e
264 #define PPC_INST_STSWI 0x7c0005aa
265 #define PPC_INST_STSWX 0x7c00052a
266 #define PPC_INST_STXVD2X 0x7c000798
267 #define PPC_INST_TLBIE 0x7c000264
268 #define PPC_INST_TLBIEL 0x7c000224
269 #define PPC_INST_TLBILX 0x7c000024
270 #define PPC_INST_WAIT 0x7c00007c
271 #define PPC_INST_TLBIVAX 0x7c000624
272 #define PPC_INST_TLBSRX_DOT 0x7c0006a5
273 #define PPC_INST_VPMSUMW 0x10000488
274 #define PPC_INST_VPMSUMD 0x100004c8
275 #define PPC_INST_VPERMXOR 0x1000002d
276 #define PPC_INST_XXLOR 0xf0000490
277 #define PPC_INST_XXSWAPD 0xf0000250
278 #define PPC_INST_XVCPSGNDP 0xf0000780
279 #define PPC_INST_TRECHKPT 0x7c0007dd
280 #define PPC_INST_TRECLAIM 0x7c00075d
281 #define PPC_INST_TABORT 0x7c00071d
282 #define PPC_INST_TSR 0x7c0005dd
284 #define PPC_INST_NAP 0x4c000364
285 #define PPC_INST_SLEEP 0x4c0003a4
286 #define PPC_INST_WINKLE 0x4c0003e4
288 #define PPC_INST_STOP 0x4c0002e4
290 /* A2 specific instructions */
291 #define PPC_INST_ERATWE 0x7c0001a6
292 #define PPC_INST_ERATRE 0x7c000166
293 #define PPC_INST_ERATILX 0x7c000066
294 #define PPC_INST_ERATIVAX 0x7c000666
295 #define PPC_INST_ERATSX 0x7c000126
296 #define PPC_INST_ERATSX_DOT 0x7c000127
298 /* Misc instructions for BPF compiler */
299 #define PPC_INST_LBZ 0x88000000
300 #define PPC_INST_LD 0xe8000000
301 #define PPC_INST_LDX 0x7c00002a
302 #define PPC_INST_LHZ 0xa0000000
303 #define PPC_INST_LWZ 0x80000000
304 #define PPC_INST_LHBRX 0x7c00062c
305 #define PPC_INST_LDBRX 0x7c000428
306 #define PPC_INST_STB 0x98000000
307 #define PPC_INST_STH 0xb0000000
308 #define PPC_INST_STD 0xf8000000
309 #define PPC_INST_STDX 0x7c00012a
310 #define PPC_INST_STDU 0xf8000001
311 #define PPC_INST_STW 0x90000000
312 #define PPC_INST_STWU 0x94000000
313 #define PPC_INST_MFLR 0x7c0802a6
314 #define PPC_INST_MTLR 0x7c0803a6
315 #define PPC_INST_MTCTR 0x7c0903a6
316 #define PPC_INST_CMPWI 0x2c000000
317 #define PPC_INST_CMPDI 0x2c200000
318 #define PPC_INST_CMPW 0x7c000000
319 #define PPC_INST_CMPD 0x7c200000
320 #define PPC_INST_CMPLW 0x7c000040
321 #define PPC_INST_CMPLD 0x7c200040
322 #define PPC_INST_CMPLWI 0x28000000
323 #define PPC_INST_CMPLDI 0x28200000
324 #define PPC_INST_ADDI 0x38000000
325 #define PPC_INST_ADDIS 0x3c000000
326 #define PPC_INST_ADD 0x7c000214
327 #define PPC_INST_ADDC 0x7c000014
328 #define PPC_INST_SUB 0x7c000050
329 #define PPC_INST_BLR 0x4e800020
330 #define PPC_INST_BLRL 0x4e800021
331 #define PPC_INST_BCTR 0x4e800420
332 #define PPC_INST_MULLD 0x7c0001d2
333 #define PPC_INST_MULLW 0x7c0001d6
334 #define PPC_INST_MULHWU 0x7c000016
335 #define PPC_INST_MULLI 0x1c000000
336 #define PPC_INST_MADDHD 0x10000030
337 #define PPC_INST_MADDHDU 0x10000031
338 #define PPC_INST_MADDLD 0x10000033
339 #define PPC_INST_DIVWU 0x7c000396
340 #define PPC_INST_DIVD 0x7c0003d2
341 #define PPC_INST_DIVDU 0x7c000392
342 #define PPC_INST_RLWINM 0x54000000
343 #define PPC_INST_RLWINM_DOT 0x54000001
344 #define PPC_INST_RLWIMI 0x50000000
345 #define PPC_INST_RLDICL 0x78000000
346 #define PPC_INST_RLDICR 0x78000004
347 #define PPC_INST_SLW 0x7c000030
348 #define PPC_INST_SLD 0x7c000036
349 #define PPC_INST_SRW 0x7c000430
350 #define PPC_INST_SRAW 0x7c000630
351 #define PPC_INST_SRAWI 0x7c000670
352 #define PPC_INST_SRD 0x7c000436
353 #define PPC_INST_SRAD 0x7c000634
354 #define PPC_INST_SRADI 0x7c000674
355 #define PPC_INST_AND 0x7c000038
356 #define PPC_INST_ANDDOT 0x7c000039
357 #define PPC_INST_OR 0x7c000378
358 #define PPC_INST_XOR 0x7c000278
359 #define PPC_INST_ANDI 0x70000000
360 #define PPC_INST_ORI 0x60000000
361 #define PPC_INST_ORIS 0x64000000
362 #define PPC_INST_XORI 0x68000000
363 #define PPC_INST_XORIS 0x6c000000
364 #define PPC_INST_NEG 0x7c0000d0
365 #define PPC_INST_EXTSW 0x7c0007b4
366 #define PPC_INST_BRANCH 0x48000000
367 #define PPC_INST_BRANCH_COND 0x40800000
368 #define PPC_INST_LBZCIX 0x7c0006aa
369 #define PPC_INST_STBCIX 0x7c0007aa
370 #define PPC_INST_LWZX 0x7c00002e
371 #define PPC_INST_LFSX 0x7c00042e
372 #define PPC_INST_STFSX 0x7c00052e
373 #define PPC_INST_LFDX 0x7c0004ae
374 #define PPC_INST_STFDX 0x7c0005ae
375 #define PPC_INST_LVX 0x7c0000ce
376 #define PPC_INST_STVX 0x7c0001ce
377 #define PPC_INST_VCMPEQUD 0x100000c7
378 #define PPC_INST_VCMPEQUB 0x10000006
380 /* macros to insert fields into opcodes */
381 #define ___PPC_RA(a) (((a) & 0x1f) << 16)
382 #define ___PPC_RB(b) (((b) & 0x1f) << 11)
383 #define ___PPC_RC(c) (((c) & 0x1f) << 6)
384 #define ___PPC_RS(s) (((s) & 0x1f) << 21)
385 #define ___PPC_RT(t) ___PPC_RS(t)
386 #define ___PPC_R(r) (((r) & 0x1) << 16)
387 #define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
388 #define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
389 #define __PPC_RA(a) ___PPC_RA(__REG_##a)
390 #define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
391 #define __PPC_RB(b) ___PPC_RB(__REG_##b)
392 #define __PPC_RS(s) ___PPC_RS(__REG_##s)
393 #define __PPC_RT(t) ___PPC_RT(__REG_##t)
394 #define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
395 #define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
396 #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
397 #define __PPC_XT(s) __PPC_XS(s)
398 #define __PPC_T_TLB(t) (((t) & 0x3) << 21)
399 #define __PPC_WC(w) (((w) & 0x3) << 21)
400 #define __PPC_WS(w) (((w) & 0x1f) << 11)
401 #define __PPC_SH(s) __PPC_WS(s)
402 #define __PPC_SH64(s) (__PPC_SH(s) | (((s) & 0x20) >> 4))
403 #define __PPC_MB(s) ___PPC_RC(s)
404 #define __PPC_ME(s) (((s) & 0x1f) << 1)
405 #define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20))
406 #define __PPC_ME64(s) __PPC_MB64(s)
407 #define __PPC_BI(s) (((s) & 0x1f) << 16)
408 #define __PPC_CT(t) (((t) & 0x0f) << 21)
409 #define __PPC_SPR(r) ((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11))
410 #define __PPC_RC21 (0x1 << 10)
412 /*
413 * Both low and high 16 bits are added as SIGNED additions, so if low 16 bits
414 * has high bit set, high 16 bits must be adjusted. These macros do that (stolen
415 * from binutils).
416 */
417 #define PPC_LO(v) ((v) & 0xffff)
418 #define PPC_HI(v) (((v) >> 16) & 0xffff)
419 #define PPC_HA(v) PPC_HI((v) + 0x8000)
421 /*
422 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
423 * larx with EH set as an illegal instruction.
424 */
425 #ifdef CONFIG_PPC64
426 #define __PPC_EH(eh) (((eh) & 0x1) << 0)
427 #else
428 #define __PPC_EH(eh) 0
429 #endif
431 /* Deal with instructions that older assemblers aren't aware of */
432 #define PPC_CP_ABORT stringify_in_c(.long PPC_INST_CP_ABORT)
433 #define PPC_COPY(a, b) stringify_in_c(.long PPC_INST_COPY | \
434 ___PPC_RA(a) | ___PPC_RB(b))
435 #define PPC_DARN(t, l) stringify_in_c(.long PPC_INST_DARN | \
436 ___PPC_RT(t) | \
437 (((l) & 0x3) << 16))
438 #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
439 __PPC_RA(a) | __PPC_RB(b))
440 #define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
441 __PPC_RA(a) | __PPC_RB(b))
442 #define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LQARX | \
443 ___PPC_RT(t) | ___PPC_RA(a) | \
444 ___PPC_RB(b) | __PPC_EH(eh))
445 #define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
446 ___PPC_RT(t) | ___PPC_RA(a) | \
447 ___PPC_RB(b) | __PPC_EH(eh))
448 #define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
449 ___PPC_RT(t) | ___PPC_RA(a) | \
450 ___PPC_RB(b) | __PPC_EH(eh))
451 #define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_INST_STQCX | \
452 ___PPC_RT(t) | ___PPC_RA(a) | \
453 ___PPC_RB(b))
454 #define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_INST_MADDHD | \
455 ___PPC_RT(t) | ___PPC_RA(a) | \
456 ___PPC_RB(b) | ___PPC_RC(c))
457 #define PPC_MADDHDU(t, a, b, c) stringify_in_c(.long PPC_INST_MADDHDU | \
458 ___PPC_RT(t) | ___PPC_RA(a) | \
459 ___PPC_RB(b) | ___PPC_RC(c))
460 #define PPC_MADDLD(t, a, b, c) stringify_in_c(.long PPC_INST_MADDLD | \
461 ___PPC_RT(t) | ___PPC_RA(a) | \
462 ___PPC_RB(b) | ___PPC_RC(c))
463 #define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
464 ___PPC_RB(b))
465 #define PPC_MSGSYNC stringify_in_c(.long PPC_INST_MSGSYNC)
466 #define PPC_MSGCLR(b) stringify_in_c(.long PPC_INST_MSGCLR | \
467 ___PPC_RB(b))
468 #define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \
469 ___PPC_RB(b))
470 #define PPC_MSGCLRP(b) stringify_in_c(.long PPC_INST_MSGCLRP | \
471 ___PPC_RB(b))
472 #define PPC_PASTE(a, b) stringify_in_c(.long PPC_INST_PASTE | \
473 ___PPC_RA(a) | ___PPC_RB(b))
474 #define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
475 __PPC_RA(a) | __PPC_RS(s))
476 #define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
477 __PPC_RA(a) | __PPC_RS(s))
478 #define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
479 __PPC_RA(a) | __PPC_RS(s))
480 #define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
481 #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
482 #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
483 #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
484 __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
485 #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
486 #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
487 #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
488 #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
489 __PPC_WC(w))
490 #define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
491 ___PPC_RB(a) | ___PPC_RS(lp))
492 #define PPC_TLBIE_5(rb,rs,ric,prs,r) \
493 stringify_in_c(.long PPC_INST_TLBIE | \
494 ___PPC_RB(rb) | ___PPC_RS(rs) | \
495 ___PPC_RIC(ric) | ___PPC_PRS(prs) | \
496 ___PPC_R(r))
497 #define PPC_TLBIEL(rb,rs,ric,prs,r) \
498 stringify_in_c(.long PPC_INST_TLBIEL | \
499 ___PPC_RB(rb) | ___PPC_RS(rs) | \
500 ___PPC_RIC(ric) | ___PPC_PRS(prs) | \
501 ___PPC_R(r))
502 #define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
503 __PPC_RA0(a) | __PPC_RB(b))
504 #define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
505 __PPC_RA0(a) | __PPC_RB(b))
507 #define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
508 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
509 #define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
510 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
511 #define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
512 __PPC_T_TLB(t) | __PPC_RA0(a) | \
513 __PPC_RB(b))
514 #define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
515 __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
516 #define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
517 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
518 #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
519 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
520 #define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
521 __PPC_RT(t) | __PPC_RB(b))
522 #define __PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
523 ___PPC_RT(t) | ___PPC_RB(b))
524 #define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \
525 __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
526 /* PASemi instructions */
527 #define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \
528 __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
529 #define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \
530 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
532 /*
533 * Define what the VSX XX1 form instructions will look like, then add
534 * the 128 bit load store instructions based on that.
535 */
536 #define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
537 #define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
538 #define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \
539 VSX_XX1((s), a, b))
540 #define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \
541 VSX_XX1((s), a, b))
542 #define MFVRD(a, t) stringify_in_c(.long PPC_INST_MFVSRD | \
543 VSX_XX1((t)+32, a, R0))
544 #define MTVRD(t, a) stringify_in_c(.long PPC_INST_MTVSRD | \
545 VSX_XX1((t)+32, a, R0))
546 #define VPMSUMW(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMW | \
547 VSX_XX3((t), a, b))
548 #define VPMSUMD(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMD | \
549 VSX_XX3((t), a, b))
550 #define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
551 VSX_XX3((t), a, b))
552 #define XXSWAPD(t, a) stringify_in_c(.long PPC_INST_XXSWAPD | \
553 VSX_XX3((t), a, a))
554 #define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
555 VSX_XX3((t), (a), (b))))
557 #define VPERMXOR(vrt, vra, vrb, vrc) \
558 stringify_in_c(.long (PPC_INST_VPERMXOR | \
559 ___PPC_RT(vrt) | ___PPC_RA(vra) | \
560 ___PPC_RB(vrb) | (((vrc) & 0x1f) << 6)))
562 #define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
563 #define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
564 #define PPC_WINKLE stringify_in_c(.long PPC_INST_WINKLE)
566 #define PPC_STOP stringify_in_c(.long PPC_INST_STOP)
568 /* BHRB instructions */
569 #define PPC_CLRBHRB stringify_in_c(.long PPC_INST_CLRBHRB)
570 #define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \
571 __PPC_RT(r) | \
572 (((n) & 0x3ff) << 11))
574 /* Transactional memory instructions */
575 #define TRECHKPT stringify_in_c(.long PPC_INST_TRECHKPT)
576 #define TRECLAIM(r) stringify_in_c(.long PPC_INST_TRECLAIM \
577 | __PPC_RA(r))
578 #define TABORT(r) stringify_in_c(.long PPC_INST_TABORT \
579 | __PPC_RA(r))
581 /* book3e thread control instructions */
582 #define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
583 #define MTTMR(tmr, r) stringify_in_c(.long PPC_INST_MTTMR | \
584 TMRN(tmr) | ___PPC_RS(r))
585 #define MFTMR(tmr, r) stringify_in_c(.long PPC_INST_MFTMR | \
586 TMRN(tmr) | ___PPC_RT(r))
588 /* Coprocessor instructions */
589 #define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_INST_ICSWX | \
590 ___PPC_RS(s) | \
591 ___PPC_RA(a) | \
592 ___PPC_RB(b))
593 #define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_INST_ICSWEPX | \
594 ___PPC_RS(s) | \
595 ___PPC_RA(a) | \
596 ___PPC_RB(b))
598 #define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA | \
599 ((IH & 0x7) << 21))
601 /*
602 * These may only be used on ISA v3.0 or later (aka. CPU_FTR_ARCH_300, radix
603 * implies CPU_FTR_ARCH_300). USER/GUEST invalidates may only be used by radix
604 * mode (on HPT these would also invalidate various SLBEs which may not be
605 * desired).
606 */
607 #define PPC_ISA_3_0_INVALIDATE_ERAT PPC_SLBIA(7)
608 #define PPC_RADIX_INVALIDATE_ERAT_USER PPC_SLBIA(3)
609 #define PPC_RADIX_INVALIDATE_ERAT_GUEST PPC_SLBIA(6)
611 #define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUD | \
612 ___PPC_RT(vrt) | ___PPC_RA(vra) | \
613 ___PPC_RB(vrb) | __PPC_RC21)
615 #define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUB | \
616 ___PPC_RT(vrt) | ___PPC_RA(vra) | \
617 ___PPC_RB(vrb) | __PPC_RC21)