| blob | 4a24f8f026c797b5f83dabb4a06f0ebf896c8365 |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * PowerPC version
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 *
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
12 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 *
14 * This file contains the low-level support and setup for the
15 * PowerPC platform, including trap and interrupt dispatch.
16 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
17 */
19 #include <linux/init.h>
20 #include <asm/reg.h>
21 #include <asm/page.h>
22 #include <asm/mmu.h>
23 #include <asm/pgtable.h>
24 #include <asm/cputable.h>
25 #include <asm/cache.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/ptrace.h>
30 #include <asm/bug.h>
31 #include <asm/kvm_book3s_asm.h>
32 #include <asm/export.h>
33 #include <asm/feature-fixups.h>
35 #include "head_32.h"
37 /* 601 only have IBAT */
38 #ifdef CONFIG_PPC_BOOK3S_601
39 #define LOAD_BAT(n, reg, RA, RB) \
40 li RA,0; \
41 mtspr SPRN_IBAT##n##U,RA; \
42 lwz RA,(n*16)+0(reg); \
43 lwz RB,(n*16)+4(reg); \
44 mtspr SPRN_IBAT##n##U,RA; \
45 mtspr SPRN_IBAT##n##L,RB
46 #else
47 #define LOAD_BAT(n, reg, RA, RB) \
48 /* see the comment for clear_bats() -- Cort */ \
49 li RA,0; \
50 mtspr SPRN_IBAT##n##U,RA; \
51 mtspr SPRN_DBAT##n##U,RA; \
52 lwz RA,(n*16)+0(reg); \
53 lwz RB,(n*16)+4(reg); \
54 mtspr SPRN_IBAT##n##U,RA; \
55 mtspr SPRN_IBAT##n##L,RB; \
56 lwz RA,(n*16)+8(reg); \
57 lwz RB,(n*16)+12(reg); \
58 mtspr SPRN_DBAT##n##U,RA; \
59 mtspr SPRN_DBAT##n##L,RB
60 #endif
62 __HEAD
63 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
64 .stabs "head_32.S",N_SO,0,0,0f
65 0:
66 _ENTRY(_stext);
68 /*
69 * _start is defined this way because the XCOFF loader in the OpenFirmware
70 * on the powermac expects the entry point to be a procedure descriptor.
71 */
72 _ENTRY(_start);
73 /*
74 * These are here for legacy reasons, the kernel used to
75 * need to look like a coff function entry for the pmac
76 * but we're always started by some kind of bootloader now.
77 * -- Cort
78 */
79 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
80 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
81 nop
83 /* PMAC
84 * Enter here with the kernel text, data and bss loaded starting at
85 * 0, running with virtual == physical mapping.
86 * r5 points to the prom entry point (the client interface handler
87 * address). Address translation is turned on, with the prom
88 * managing the hash table. Interrupts are disabled. The stack
89 * pointer (r1) points to just below the end of the half-meg region
90 * from 0x380000 - 0x400000, which is mapped in already.
91 *
92 * If we are booted from MacOS via BootX, we enter with the kernel
93 * image loaded somewhere, and the following values in registers:
94 * r3: 'BooX' (0x426f6f58)
95 * r4: virtual address of boot_infos_t
96 * r5: 0
97 *
98 * PREP
99 * This is jumped to on prep systems right after the kernel is relocated
100 * to its proper place in memory by the boot loader. The expected layout
101 * of the regs is:
102 * r3: ptr to residual data
103 * r4: initrd_start or if no initrd then 0
104 * r5: initrd_end - unused if r4 is 0
105 * r6: Start of command line string
106 * r7: End of command line string
107 *
108 * This just gets a minimal mmu environment setup so we can call
109 * start_here() to do the real work.
110 * -- Cort
111 */
113 .globl __start
114 __start:
115 /*
116 * We have to do any OF calls before we map ourselves to KERNELBASE,
117 * because OF may have I/O devices mapped into that area
118 * (particularly on CHRP).
119 */
120 cmpwi 0,r5,0
121 beq 1f
123 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
124 /* find out where we are now */
125 bcl 20,31,$+4
126 0: mflr r8 /* r8 = runtime addr here */
127 addis r8,r8,(_stext - 0b)@ha
128 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
129 bl prom_init
130 #endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
132 /* We never return. We also hit that trap if trying to boot
133 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
134 trap
136 /*
137 * Check for BootX signature when supporting PowerMac and branch to
138 * appropriate trampoline if it's present
139 */
140 #ifdef CONFIG_PPC_PMAC
141 1: lis r31,0x426f
142 ori r31,r31,0x6f58
143 cmpw 0,r3,r31
144 bne 1f
145 bl bootx_init
146 trap
147 #endif /* CONFIG_PPC_PMAC */
149 1: mr r31,r3 /* save device tree ptr */
150 li r24,0 /* cpu # */
152 /*
153 * early_init() does the early machine identification and does
154 * the necessary low-level setup and clears the BSS
155 * -- Cort <cort@fsmlabs.com>
156 */
157 bl early_init
159 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
160 * the physical address we are running at, returned by early_init()
161 */
162 bl mmu_off
163 __after_mmu_off:
164 bl clear_bats
165 bl flush_tlbs
167 bl initial_bats
168 bl load_segment_registers
169 #ifdef CONFIG_KASAN
170 bl early_hash_table
171 #endif
172 #if defined(CONFIG_BOOTX_TEXT)
173 bl setup_disp_bat
174 #endif
175 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
176 bl setup_cpm_bat
177 #endif
178 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
179 bl setup_usbgecko_bat
180 #endif
182 /*
183 * Call setup_cpu for CPU 0 and initialize 6xx Idle
184 */
185 bl reloc_offset
186 li r24,0 /* cpu# */
187 bl call_setup_cpu /* Call setup_cpu for this CPU */
188 #ifdef CONFIG_PPC_BOOK3S_32
189 bl reloc_offset
190 bl init_idle_6xx
191 #endif /* CONFIG_PPC_BOOK3S_32 */
194 /*
195 * We need to run with _start at physical address 0.
196 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
197 * the exception vectors at 0 (and therefore this copy
198 * overwrites OF's exception vectors with our own).
199 * The MMU is off at this point.
200 */
201 bl reloc_offset
202 mr r26,r3
203 addis r4,r3,KERNELBASE@h /* current address of _start */
204 lis r5,PHYSICAL_START@h
205 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
206 bne relocate_kernel
207 /*
208 * we now have the 1st 16M of ram mapped with the bats.
209 * prep needs the mmu to be turned on here, but pmac already has it on.
210 * this shouldn't bother the pmac since it just gets turned on again
211 * as we jump to our code at KERNELBASE. -- Cort
212 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
213 * off, and in other cases, we now turn it off before changing BATs above.
214 */
215 turn_on_mmu:
216 mfmsr r0
217 ori r0,r0,MSR_DR|MSR_IR|MSR_RI
218 mtspr SPRN_SRR1,r0
219 lis r0,start_here@h
220 ori r0,r0,start_here@l
221 mtspr SPRN_SRR0,r0
222 SYNC
223 RFI /* enables MMU */
225 /*
226 * We need __secondary_hold as a place to hold the other cpus on
227 * an SMP machine, even when we are running a UP kernel.
228 */
229 . = 0xc0 /* for prep bootloader */
230 li r3,1 /* MTX only has 1 cpu */
231 .globl __secondary_hold
232 __secondary_hold:
233 /* tell the master we're here */
234 stw r3,__secondary_hold_acknowledge@l(0)
235 #ifdef CONFIG_SMP
236 100: lwz r4,0(0)
237 /* wait until we're told to start */
238 cmpw 0,r4,r3
239 bne 100b
240 /* our cpu # was at addr 0 - go */
241 mr r24,r3 /* cpu # */
242 b __secondary_start
243 #else
244 b .
245 #endif /* CONFIG_SMP */
247 .globl __secondary_hold_spinloop
248 __secondary_hold_spinloop:
249 .long 0
250 .globl __secondary_hold_acknowledge
251 __secondary_hold_acknowledge:
252 .long -1
254 /* System reset */
255 /* core99 pmac starts the seconary here by changing the vector, and
256 putting it back to what it was (unknown_exception) when done. */
257 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
259 /* Machine check */
260 /*
261 * On CHRP, this is complicated by the fact that we could get a
262 * machine check inside RTAS, and we have no guarantee that certain
263 * critical registers will have the values we expect. The set of
264 * registers that might have bad values includes all the GPRs
265 * and all the BATs. We indicate that we are in RTAS by putting
266 * a non-zero value, the address of the exception frame to use,
267 * in thread.rtas_sp. The machine check handler checks thread.rtas_sp
268 * and uses its value if it is non-zero.
269 * (Other exception handlers assume that r1 is a valid kernel stack
270 * pointer when we take an exception from supervisor mode.)
271 * -- paulus.
272 */
273 . = 0x200
274 DO_KVM 0x200
275 mtspr SPRN_SPRG_SCRATCH0,r10
276 mtspr SPRN_SPRG_SCRATCH1,r11
277 mfcr r10
278 #ifdef CONFIG_PPC_CHRP
279 mfspr r11, SPRN_SPRG_THREAD
280 lwz r11, RTAS_SP(r11)
281 cmpwi cr1, r11, 0
282 bne cr1, 7f
283 #endif /* CONFIG_PPC_CHRP */
284 EXCEPTION_PROLOG_1
285 7: EXCEPTION_PROLOG_2
286 addi r3,r1,STACK_FRAME_OVERHEAD
287 #ifdef CONFIG_PPC_CHRP
288 bne cr1,1f
289 #endif
290 EXC_XFER_STD(0x200, machine_check_exception)
291 #ifdef CONFIG_PPC_CHRP
292 1: b machine_check_in_rtas
293 #endif
295 /* Data access exception. */
296 . = 0x300
297 DO_KVM 0x300
298 DataAccess:
299 EXCEPTION_PROLOG
300 mfspr r10,SPRN_DSISR
301 stw r10,_DSISR(r11)
302 #ifdef CONFIG_PPC_KUAP
303 andis. r0,r10,(DSISR_BAD_FAULT_32S | DSISR_DABRMATCH | DSISR_PROTFAULT)@h
304 #else
305 andis. r0,r10,(DSISR_BAD_FAULT_32S|DSISR_DABRMATCH)@h
306 #endif
307 bne 1f /* if not, try to put a PTE */
308 mfspr r4,SPRN_DAR /* into the hash table */
309 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
310 BEGIN_MMU_FTR_SECTION
311 bl hash_page
312 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
313 1: lwz r5,_DSISR(r11) /* get DSISR value */
314 mfspr r4,SPRN_DAR
315 EXC_XFER_LITE(0x300, handle_page_fault)
318 /* Instruction access exception. */
319 . = 0x400
320 DO_KVM 0x400
321 InstructionAccess:
322 EXCEPTION_PROLOG
323 andis. r0,r9,SRR1_ISI_NOPT@h /* no pte found? */
324 beq 1f /* if so, try to put a PTE */
325 li r3,0 /* into the hash table */
326 mr r4,r12 /* SRR0 is fault address */
327 BEGIN_MMU_FTR_SECTION
328 bl hash_page
329 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
330 1: mr r4,r12
331 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
332 EXC_XFER_LITE(0x400, handle_page_fault)
334 /* External interrupt */
335 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
337 /* Alignment exception */
338 . = 0x600
339 DO_KVM 0x600
340 Alignment:
341 EXCEPTION_PROLOG
342 mfspr r4,SPRN_DAR
343 stw r4,_DAR(r11)
344 mfspr r5,SPRN_DSISR
345 stw r5,_DSISR(r11)
346 addi r3,r1,STACK_FRAME_OVERHEAD
347 EXC_XFER_STD(0x600, alignment_exception)
349 /* Program check exception */
350 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
352 /* Floating-point unavailable */
353 . = 0x800
354 DO_KVM 0x800
355 FPUnavailable:
356 BEGIN_FTR_SECTION
357 /*
358 * Certain Freescale cores don't have a FPU and treat fp instructions
359 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
360 */
361 b ProgramCheck
362 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
363 EXCEPTION_PROLOG
364 beq 1f
365 bl load_up_fpu /* if from user, just load it up */
366 b fast_exception_return
367 1: addi r3,r1,STACK_FRAME_OVERHEAD
368 EXC_XFER_LITE(0x800, kernel_fp_unavailable_exception)
370 /* Decrementer */
371 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
373 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_STD)
374 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_STD)
376 /* System call */
377 . = 0xc00
378 DO_KVM 0xc00
379 SystemCall:
380 SYSCALL_ENTRY 0xc00
382 /* Single step - not used on 601 */
383 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
384 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_STD)
386 /*
387 * The Altivec unavailable trap is at 0x0f20. Foo.
388 * We effectively remap it to 0x3000.
389 * We include an altivec unavailable exception vector even if
390 * not configured for Altivec, so that you can't panic a
391 * non-altivec kernel running on a machine with altivec just
392 * by executing an altivec instruction.
393 */
394 . = 0xf00
395 DO_KVM 0xf00
396 b PerformanceMonitor
398 . = 0xf20
399 DO_KVM 0xf20
400 b AltiVecUnavailable
402 /*
403 * Handle TLB miss for instruction on 603/603e.
404 * Note: we get an alternate set of r0 - r3 to use automatically.
405 */
406 . = 0x1000
407 InstructionTLBMiss:
408 /*
409 * r0: scratch
410 * r1: linux style pte ( later becomes ppc hardware pte )
411 * r2: ptr to linux-style pte
412 * r3: scratch
413 */
414 /* Get PTE (linux-style) and check access */
415 mfspr r3,SPRN_IMISS
416 #if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
417 lis r1,PAGE_OFFSET@h /* check if kernel address */
418 cmplw 0,r1,r3
419 #endif
420 mfspr r2, SPRN_SPRG_PGDIR
421 #ifdef CONFIG_SWAP
422 li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
423 #else
424 li r1,_PAGE_PRESENT | _PAGE_EXEC
425 #endif
426 #if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
427 bge- 112f
428 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
429 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
430 #endif
431 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
432 lwz r2,0(r2) /* get pmd entry */
433 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
434 beq- InstructionAddressInvalid /* return if no mapping */
435 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
436 lwz r0,0(r2) /* get linux-style pte */
437 andc. r1,r1,r0 /* check access & ~permission */
438 bne- InstructionAddressInvalid /* return if access not permitted */
439 /* Convert linux-style PTE to low word of PPC-style PTE */
440 rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
441 ori r1, r1, 0xe06 /* clear out reserved bits */
442 andc r1, r0, r1 /* PP = user? 1 : 0 */
443 BEGIN_FTR_SECTION
444 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
445 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
446 mtspr SPRN_RPA,r1
447 tlbli r3
448 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
449 mtcrf 0x80,r3
450 rfi
451 InstructionAddressInvalid:
452 mfspr r3,SPRN_SRR1
453 rlwinm r1,r3,9,6,6 /* Get load/store bit */
455 addis r1,r1,0x2000
456 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
457 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
458 or r2,r2,r1
459 mtspr SPRN_SRR1,r2
460 mfspr r1,SPRN_IMISS /* Get failing address */
461 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
462 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
463 xor r1,r1,r2
464 mtspr SPRN_DAR,r1 /* Set fault address */
465 mfmsr r0 /* Restore "normal" registers */
466 xoris r0,r0,MSR_TGPR>>16
467 mtcrf 0x80,r3 /* Restore CR0 */
468 mtmsr r0
469 b InstructionAccess
471 /*
472 * Handle TLB miss for DATA Load operation on 603/603e
473 */
474 . = 0x1100
475 DataLoadTLBMiss:
476 /*
477 * r0: scratch
478 * r1: linux style pte ( later becomes ppc hardware pte )
479 * r2: ptr to linux-style pte
480 * r3: scratch
481 */
482 /* Get PTE (linux-style) and check access */
483 mfspr r3,SPRN_DMISS
484 lis r1,PAGE_OFFSET@h /* check if kernel address */
485 cmplw 0,r1,r3
486 mfspr r2, SPRN_SPRG_PGDIR
487 #ifdef CONFIG_SWAP
488 li r1, _PAGE_PRESENT | _PAGE_ACCESSED
489 #else
490 li r1, _PAGE_PRESENT
491 #endif
492 bge- 112f
493 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
494 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
495 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
496 lwz r2,0(r2) /* get pmd entry */
497 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
498 beq- DataAddressInvalid /* return if no mapping */
499 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
500 lwz r0,0(r2) /* get linux-style pte */
501 andc. r1,r1,r0 /* check access & ~permission */
502 bne- DataAddressInvalid /* return if access not permitted */
503 /*
504 * NOTE! We are assuming this is not an SMP system, otherwise
505 * we would need to update the pte atomically with lwarx/stwcx.
506 */
507 /* Convert linux-style PTE to low word of PPC-style PTE */
508 rlwinm r1,r0,32-9,30,30 /* _PAGE_RW -> PP msb */
509 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
510 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
511 ori r1,r1,0xe04 /* clear out reserved bits */
512 andc r1,r0,r1 /* PP = user? rw? 1: 3: 0 */
513 BEGIN_FTR_SECTION
514 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
515 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
516 mtspr SPRN_RPA,r1
517 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
518 mtcrf 0x80,r2
519 BEGIN_MMU_FTR_SECTION
520 li r0,1
521 mfspr r1,SPRN_SPRG_603_LRU
522 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
523 slw r0,r0,r2
524 xor r1,r0,r1
525 srw r0,r1,r2
526 mtspr SPRN_SPRG_603_LRU,r1
527 mfspr r2,SPRN_SRR1
528 rlwimi r2,r0,31-14,14,14
529 mtspr SPRN_SRR1,r2
530 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
531 tlbld r3
532 rfi
533 DataAddressInvalid:
534 mfspr r3,SPRN_SRR1
535 rlwinm r1,r3,9,6,6 /* Get load/store bit */
536 addis r1,r1,0x2000
537 mtspr SPRN_DSISR,r1
538 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
539 mtspr SPRN_SRR1,r2
540 mfspr r1,SPRN_DMISS /* Get failing address */
541 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
542 beq 20f /* Jump if big endian */
543 xori r1,r1,3
544 20: mtspr SPRN_DAR,r1 /* Set fault address */
545 mfmsr r0 /* Restore "normal" registers */
546 xoris r0,r0,MSR_TGPR>>16
547 mtcrf 0x80,r3 /* Restore CR0 */
548 mtmsr r0
549 b DataAccess
551 /*
552 * Handle TLB miss for DATA Store on 603/603e
553 */
554 . = 0x1200
555 DataStoreTLBMiss:
556 /*
557 * r0: scratch
558 * r1: linux style pte ( later becomes ppc hardware pte )
559 * r2: ptr to linux-style pte
560 * r3: scratch
561 */
562 /* Get PTE (linux-style) and check access */
563 mfspr r3,SPRN_DMISS
564 lis r1,PAGE_OFFSET@h /* check if kernel address */
565 cmplw 0,r1,r3
566 mfspr r2, SPRN_SPRG_PGDIR
567 #ifdef CONFIG_SWAP
568 li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
569 #else
570 li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT
571 #endif
572 bge- 112f
573 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
574 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
575 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
576 lwz r2,0(r2) /* get pmd entry */
577 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
578 beq- DataAddressInvalid /* return if no mapping */
579 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
580 lwz r0,0(r2) /* get linux-style pte */
581 andc. r1,r1,r0 /* check access & ~permission */
582 bne- DataAddressInvalid /* return if access not permitted */
583 /*
584 * NOTE! We are assuming this is not an SMP system, otherwise
585 * we would need to update the pte atomically with lwarx/stwcx.
586 */
587 /* Convert linux-style PTE to low word of PPC-style PTE */
588 rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
589 li r1,0xe06 /* clear out reserved bits & PP msb */
590 andc r1,r0,r1 /* PP = user? 1: 0 */
591 BEGIN_FTR_SECTION
592 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
593 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
594 mtspr SPRN_RPA,r1
595 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
596 mtcrf 0x80,r2
597 BEGIN_MMU_FTR_SECTION
598 li r0,1
599 mfspr r1,SPRN_SPRG_603_LRU
600 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
601 slw r0,r0,r2
602 xor r1,r0,r1
603 srw r0,r1,r2
604 mtspr SPRN_SPRG_603_LRU,r1
605 mfspr r2,SPRN_SRR1
606 rlwimi r2,r0,31-14,14,14
607 mtspr SPRN_SRR1,r2
608 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
609 tlbld r3
610 rfi
612 #ifndef CONFIG_ALTIVEC
613 #define altivec_assist_exception unknown_exception
614 #endif
616 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_STD)
617 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_STD)
618 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD)
619 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_STD)
620 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
621 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD)
622 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD)
623 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_STD)
624 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_STD)
625 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_STD)
626 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_STD)
627 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_STD)
628 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_STD)
629 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_STD)
630 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_STD)
631 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_STD)
632 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_STD)
633 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_STD)
634 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_STD)
635 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_STD)
636 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_STD)
637 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_STD)
638 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_STD)
639 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_STD)
640 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_STD)
641 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_STD)
642 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_STD)
643 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_STD)
644 EXCEPTION(0x2f00, Trap_2f, unknown_exception, EXC_XFER_STD)
646 . = 0x3000
648 AltiVecUnavailable:
649 EXCEPTION_PROLOG
650 #ifdef CONFIG_ALTIVEC
651 beq 1f
652 bl load_up_altivec /* if from user, just load it up */
653 b fast_exception_return
654 #endif /* CONFIG_ALTIVEC */
655 1: addi r3,r1,STACK_FRAME_OVERHEAD
656 EXC_XFER_LITE(0xf20, altivec_unavailable_exception)
658 PerformanceMonitor:
659 EXCEPTION_PROLOG
660 addi r3,r1,STACK_FRAME_OVERHEAD
661 EXC_XFER_STD(0xf00, performance_monitor_exception)
664 /*
665 * This code is jumped to from the startup code to copy
666 * the kernel image to physical address PHYSICAL_START.
667 */
668 relocate_kernel:
669 addis r9,r26,klimit@ha /* fetch klimit */
670 lwz r25,klimit@l(r9)
671 addis r25,r25,-KERNELBASE@h
672 lis r3,PHYSICAL_START@h /* Destination base address */
673 li r6,0 /* Destination offset */
674 li r5,0x4000 /* # bytes of memory to copy */
675 bl copy_and_flush /* copy the first 0x4000 bytes */
676 addi r0,r3,4f@l /* jump to the address of 4f */
677 mtctr r0 /* in copy and do the rest. */
678 bctr /* jump to the copy */
679 4: mr r5,r25
680 bl copy_and_flush /* copy the rest */
681 b turn_on_mmu
683 /*
684 * Copy routine used to copy the kernel to start at physical address 0
685 * and flush and invalidate the caches as needed.
686 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
687 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
688 */
689 _ENTRY(copy_and_flush)
690 addi r5,r5,-4
691 addi r6,r6,-4
692 4: li r0,L1_CACHE_BYTES/4
693 mtctr r0
694 3: addi r6,r6,4 /* copy a cache line */
695 lwzx r0,r6,r4
696 stwx r0,r6,r3
697 bdnz 3b
698 dcbst r6,r3 /* write it to memory */
699 sync
700 icbi r6,r3 /* flush the icache line */
701 cmplw 0,r6,r5
702 blt 4b
703 sync /* additional sync needed on g4 */
704 isync
705 addi r5,r5,4
706 addi r6,r6,4
707 blr
709 #ifdef CONFIG_SMP
710 .globl __secondary_start_mpc86xx
711 __secondary_start_mpc86xx:
712 mfspr r3, SPRN_PIR
713 stw r3, __secondary_hold_acknowledge@l(0)
714 mr r24, r3 /* cpu # */
715 b __secondary_start
717 .globl __secondary_start_pmac_0
718 __secondary_start_pmac_0:
719 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
720 li r24,0
721 b 1f
722 li r24,1
723 b 1f
724 li r24,2
725 b 1f
726 li r24,3
727 1:
728 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
729 set to map the 0xf0000000 - 0xffffffff region */
730 mfmsr r0
731 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
732 SYNC
733 mtmsr r0
734 isync
736 .globl __secondary_start
737 __secondary_start:
738 /* Copy some CPU settings from CPU 0 */
739 bl __restore_cpu_setup
741 lis r3,-KERNELBASE@h
742 mr r4,r24
743 bl call_setup_cpu /* Call setup_cpu for this CPU */
744 #ifdef CONFIG_PPC_BOOK3S_32
745 lis r3,-KERNELBASE@h
746 bl init_idle_6xx
747 #endif /* CONFIG_PPC_BOOK3S_32 */
749 /* get current's stack and current */
750 lis r2,secondary_current@ha
751 tophys(r2,r2)
752 lwz r2,secondary_current@l(r2)
753 tophys(r1,r2)
754 lwz r1,TASK_STACK(r1)
756 /* stack */
757 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
758 li r0,0
759 tophys(r3,r1)
760 stw r0,0(r3)
762 /* load up the MMU */
763 bl load_segment_registers
764 bl load_up_mmu
766 /* ptr to phys current thread */
767 tophys(r4,r2)
768 addi r4,r4,THREAD /* phys address of our thread_struct */
769 mtspr SPRN_SPRG_THREAD,r4
770 lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
771 ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
772 mtspr SPRN_SPRG_PGDIR, r4
774 /* enable MMU and jump to start_secondary */
775 li r4,MSR_KERNEL
776 lis r3,start_secondary@h
777 ori r3,r3,start_secondary@l
778 mtspr SPRN_SRR0,r3
779 mtspr SPRN_SRR1,r4
780 SYNC
781 RFI
782 #endif /* CONFIG_SMP */
784 #ifdef CONFIG_KVM_BOOK3S_HANDLER
785 #include "../kvm/book3s_rmhandlers.S"
786 #endif
788 /*
789 * Those generic dummy functions are kept for CPUs not
790 * included in CONFIG_PPC_BOOK3S_32
791 */
792 #if !defined(CONFIG_PPC_BOOK3S_32)
793 _ENTRY(__save_cpu_setup)
794 blr
795 _ENTRY(__restore_cpu_setup)
796 blr
797 #endif /* !defined(CONFIG_PPC_BOOK3S_32) */
799 /*
800 * Load stuff into the MMU. Intended to be called with
801 * IR=0 and DR=0.
802 */
803 #ifdef CONFIG_KASAN
804 early_hash_table:
805 sync /* Force all PTE updates to finish */
806 isync
807 tlbia /* Clear all TLB entries */
808 sync /* wait for tlbia/tlbie to finish */
809 TLBSYNC /* ... on all CPUs */
810 /* Load the SDR1 register (hash table base & size) */
811 lis r6, early_hash - PAGE_OFFSET@h
812 ori r6, r6, 3 /* 256kB table */
813 mtspr SPRN_SDR1, r6
814 blr
815 #endif
817 load_up_mmu:
818 sync /* Force all PTE updates to finish */
819 isync
820 tlbia /* Clear all TLB entries */
821 sync /* wait for tlbia/tlbie to finish */
822 TLBSYNC /* ... on all CPUs */
823 /* Load the SDR1 register (hash table base & size) */
824 lis r6,_SDR1@ha
825 tophys(r6,r6)
826 lwz r6,_SDR1@l(r6)
827 mtspr SPRN_SDR1,r6
829 /* Load the BAT registers with the values set up by MMU_init.
830 MMU_init takes care of whether we're on a 601 or not. */
831 lis r3,BATS@ha
832 addi r3,r3,BATS@l
833 tophys(r3,r3)
834 LOAD_BAT(0,r3,r4,r5)
835 LOAD_BAT(1,r3,r4,r5)
836 LOAD_BAT(2,r3,r4,r5)
837 LOAD_BAT(3,r3,r4,r5)
838 BEGIN_MMU_FTR_SECTION
839 LOAD_BAT(4,r3,r4,r5)
840 LOAD_BAT(5,r3,r4,r5)
841 LOAD_BAT(6,r3,r4,r5)
842 LOAD_BAT(7,r3,r4,r5)
843 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
844 blr
846 load_segment_registers:
847 li r0, NUM_USER_SEGMENTS /* load up user segment register values */
848 mtctr r0 /* for context 0 */
849 li r3, 0 /* Kp = 0, Ks = 0, VSID = 0 */
850 #ifdef CONFIG_PPC_KUEP
851 oris r3, r3, SR_NX@h /* Set Nx */
852 #endif
853 #ifdef CONFIG_PPC_KUAP
854 oris r3, r3, SR_KS@h /* Set Ks */
855 #endif
856 li r4, 0
857 3: mtsrin r3, r4
858 addi r3, r3, 0x111 /* increment VSID */
859 addis r4, r4, 0x1000 /* address of next segment */
860 bdnz 3b
861 li r0, 16 - NUM_USER_SEGMENTS /* load up kernel segment registers */
862 mtctr r0 /* for context 0 */
863 rlwinm r3, r3, 0, ~SR_NX /* Nx = 0 */
864 rlwinm r3, r3, 0, ~SR_KS /* Ks = 0 */
865 oris r3, r3, SR_KP@h /* Kp = 1 */
866 3: mtsrin r3, r4
867 addi r3, r3, 0x111 /* increment VSID */
868 addis r4, r4, 0x1000 /* address of next segment */
869 bdnz 3b
870 blr
872 /*
873 * This is where the main kernel code starts.
874 */
875 start_here:
876 /* ptr to current */
877 lis r2,init_task@h
878 ori r2,r2,init_task@l
879 /* Set up for using our exception vectors */
880 /* ptr to phys current thread */
881 tophys(r4,r2)
882 addi r4,r4,THREAD /* init task's THREAD */
883 mtspr SPRN_SPRG_THREAD,r4
884 lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
885 ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
886 mtspr SPRN_SPRG_PGDIR, r4
888 /* stack */
889 lis r1,init_thread_union@ha
890 addi r1,r1,init_thread_union@l
891 li r0,0
892 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
893 /*
894 * Do early platform-specific initialization,
895 * and set up the MMU.
896 */
897 #ifdef CONFIG_KASAN
898 bl kasan_early_init
899 #endif
900 li r3,0
901 mr r4,r31
902 bl machine_init
903 bl __save_cpu_setup
904 bl MMU_init
905 #ifdef CONFIG_KASAN
906 BEGIN_MMU_FTR_SECTION
907 bl MMU_init_hw_patch
908 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
909 #endif
911 /*
912 * Go back to running unmapped so we can load up new values
913 * for SDR1 (hash table pointer) and the segment registers
914 * and change to using our exception vectors.
915 */
916 lis r4,2f@h
917 ori r4,r4,2f@l
918 tophys(r4,r4)
919 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
920 mtspr SPRN_SRR0,r4
921 mtspr SPRN_SRR1,r3
922 SYNC
923 RFI
924 /* Load up the kernel context */
925 2: bl load_up_mmu
927 #ifdef CONFIG_BDI_SWITCH
928 /* Add helper information for the Abatron bdiGDB debugger.
929 * We do this here because we know the mmu is disabled, and
930 * will be enabled for real in just a few instructions.
931 */
932 lis r5, abatron_pteptrs@h
933 ori r5, r5, abatron_pteptrs@l
934 stw r5, 0xf0(r0) /* This much match your Abatron config */
935 lis r6, swapper_pg_dir@h
936 ori r6, r6, swapper_pg_dir@l
937 tophys(r5, r5)
938 stw r6, 0(r5)
939 #endif /* CONFIG_BDI_SWITCH */
941 /* Now turn on the MMU for real! */
942 li r4,MSR_KERNEL
943 lis r3,start_kernel@h
944 ori r3,r3,start_kernel@l
945 mtspr SPRN_SRR0,r3
946 mtspr SPRN_SRR1,r4
947 SYNC
948 RFI
950 /*
951 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
952 *
953 * Set up the segment registers for a new context.
954 */
955 _ENTRY(switch_mmu_context)
956 lwz r3,MMCONTEXTID(r4)
957 cmpwi cr0,r3,0
958 blt- 4f
959 mulli r3,r3,897 /* multiply context by skew factor */
960 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
961 #ifdef CONFIG_PPC_KUEP
962 oris r3, r3, SR_NX@h /* Set Nx */
963 #endif
964 #ifdef CONFIG_PPC_KUAP
965 oris r3, r3, SR_KS@h /* Set Ks */
966 #endif
967 li r0,NUM_USER_SEGMENTS
968 mtctr r0
970 lwz r4, MM_PGD(r4)
971 #ifdef CONFIG_BDI_SWITCH
972 /* Context switch the PTE pointer for the Abatron BDI2000.
973 * The PGDIR is passed as second argument.
974 */
975 lis r5, abatron_pteptrs@ha
976 stw r4, abatron_pteptrs@l + 0x4(r5)
977 #endif
978 tophys(r4, r4)
979 mtspr SPRN_SPRG_PGDIR, r4
980 li r4,0
981 isync
982 3:
983 mtsrin r3,r4
984 addi r3,r3,0x111 /* next VSID */
985 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
986 addis r4,r4,0x1000 /* address of next segment */
987 bdnz 3b
988 sync
989 isync
990 blr
991 4: trap
992 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
993 blr
994 EXPORT_SYMBOL(switch_mmu_context)
996 /*
997 * An undocumented "feature" of 604e requires that the v bit
998 * be cleared before changing BAT values.
999 *
1000 * Also, newer IBM firmware does not clear bat3 and 4 so
1001 * this makes sure it's done.
1002 * -- Cort
1003 */
1004 clear_bats:
1005 li r10,0
1007 #ifndef CONFIG_PPC_BOOK3S_601
1008 mtspr SPRN_DBAT0U,r10
1009 mtspr SPRN_DBAT0L,r10
1010 mtspr SPRN_DBAT1U,r10
1011 mtspr SPRN_DBAT1L,r10
1012 mtspr SPRN_DBAT2U,r10
1013 mtspr SPRN_DBAT2L,r10
1014 mtspr SPRN_DBAT3U,r10
1015 mtspr SPRN_DBAT3L,r10
1016 #endif
1017 mtspr SPRN_IBAT0U,r10
1018 mtspr SPRN_IBAT0L,r10
1019 mtspr SPRN_IBAT1U,r10
1020 mtspr SPRN_IBAT1L,r10
1021 mtspr SPRN_IBAT2U,r10
1022 mtspr SPRN_IBAT2L,r10
1023 mtspr SPRN_IBAT3U,r10
1024 mtspr SPRN_IBAT3L,r10
1025 BEGIN_MMU_FTR_SECTION
1026 /* Here's a tweak: at this point, CPU setup have
1027 * not been called yet, so HIGH_BAT_EN may not be
1028 * set in HID0 for the 745x processors. However, it
1029 * seems that doesn't affect our ability to actually
1030 * write to these SPRs.
1031 */
1032 mtspr SPRN_DBAT4U,r10
1033 mtspr SPRN_DBAT4L,r10
1034 mtspr SPRN_DBAT5U,r10
1035 mtspr SPRN_DBAT5L,r10
1036 mtspr SPRN_DBAT6U,r10
1037 mtspr SPRN_DBAT6L,r10
1038 mtspr SPRN_DBAT7U,r10
1039 mtspr SPRN_DBAT7L,r10
1040 mtspr SPRN_IBAT4U,r10
1041 mtspr SPRN_IBAT4L,r10
1042 mtspr SPRN_IBAT5U,r10
1043 mtspr SPRN_IBAT5L,r10
1044 mtspr SPRN_IBAT6U,r10
1045 mtspr SPRN_IBAT6L,r10
1046 mtspr SPRN_IBAT7U,r10
1047 mtspr SPRN_IBAT7L,r10
1048 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1049 blr
1051 _ENTRY(update_bats)
1052 lis r4, 1f@h
1053 ori r4, r4, 1f@l
1054 tophys(r4, r4)
1055 mfmsr r6
1056 mflr r7
1057 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR)
1058 rlwinm r0, r6, 0, ~MSR_RI
1059 rlwinm r0, r0, 0, ~MSR_EE
1060 mtmsr r0
1061 mtspr SPRN_SRR0, r4
1062 mtspr SPRN_SRR1, r3
1063 SYNC
1064 RFI
1065 1: bl clear_bats
1066 lis r3, BATS@ha
1067 addi r3, r3, BATS@l
1068 tophys(r3, r3)
1069 LOAD_BAT(0, r3, r4, r5)
1070 LOAD_BAT(1, r3, r4, r5)
1071 LOAD_BAT(2, r3, r4, r5)
1072 LOAD_BAT(3, r3, r4, r5)
1073 BEGIN_MMU_FTR_SECTION
1074 LOAD_BAT(4, r3, r4, r5)
1075 LOAD_BAT(5, r3, r4, r5)
1076 LOAD_BAT(6, r3, r4, r5)
1077 LOAD_BAT(7, r3, r4, r5)
1078 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1079 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
1080 mtmsr r3
1081 mtspr SPRN_SRR0, r7
1082 mtspr SPRN_SRR1, r6
1083 SYNC
1084 RFI
1086 flush_tlbs:
1087 lis r10, 0x40
1088 1: addic. r10, r10, -0x1000
1089 tlbie r10
1090 bgt 1b
1091 sync
1092 blr
1094 mmu_off:
1095 addi r4, r3, __after_mmu_off - _start
1096 mfmsr r3
1097 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1098 beqlr
1099 andc r3,r3,r0
1100 mtspr SPRN_SRR0,r4
1101 mtspr SPRN_SRR1,r3
1102 sync
1103 RFI
1105 /*
1106 * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET
1107 * (we keep one for debugging) and on others, we use one 256M BAT.
1108 */
1109 initial_bats:
1110 lis r11,PAGE_OFFSET@h
1111 #ifdef CONFIG_PPC_BOOK3S_601
1112 ori r11,r11,4 /* set up BAT registers for 601 */
1113 li r8,0x7f /* valid, block length = 8MB */
1114 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1115 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1116 addis r11,r11,0x800000@h
1117 addis r8,r8,0x800000@h
1118 mtspr SPRN_IBAT1U,r11
1119 mtspr SPRN_IBAT1L,r8
1120 addis r11,r11,0x800000@h
1121 addis r8,r8,0x800000@h
1122 mtspr SPRN_IBAT2U,r11
1123 mtspr SPRN_IBAT2L,r8
1124 #else
1125 tophys(r8,r11)
1126 #ifdef CONFIG_SMP
1127 ori r8,r8,0x12 /* R/W access, M=1 */
1128 #else
1129 ori r8,r8,2 /* R/W access */
1130 #endif /* CONFIG_SMP */
1131 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1133 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1134 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1135 mtspr SPRN_IBAT0L,r8
1136 mtspr SPRN_IBAT0U,r11
1137 #endif
1138 isync
1139 blr
1141 #ifdef CONFIG_BOOTX_TEXT
1142 setup_disp_bat:
1143 /*
1144 * setup the display bat prepared for us in prom.c
1145 */
1146 mflr r8
1147 bl reloc_offset
1148 mtlr r8
1149 addis r8,r3,disp_BAT@ha
1150 addi r8,r8,disp_BAT@l
1151 cmpwi cr0,r8,0
1152 beqlr
1153 lwz r11,0(r8)
1154 lwz r8,4(r8)
1155 #ifndef CONFIG_PPC_BOOK3S_601
1156 mtspr SPRN_DBAT3L,r8
1157 mtspr SPRN_DBAT3U,r11
1158 #else
1159 mtspr SPRN_IBAT3L,r8
1160 mtspr SPRN_IBAT3U,r11
1161 #endif
1162 blr
1163 #endif /* CONFIG_BOOTX_TEXT */
1165 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1166 setup_cpm_bat:
1167 lis r8, 0xf000
1168 ori r8, r8, 0x002a
1169 mtspr SPRN_DBAT1L, r8
1171 lis r11, 0xf000
1172 ori r11, r11, (BL_1M << 2) | 2
1173 mtspr SPRN_DBAT1U, r11
1175 blr
1176 #endif
1178 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
1179 setup_usbgecko_bat:
1180 /* prepare a BAT for early io */
1181 #if defined(CONFIG_GAMECUBE)
1182 lis r8, 0x0c00
1183 #elif defined(CONFIG_WII)
1184 lis r8, 0x0d00
1185 #else
1186 #error Invalid platform for USB Gecko based early debugging.
1187 #endif
1188 /*
1189 * The virtual address used must match the virtual address
1190 * associated to the fixmap entry FIX_EARLY_DEBUG_BASE.
1191 */
1192 lis r11, 0xfffe /* top 128K */
1193 ori r8, r8, 0x002a /* uncached, guarded ,rw */
1194 ori r11, r11, 0x2 /* 128K, Vs=1, Vp=0 */
1195 mtspr SPRN_DBAT1L, r8
1196 mtspr SPRN_DBAT1U, r11
1197 blr
1198 #endif
1200 #ifdef CONFIG_8260
1201 /* Jump into the system reset for the rom.
1202 * We first disable the MMU, and then jump to the ROM reset address.
1203 *
1204 * r3 is the board info structure, r4 is the location for starting.
1205 * I use this for building a small kernel that can load other kernels,
1206 * rather than trying to write or rely on a rom monitor that can tftp load.
1207 */
1208 .globl m8260_gorom
1209 m8260_gorom:
1210 mfmsr r0
1211 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1212 sync
1213 mtmsr r0
1214 sync
1215 mfspr r11, SPRN_HID0
1216 lis r10, 0
1217 ori r10,r10,HID0_ICE|HID0_DCE
1218 andc r11, r11, r10
1219 mtspr SPRN_HID0, r11
1220 isync
1221 li r5, MSR_ME|MSR_RI
1222 lis r6,2f@h
1223 addis r6,r6,-KERNELBASE@h
1224 ori r6,r6,2f@l
1225 mtspr SPRN_SRR0,r6
1226 mtspr SPRN_SRR1,r5
1227 isync
1228 sync
1229 rfi
1230 2:
1231 mtlr r4
1232 blr
1233 #endif
1236 /*
1237 * We put a few things here that have to be page-aligned.
1238 * This stuff goes at the beginning of the data segment,
1239 * which is page-aligned.
1240 */
1241 .data
1242 .globl sdata
1243 sdata:
1244 .globl empty_zero_page
1245 empty_zero_page:
1246 .space 4096
1247 EXPORT_SYMBOL(empty_zero_page)
1249 .globl swapper_pg_dir
1250 swapper_pg_dir:
1251 .space PGD_TABLE_SIZE
1253 /* Room for two PTE pointers, usually the kernel and current user pointers
1254 * to their respective root page table.
1255 */
1256 abatron_pteptrs:
1257 .space 8