| blob | 6f7a3a7162c524195adbcacebeb8fa15e75e7a38 |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Kernel execution entry point code.
4 *
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
6 * Initial PowerPC version.
7 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Rewritten for PReP
9 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
10 * Low-level exception handers, MMU support, and rewrite.
11 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
12 * PowerPC 8xx modifications.
13 * Copyright (c) 1998-1999 TiVo, Inc.
14 * PowerPC 403GCX modifications.
15 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
16 * PowerPC 403GCX/405GP modifications.
17 * Copyright 2000 MontaVista Software Inc.
18 * PPC405 modifications
19 * PowerPC 403GCX/405GP modifications.
20 * Author: MontaVista Software, Inc.
21 * frank_rowand@mvista.com or source@mvista.com
22 * debbie_chu@mvista.com
23 * Copyright 2002-2004 MontaVista Software, Inc.
24 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
25 * Copyright 2004 Freescale Semiconductor, Inc
26 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
27 */
29 #include <linux/init.h>
30 #include <linux/threads.h>
31 #include <asm/processor.h>
32 #include <asm/page.h>
33 #include <asm/mmu.h>
34 #include <asm/pgtable.h>
35 #include <asm/cputable.h>
36 #include <asm/thread_info.h>
37 #include <asm/ppc_asm.h>
38 #include <asm/asm-offsets.h>
39 #include <asm/cache.h>
40 #include <asm/ptrace.h>
41 #include <asm/export.h>
42 #include <asm/feature-fixups.h>
43 #include "head_booke.h"
45 /* As with the other PowerPC ports, it is expected that when code
46 * execution begins here, the following registers contain valid, yet
47 * optional, information:
48 *
49 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
50 * r4 - Starting address of the init RAM disk
51 * r5 - Ending address of the init RAM disk
52 * r6 - Start of kernel command line string (e.g. "mem=128")
53 * r7 - End of kernel command line string
54 *
55 */
56 __HEAD
57 _ENTRY(_stext);
58 _ENTRY(_start);
59 /*
60 * Reserve a word at a fixed location to store the address
61 * of abatron_pteptrs
62 */
63 nop
65 /* Translate device tree address to physical, save in r30/r31 */
66 bl get_phys_addr
67 mr r30,r3
68 mr r31,r4
70 li r25,0 /* phys kernel start (low) */
71 li r24,0 /* CPU number */
72 li r23,0 /* phys kernel start (high) */
74 #ifdef CONFIG_RELOCATABLE
75 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */
77 /* Translate _stext address to physical, save in r23/r25 */
78 bl get_phys_addr
79 mr r23,r3
80 mr r25,r4
82 bl 0f
83 0: mflr r8
84 addis r3,r8,(is_second_reloc - 0b)@ha
85 lwz r19,(is_second_reloc - 0b)@l(r3)
87 /* Check if this is the second relocation. */
88 cmpwi r19,1
89 bne 1f
91 /*
92 * For the second relocation, we already get the real memstart_addr
93 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
94 * then the virtual address of start kernel should be:
95 * PAGE_OFFSET + (kernstart_addr - memstart_addr)
96 * Since the offset between kernstart_addr and memstart_addr should
97 * never be beyond 1G, so we can just use the lower 32bit of them
98 * for the calculation.
99 */
100 lis r3,PAGE_OFFSET@h
102 addis r4,r8,(kernstart_addr - 0b)@ha
103 addi r4,r4,(kernstart_addr - 0b)@l
104 lwz r5,4(r4)
106 addis r6,r8,(memstart_addr - 0b)@ha
107 addi r6,r6,(memstart_addr - 0b)@l
108 lwz r7,4(r6)
110 subf r5,r7,r5
111 add r3,r3,r5
112 b 2f
114 1:
115 /*
116 * We have the runtime (virutal) address of our base.
117 * We calculate our shift of offset from a 64M page.
118 * We could map the 64M page we belong to at PAGE_OFFSET and
119 * get going from there.
120 */
121 lis r4,KERNELBASE@h
122 ori r4,r4,KERNELBASE@l
123 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */
124 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
125 subf r3,r5,r6 /* r3 = r6 - r5 */
126 add r3,r4,r3 /* Required Virtual Address */
128 2: bl relocate
130 /*
131 * For the second relocation, we already set the right tlb entries
132 * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
133 */
134 cmpwi r19,1
135 beq set_ivor
136 #endif
138 /* We try to not make any assumptions about how the boot loader
139 * setup or used the TLBs. We invalidate all mappings from the
140 * boot loader and load a single entry in TLB1[0] to map the
141 * first 64M of kernel memory. Any boot info passed from the
142 * bootloader needs to live in this first 64M.
143 *
144 * Requirement on bootloader:
145 * - The page we're executing in needs to reside in TLB1 and
146 * have IPROT=1. If not an invalidate broadcast could
147 * evict the entry we're currently executing in.
148 *
149 * r3 = Index of TLB1 were executing in
150 * r4 = Current MSR[IS]
151 * r5 = Index of TLB1 temp mapping
152 *
153 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
154 * if needed
155 */
157 _ENTRY(__early_start)
158 LOAD_REG_ADDR_PIC(r20, kernstart_virt_addr)
159 lwz r20,0(r20)
161 #define ENTRY_MAPPING_BOOT_SETUP
162 #include "fsl_booke_entry_mapping.S"
163 #undef ENTRY_MAPPING_BOOT_SETUP
165 set_ivor:
166 /* Establish the interrupt vector offsets */
167 SET_IVOR(0, CriticalInput);
168 SET_IVOR(1, MachineCheck);
169 SET_IVOR(2, DataStorage);
170 SET_IVOR(3, InstructionStorage);
171 SET_IVOR(4, ExternalInput);
172 SET_IVOR(5, Alignment);
173 SET_IVOR(6, Program);
174 SET_IVOR(7, FloatingPointUnavailable);
175 SET_IVOR(8, SystemCall);
176 SET_IVOR(9, AuxillaryProcessorUnavailable);
177 SET_IVOR(10, Decrementer);
178 SET_IVOR(11, FixedIntervalTimer);
179 SET_IVOR(12, WatchdogTimer);
180 SET_IVOR(13, DataTLBError);
181 SET_IVOR(14, InstructionTLBError);
182 SET_IVOR(15, DebugCrit);
184 /* Establish the interrupt vector base */
185 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
186 mtspr SPRN_IVPR,r4
188 /* Setup the defaults for TLB entries */
189 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
190 #ifdef CONFIG_E200
191 oris r2,r2,MAS4_TLBSELD(1)@h
192 #endif
193 mtspr SPRN_MAS4, r2
195 #if !defined(CONFIG_BDI_SWITCH)
196 /*
197 * The Abatron BDI JTAG debugger does not tolerate others
198 * mucking with the debug registers.
199 */
200 lis r2,DBCR0_IDM@h
201 mtspr SPRN_DBCR0,r2
202 isync
203 /* clear any residual debug events */
204 li r2,-1
205 mtspr SPRN_DBSR,r2
206 #endif
208 #ifdef CONFIG_SMP
209 /* Check to see if we're the second processor, and jump
210 * to the secondary_start code if so
211 */
212 LOAD_REG_ADDR_PIC(r24, boot_cpuid)
213 lwz r24, 0(r24)
214 cmpwi r24, -1
215 mfspr r24,SPRN_PIR
216 bne __secondary_start
217 #endif
219 /*
220 * This is where the main kernel code starts.
221 */
223 /* ptr to current */
224 lis r2,init_task@h
225 ori r2,r2,init_task@l
227 /* ptr to current thread */
228 addi r4,r2,THREAD /* init task's THREAD */
229 mtspr SPRN_SPRG_THREAD,r4
231 /* stack */
232 lis r1,init_thread_union@h
233 ori r1,r1,init_thread_union@l
234 li r0,0
235 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
237 #ifdef CONFIG_SMP
238 stw r24, TASK_CPU(r2)
239 #endif
241 bl early_init
243 #ifdef CONFIG_KASAN
244 bl kasan_early_init
245 #endif
246 #ifdef CONFIG_RELOCATABLE
247 mr r3,r30
248 mr r4,r31
249 #ifdef CONFIG_PHYS_64BIT
250 mr r5,r23
251 mr r6,r25
252 #else
253 mr r5,r25
254 #endif
255 bl relocate_init
256 #endif
258 #ifdef CONFIG_DYNAMIC_MEMSTART
259 lis r3,kernstart_addr@ha
260 la r3,kernstart_addr@l(r3)
261 #ifdef CONFIG_PHYS_64BIT
262 stw r23,0(r3)
263 stw r25,4(r3)
264 #else
265 stw r25,0(r3)
266 #endif
267 #endif
269 /*
270 * Decide what sort of machine this is and initialize the MMU.
271 */
272 mr r3,r30
273 mr r4,r31
274 bl machine_init
275 bl MMU_init
277 /* Setup PTE pointers for the Abatron bdiGDB */
278 lis r6, swapper_pg_dir@h
279 ori r6, r6, swapper_pg_dir@l
280 lis r5, abatron_pteptrs@h
281 ori r5, r5, abatron_pteptrs@l
282 lis r3, kernstart_virt_addr@ha
283 lwz r4, kernstart_virt_addr@l(r3)
284 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
285 stw r6, 0(r5)
287 /* Let's move on */
288 lis r4,start_kernel@h
289 ori r4,r4,start_kernel@l
290 lis r3,MSR_KERNEL@h
291 ori r3,r3,MSR_KERNEL@l
292 mtspr SPRN_SRR0,r4
293 mtspr SPRN_SRR1,r3
294 rfi /* change context and jump to start_kernel */
296 /* Macros to hide the PTE size differences
297 *
298 * FIND_PTE -- walks the page tables given EA & pgdir pointer
299 * r10 -- EA of fault
300 * r11 -- PGDIR pointer
301 * r12 -- free
302 * label 2: is the bailout case
303 *
304 * if we find the pte (fall through):
305 * r11 is low pte word
306 * r12 is pointer to the pte
307 * r10 is the pshift from the PGD, if we're a hugepage
308 */
309 #ifdef CONFIG_PTE_64BIT
310 #ifdef CONFIG_HUGETLB_PAGE
311 #define FIND_PTE \
312 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
313 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
314 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
315 blt 1000f; /* Normal non-huge page */ \
316 beq 2f; /* Bail if no table */ \
317 oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
318 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
319 xor r12, r10, r11; /* drop size bits from pointer */ \
320 b 1001f; \
321 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
322 li r10, 0; /* clear r10 */ \
323 1001: lwz r11, 4(r12); /* Get pte entry */
324 #else
325 #define FIND_PTE \
326 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
327 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
328 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
329 beq 2f; /* Bail if no table */ \
330 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
331 lwz r11, 4(r12); /* Get pte entry */
332 #endif /* HUGEPAGE */
333 #else /* !PTE_64BIT */
334 #define FIND_PTE \
335 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
336 lwz r11, 0(r11); /* Get L1 entry */ \
337 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
338 beq 2f; /* Bail if no table */ \
339 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
340 lwz r11, 0(r12); /* Get Linux PTE */
341 #endif
343 /*
344 * Interrupt vector entry code
345 *
346 * The Book E MMUs are always on so we don't need to handle
347 * interrupts in real mode as with previous PPC processors. In
348 * this case we handle interrupts in the kernel virtual address
349 * space.
350 *
351 * Interrupt vectors are dynamically placed relative to the
352 * interrupt prefix as determined by the address of interrupt_base.
353 * The interrupt vectors offsets are programmed using the labels
354 * for each interrupt vector entry.
355 *
356 * Interrupt vectors must be aligned on a 16 byte boundary.
357 * We align on a 32 byte cache line boundary for good measure.
358 */
360 interrupt_base:
361 /* Critical Input Interrupt */
362 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
364 /* Machine Check Interrupt */
365 #ifdef CONFIG_E200
366 /* no RFMCI, MCSRRs on E200 */
367 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
368 machine_check_exception)
369 #else
370 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
371 #endif
373 /* Data Storage Interrupt */
374 START_EXCEPTION(DataStorage)
375 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
376 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
377 stw r5,_ESR(r11)
378 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
379 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
380 bne 1f
381 EXC_XFER_LITE(0x0300, handle_page_fault)
382 1:
383 addi r3,r1,STACK_FRAME_OVERHEAD
384 EXC_XFER_LITE(0x0300, CacheLockingException)
386 /* Instruction Storage Interrupt */
387 INSTRUCTION_STORAGE_EXCEPTION
389 /* External Input Interrupt */
390 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
392 /* Alignment Interrupt */
393 ALIGNMENT_EXCEPTION
395 /* Program Interrupt */
396 PROGRAM_EXCEPTION
398 /* Floating Point Unavailable Interrupt */
399 #ifdef CONFIG_PPC_FPU
400 FP_UNAVAILABLE_EXCEPTION
401 #else
402 #ifdef CONFIG_E200
403 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
404 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
405 program_check_exception, EXC_XFER_STD)
406 #else
407 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
408 unknown_exception, EXC_XFER_STD)
409 #endif
410 #endif
412 /* System Call Interrupt */
413 START_EXCEPTION(SystemCall)
414 SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1
416 /* Auxiliary Processor Unavailable Interrupt */
417 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
418 unknown_exception, EXC_XFER_STD)
420 /* Decrementer Interrupt */
421 DECREMENTER_EXCEPTION
423 /* Fixed Internal Timer Interrupt */
424 /* TODO: Add FIT support */
425 EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
426 unknown_exception, EXC_XFER_STD)
428 /* Watchdog Timer Interrupt */
429 #ifdef CONFIG_BOOKE_WDT
430 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
431 #else
432 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
433 #endif
435 /* Data TLB Error Interrupt */
436 START_EXCEPTION(DataTLBError)
437 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
438 mfspr r10, SPRN_SPRG_THREAD
439 stw r11, THREAD_NORMSAVE(0)(r10)
440 #ifdef CONFIG_KVM_BOOKE_HV
441 BEGIN_FTR_SECTION
442 mfspr r11, SPRN_SRR1
443 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
444 #endif
445 stw r12, THREAD_NORMSAVE(1)(r10)
446 stw r13, THREAD_NORMSAVE(2)(r10)
447 mfcr r13
448 stw r13, THREAD_NORMSAVE(3)(r10)
449 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
450 START_BTB_FLUSH_SECTION
451 mfspr r11, SPRN_SRR1
452 andi. r10,r11,MSR_PR
453 beq 1f
454 BTB_FLUSH(r10)
455 1:
456 END_BTB_FLUSH_SECTION
457 mfspr r10, SPRN_DEAR /* Get faulting address */
459 /* If we are faulting a kernel address, we have to use the
460 * kernel page tables.
461 */
462 lis r11, PAGE_OFFSET@h
463 cmplw 5, r10, r11
464 blt 5, 3f
465 lis r11, swapper_pg_dir@h
466 ori r11, r11, swapper_pg_dir@l
468 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
469 rlwinm r12,r12,0,16,1
470 mtspr SPRN_MAS1,r12
472 b 4f
474 /* Get the PGD for the current thread */
475 3:
476 mfspr r11,SPRN_SPRG_THREAD
477 lwz r11,PGDIR(r11)
479 4:
480 /* Mask of required permission bits. Note that while we
481 * do copy ESR:ST to _PAGE_RW position as trying to write
482 * to an RO page is pretty common, we don't do it with
483 * _PAGE_DIRTY. We could do it, but it's a fairly rare
484 * event so I'd rather take the overhead when it happens
485 * rather than adding an instruction here. We should measure
486 * whether the whole thing is worth it in the first place
487 * as we could avoid loading SPRN_ESR completely in the first
488 * place...
489 *
490 * TODO: Is it worth doing that mfspr & rlwimi in the first
491 * place or can we save a couple of instructions here ?
492 */
493 mfspr r12,SPRN_ESR
494 #ifdef CONFIG_PTE_64BIT
495 li r13,_PAGE_PRESENT
496 oris r13,r13,_PAGE_ACCESSED@h
497 #else
498 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
499 #endif
500 rlwimi r13,r12,11,29,29
502 FIND_PTE
503 andc. r13,r13,r11 /* Check permission */
505 #ifdef CONFIG_PTE_64BIT
506 #ifdef CONFIG_SMP
507 subf r13,r11,r12 /* create false data dep */
508 lwzx r13,r11,r13 /* Get upper pte bits */
509 #else
510 lwz r13,0(r12) /* Get upper pte bits */
511 #endif
512 #endif
514 bne 2f /* Bail if permission/valid mismach */
516 /* Jump to common tlb load */
517 b finish_tlb_load
518 2:
519 /* The bailout. Restore registers to pre-exception conditions
520 * and call the heavyweights to help us out.
521 */
522 mfspr r10, SPRN_SPRG_THREAD
523 lwz r11, THREAD_NORMSAVE(3)(r10)
524 mtcr r11
525 lwz r13, THREAD_NORMSAVE(2)(r10)
526 lwz r12, THREAD_NORMSAVE(1)(r10)
527 lwz r11, THREAD_NORMSAVE(0)(r10)
528 mfspr r10, SPRN_SPRG_RSCRATCH0
529 b DataStorage
531 /* Instruction TLB Error Interrupt */
532 /*
533 * Nearly the same as above, except we get our
534 * information from different registers and bailout
535 * to a different point.
536 */
537 START_EXCEPTION(InstructionTLBError)
538 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
539 mfspr r10, SPRN_SPRG_THREAD
540 stw r11, THREAD_NORMSAVE(0)(r10)
541 #ifdef CONFIG_KVM_BOOKE_HV
542 BEGIN_FTR_SECTION
543 mfspr r11, SPRN_SRR1
544 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
545 #endif
546 stw r12, THREAD_NORMSAVE(1)(r10)
547 stw r13, THREAD_NORMSAVE(2)(r10)
548 mfcr r13
549 stw r13, THREAD_NORMSAVE(3)(r10)
550 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
551 START_BTB_FLUSH_SECTION
552 mfspr r11, SPRN_SRR1
553 andi. r10,r11,MSR_PR
554 beq 1f
555 BTB_FLUSH(r10)
556 1:
557 END_BTB_FLUSH_SECTION
559 mfspr r10, SPRN_SRR0 /* Get faulting address */
561 /* If we are faulting a kernel address, we have to use the
562 * kernel page tables.
563 */
564 lis r11, PAGE_OFFSET@h
565 cmplw 5, r10, r11
566 blt 5, 3f
567 lis r11, swapper_pg_dir@h
568 ori r11, r11, swapper_pg_dir@l
570 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
571 rlwinm r12,r12,0,16,1
572 mtspr SPRN_MAS1,r12
574 /* Make up the required permissions for kernel code */
575 #ifdef CONFIG_PTE_64BIT
576 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
577 oris r13,r13,_PAGE_ACCESSED@h
578 #else
579 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
580 #endif
581 b 4f
583 /* Get the PGD for the current thread */
584 3:
585 mfspr r11,SPRN_SPRG_THREAD
586 lwz r11,PGDIR(r11)
588 /* Make up the required permissions for user code */
589 #ifdef CONFIG_PTE_64BIT
590 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
591 oris r13,r13,_PAGE_ACCESSED@h
592 #else
593 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
594 #endif
596 4:
597 FIND_PTE
598 andc. r13,r13,r11 /* Check permission */
600 #ifdef CONFIG_PTE_64BIT
601 #ifdef CONFIG_SMP
602 subf r13,r11,r12 /* create false data dep */
603 lwzx r13,r11,r13 /* Get upper pte bits */
604 #else
605 lwz r13,0(r12) /* Get upper pte bits */
606 #endif
607 #endif
609 bne 2f /* Bail if permission mismach */
611 /* Jump to common TLB load point */
612 b finish_tlb_load
614 2:
615 /* The bailout. Restore registers to pre-exception conditions
616 * and call the heavyweights to help us out.
617 */
618 mfspr r10, SPRN_SPRG_THREAD
619 lwz r11, THREAD_NORMSAVE(3)(r10)
620 mtcr r11
621 lwz r13, THREAD_NORMSAVE(2)(r10)
622 lwz r12, THREAD_NORMSAVE(1)(r10)
623 lwz r11, THREAD_NORMSAVE(0)(r10)
624 mfspr r10, SPRN_SPRG_RSCRATCH0
625 b InstructionStorage
627 /* Define SPE handlers for e200 and e500v2 */
628 #ifdef CONFIG_SPE
629 /* SPE Unavailable */
630 START_EXCEPTION(SPEUnavailable)
631 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
632 beq 1f
633 bl load_up_spe
634 b fast_exception_return
635 1: addi r3,r1,STACK_FRAME_OVERHEAD
636 EXC_XFER_LITE(0x2010, KernelSPE)
637 #elif defined(CONFIG_SPE_POSSIBLE)
638 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
639 unknown_exception, EXC_XFER_STD)
640 #endif /* CONFIG_SPE_POSSIBLE */
642 /* SPE Floating Point Data */
643 #ifdef CONFIG_SPE
644 EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData,
645 SPEFloatingPointException, EXC_XFER_STD)
647 /* SPE Floating Point Round */
648 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
649 SPEFloatingPointRoundException, EXC_XFER_STD)
650 #elif defined(CONFIG_SPE_POSSIBLE)
651 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData,
652 unknown_exception, EXC_XFER_STD)
653 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
654 unknown_exception, EXC_XFER_STD)
655 #endif /* CONFIG_SPE_POSSIBLE */
658 /* Performance Monitor */
659 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
660 performance_monitor_exception, EXC_XFER_STD)
662 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
664 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
665 CriticalDoorbell, unknown_exception)
667 /* Debug Interrupt */
668 DEBUG_DEBUG_EXCEPTION
669 DEBUG_CRIT_EXCEPTION
671 GUEST_DOORBELL_EXCEPTION
673 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
674 unknown_exception)
676 /* Hypercall */
677 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_STD)
679 /* Embedded Hypervisor Privilege */
680 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_STD)
682 interrupt_end:
684 /*
685 * Local functions
686 */
688 /*
689 * Both the instruction and data TLB miss get to this
690 * point to load the TLB.
691 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use
692 * r11 - TLB (info from Linux PTE)
693 * r12 - available to use
694 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
695 * CR5 - results of addr >= PAGE_OFFSET
696 * MAS0, MAS1 - loaded with proper value when we get here
697 * MAS2, MAS3 - will need additional info from Linux PTE
698 * Upon exit, we reload everything and RFI.
699 */
700 finish_tlb_load:
701 #ifdef CONFIG_HUGETLB_PAGE
702 cmpwi 6, r10, 0 /* check for huge page */
703 beq 6, finish_tlb_load_cont /* !huge */
705 /* Alas, we need more scratch registers for hugepages */
706 mfspr r12, SPRN_SPRG_THREAD
707 stw r14, THREAD_NORMSAVE(4)(r12)
708 stw r15, THREAD_NORMSAVE(5)(r12)
709 stw r16, THREAD_NORMSAVE(6)(r12)
710 stw r17, THREAD_NORMSAVE(7)(r12)
712 /* Get the next_tlbcam_idx percpu var */
713 #ifdef CONFIG_SMP
714 lwz r15, TASK_CPU-THREAD(r12)
715 lis r14, __per_cpu_offset@h
716 ori r14, r14, __per_cpu_offset@l
717 rlwinm r15, r15, 2, 0, 29
718 lwzx r16, r14, r15
719 #else
720 li r16, 0
721 #endif
722 lis r17, next_tlbcam_idx@h
723 ori r17, r17, next_tlbcam_idx@l
724 add r17, r17, r16 /* r17 = *next_tlbcam_idx */
725 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
727 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
728 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
729 mtspr SPRN_MAS0, r14
731 /* Extract TLB1CFG(NENTRY) */
732 mfspr r16, SPRN_TLB1CFG
733 andi. r16, r16, 0xfff
735 /* Update next_tlbcam_idx, wrapping when necessary */
736 addi r15, r15, 1
737 cmpw r15, r16
738 blt 100f
739 lis r14, tlbcam_index@h
740 ori r14, r14, tlbcam_index@l
741 lwz r15, 0(r14)
742 100: stw r15, 0(r17)
744 /*
745 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
746 * tlb_enc = (pshift - 10).
747 */
748 subi r15, r10, 10
749 mfspr r16, SPRN_MAS1
750 rlwimi r16, r15, 7, 20, 24
751 mtspr SPRN_MAS1, r16
753 /* copy the pshift for use later */
754 mr r14, r10
756 /* fall through */
758 #endif /* CONFIG_HUGETLB_PAGE */
760 /*
761 * We set execute, because we don't have the granularity to
762 * properly set this at the page level (Linux problem).
763 * Many of these bits are software only. Bits we don't set
764 * here we (properly should) assume have the appropriate value.
765 */
766 finish_tlb_load_cont:
767 #ifdef CONFIG_PTE_64BIT
768 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
769 andi. r10, r11, _PAGE_DIRTY
770 bne 1f
771 li r10, MAS3_SW | MAS3_UW
772 andc r12, r12, r10
773 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
774 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
775 2: mtspr SPRN_MAS3, r12
776 BEGIN_MMU_FTR_SECTION
777 srwi r10, r13, 12 /* grab RPN[12:31] */
778 mtspr SPRN_MAS7, r10
779 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
780 #else
781 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
782 mr r13, r11
783 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
784 and r12, r11, r10
785 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
786 slwi r10, r12, 1
787 or r10, r10, r12
788 iseleq r12, r12, r10
789 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
790 mtspr SPRN_MAS3, r13
791 #endif
793 mfspr r12, SPRN_MAS2
794 #ifdef CONFIG_PTE_64BIT
795 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
796 #else
797 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
798 #endif
799 #ifdef CONFIG_HUGETLB_PAGE
800 beq 6, 3f /* don't mask if page isn't huge */
801 li r13, 1
802 slw r13, r13, r14
803 subi r13, r13, 1
804 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
805 andc r12, r12, r13 /* mask off ea bits within the page */
806 #endif
807 3: mtspr SPRN_MAS2, r12
809 #ifdef CONFIG_E200
810 /* Round robin TLB1 entries assignment */
811 mfspr r12, SPRN_MAS0
813 /* Extract TLB1CFG(NENTRY) */
814 mfspr r11, SPRN_TLB1CFG
815 andi. r11, r11, 0xfff
817 /* Extract MAS0(NV) */
818 andi. r13, r12, 0xfff
819 addi r13, r13, 1
820 cmpw 0, r13, r11
821 addi r12, r12, 1
823 /* check if we need to wrap */
824 blt 7f
826 /* wrap back to first free tlbcam entry */
827 lis r13, tlbcam_index@ha
828 lwz r13, tlbcam_index@l(r13)
829 rlwimi r12, r13, 0, 20, 31
830 7:
831 mtspr SPRN_MAS0,r12
832 #endif /* CONFIG_E200 */
834 tlb_write_entry:
835 tlbwe
837 /* Done...restore registers and get out of here. */
838 mfspr r10, SPRN_SPRG_THREAD
839 #ifdef CONFIG_HUGETLB_PAGE
840 beq 6, 8f /* skip restore for 4k page faults */
841 lwz r14, THREAD_NORMSAVE(4)(r10)
842 lwz r15, THREAD_NORMSAVE(5)(r10)
843 lwz r16, THREAD_NORMSAVE(6)(r10)
844 lwz r17, THREAD_NORMSAVE(7)(r10)
845 #endif
846 8: lwz r11, THREAD_NORMSAVE(3)(r10)
847 mtcr r11
848 lwz r13, THREAD_NORMSAVE(2)(r10)
849 lwz r12, THREAD_NORMSAVE(1)(r10)
850 lwz r11, THREAD_NORMSAVE(0)(r10)
851 mfspr r10, SPRN_SPRG_RSCRATCH0
852 rfi /* Force context change */
854 #ifdef CONFIG_SPE
855 /* Note that the SPE support is closely modeled after the AltiVec
856 * support. Changes to one are likely to be applicable to the
857 * other! */
858 _GLOBAL(load_up_spe)
859 /*
860 * Disable SPE for the task which had SPE previously,
861 * and save its SPE registers in its thread_struct.
862 * Enables SPE for use in the kernel on return.
863 * On SMP we know the SPE units are free, since we give it up every
864 * switch. -- Kumar
865 */
866 mfmsr r5
867 oris r5,r5,MSR_SPE@h
868 mtmsr r5 /* enable use of SPE now */
869 isync
870 /* enable use of SPE after return */
871 oris r9,r9,MSR_SPE@h
872 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
873 li r4,1
874 li r10,THREAD_ACC
875 stw r4,THREAD_USED_SPE(r5)
876 evlddx evr4,r10,r5
877 evmra evr4,evr4
878 REST_32EVRS(0,r10,r5,THREAD_EVR0)
879 blr
881 /*
882 * SPE unavailable trap from kernel - print a message, but let
883 * the task use SPE in the kernel until it returns to user mode.
884 */
885 KernelSPE:
886 lwz r3,_MSR(r1)
887 oris r3,r3,MSR_SPE@h
888 stw r3,_MSR(r1) /* enable use of SPE after return */
889 #ifdef CONFIG_PRINTK
890 lis r3,87f@h
891 ori r3,r3,87f@l
892 mr r4,r2 /* current */
893 lwz r5,_NIP(r1)
894 bl printk
895 #endif
896 b ret_from_except
897 #ifdef CONFIG_PRINTK
898 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
899 #endif
900 .align 4,0
902 #endif /* CONFIG_SPE */
904 /*
905 * Translate the effec addr in r3 to phys addr. The phys addr will be put
906 * into r3(higher 32bit) and r4(lower 32bit)
907 */
908 get_phys_addr:
909 mfmsr r8
910 mfspr r9,SPRN_PID
911 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */
912 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
913 mtspr SPRN_MAS6,r9
915 tlbsx 0,r3 /* must succeed */
917 mfspr r8,SPRN_MAS1
918 mfspr r12,SPRN_MAS3
919 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */
920 li r10,1024
921 slw r10,r10,r9 /* r10 = page size */
922 addi r10,r10,-1
923 and r11,r3,r10 /* r11 = page offset */
924 andc r4,r12,r10 /* r4 = page base */
925 or r4,r4,r11 /* r4 = devtree phys addr */
926 #ifdef CONFIG_PHYS_64BIT
927 mfspr r3,SPRN_MAS7
928 #endif
929 blr
931 /*
932 * Global functions
933 */
935 #ifdef CONFIG_E200
936 /* Adjust or setup IVORs for e200 */
937 _GLOBAL(__setup_e200_ivors)
938 li r3,DebugDebug@l
939 mtspr SPRN_IVOR15,r3
940 li r3,SPEUnavailable@l
941 mtspr SPRN_IVOR32,r3
942 li r3,SPEFloatingPointData@l
943 mtspr SPRN_IVOR33,r3
944 li r3,SPEFloatingPointRound@l
945 mtspr SPRN_IVOR34,r3
946 sync
947 blr
948 #endif
950 #ifdef CONFIG_E500
951 #ifndef CONFIG_PPC_E500MC
952 /* Adjust or setup IVORs for e500v1/v2 */
953 _GLOBAL(__setup_e500_ivors)
954 li r3,DebugCrit@l
955 mtspr SPRN_IVOR15,r3
956 li r3,SPEUnavailable@l
957 mtspr SPRN_IVOR32,r3
958 li r3,SPEFloatingPointData@l
959 mtspr SPRN_IVOR33,r3
960 li r3,SPEFloatingPointRound@l
961 mtspr SPRN_IVOR34,r3
962 li r3,PerformanceMonitor@l
963 mtspr SPRN_IVOR35,r3
964 sync
965 blr
966 #else
967 /* Adjust or setup IVORs for e500mc */
968 _GLOBAL(__setup_e500mc_ivors)
969 li r3,DebugDebug@l
970 mtspr SPRN_IVOR15,r3
971 li r3,PerformanceMonitor@l
972 mtspr SPRN_IVOR35,r3
973 li r3,Doorbell@l
974 mtspr SPRN_IVOR36,r3
975 li r3,CriticalDoorbell@l
976 mtspr SPRN_IVOR37,r3
977 sync
978 blr
980 /* setup ehv ivors for */
981 _GLOBAL(__setup_ehv_ivors)
982 li r3,GuestDoorbell@l
983 mtspr SPRN_IVOR38,r3
984 li r3,CriticalGuestDoorbell@l
985 mtspr SPRN_IVOR39,r3
986 li r3,Hypercall@l
987 mtspr SPRN_IVOR40,r3
988 li r3,Ehvpriv@l
989 mtspr SPRN_IVOR41,r3
990 sync
991 blr
992 #endif /* CONFIG_PPC_E500MC */
993 #endif /* CONFIG_E500 */
995 #ifdef CONFIG_SPE
996 /*
997 * extern void __giveup_spe(struct task_struct *prev)
998 *
999 */
1000 _GLOBAL(__giveup_spe)
1001 addi r3,r3,THREAD /* want THREAD of task */
1002 lwz r5,PT_REGS(r3)
1003 cmpi 0,r5,0
1004 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
1005 evxor evr6, evr6, evr6 /* clear out evr6 */
1006 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
1007 li r4,THREAD_ACC
1008 evstddx evr6, r4, r3 /* save off accumulator */
1009 beq 1f
1010 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1011 lis r3,MSR_SPE@h
1012 andc r4,r4,r3 /* disable SPE for previous task */
1013 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1014 1:
1015 blr
1016 #endif /* CONFIG_SPE */
1018 /*
1019 * extern void abort(void)
1020 *
1021 * At present, this routine just applies a system reset.
1022 */
1023 _GLOBAL(abort)
1024 li r13,0
1025 mtspr SPRN_DBCR0,r13 /* disable all debug events */
1026 isync
1027 mfmsr r13
1028 ori r13,r13,MSR_DE@l /* Enable Debug Events */
1029 mtmsr r13
1030 isync
1031 mfspr r13,SPRN_DBCR0
1032 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1033 mtspr SPRN_DBCR0,r13
1034 isync
1036 _GLOBAL(set_context)
1038 #ifdef CONFIG_BDI_SWITCH
1039 /* Context switch the PTE pointer for the Abatron BDI2000.
1040 * The PGDIR is the second parameter.
1041 */
1042 lis r5, abatron_pteptrs@h
1043 ori r5, r5, abatron_pteptrs@l
1044 stw r4, 0x4(r5)
1045 #endif
1046 mtspr SPRN_PID,r3
1047 isync /* Force context change */
1048 blr
1050 #ifdef CONFIG_SMP
1051 /* When we get here, r24 needs to hold the CPU # */
1052 .globl __secondary_start
1053 __secondary_start:
1054 LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1055 lwz r3,0(r3)
1056 mtctr r3
1057 li r26,0 /* r26 safe? */
1059 bl switch_to_as1
1060 mr r27,r3 /* tlb entry */
1061 /* Load each CAM entry */
1062 1: mr r3,r26
1063 bl loadcam_entry
1064 addi r26,r26,1
1065 bdnz 1b
1066 mr r3,r27 /* tlb entry */
1067 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1068 lwz r4,0(r4)
1069 mr r5,r25 /* phys kernel start */
1070 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */
1071 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1072 lis r7,KERNELBASE@h
1073 ori r7,r7,KERNELBASE@l
1074 cmpw r20,r7 /* if kernstart_virt_addr != KERNELBASE, randomized */
1075 beq 2f
1076 li r4,0
1077 2: li r5,0 /* no device tree */
1078 li r6,0 /* not boot cpu */
1079 bl restore_to_as0
1082 lis r3,__secondary_hold_acknowledge@h
1083 ori r3,r3,__secondary_hold_acknowledge@l
1084 stw r24,0(r3)
1086 li r3,0
1087 mr r4,r24 /* Why? */
1088 bl call_setup_cpu
1090 /* get current's stack and current */
1091 lis r2,secondary_current@ha
1092 lwz r2,secondary_current@l(r2)
1093 lwz r1,TASK_STACK(r2)
1095 /* stack */
1096 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1097 li r0,0
1098 stw r0,0(r1)
1100 /* ptr to current thread */
1101 addi r4,r2,THREAD /* address of our thread_struct */
1102 mtspr SPRN_SPRG_THREAD,r4
1104 /* Setup the defaults for TLB entries */
1105 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1106 mtspr SPRN_MAS4,r4
1108 /* Jump to start_secondary */
1109 lis r4,MSR_KERNEL@h
1110 ori r4,r4,MSR_KERNEL@l
1111 lis r3,start_secondary@h
1112 ori r3,r3,start_secondary@l
1113 mtspr SPRN_SRR0,r3
1114 mtspr SPRN_SRR1,r4
1115 sync
1116 rfi
1117 sync
1119 .globl __secondary_hold_acknowledge
1120 __secondary_hold_acknowledge:
1121 .long -1
1122 #endif
1124 /*
1125 * Create a 64M tlb by address and entry
1126 * r3 - entry
1127 * r4 - virtual address
1128 * r5/r6 - physical address
1129 */
1130 _GLOBAL(create_kaslr_tlb_entry)
1131 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
1132 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
1133 mtspr SPRN_MAS0,r7 /* Write MAS0 */
1135 lis r3,(MAS1_VALID|MAS1_IPROT)@h
1136 ori r3,r3,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
1137 mtspr SPRN_MAS1,r3 /* Write MAS1 */
1139 lis r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h
1140 ori r3,r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l
1141 and r3,r3,r4
1142 ori r3,r3,MAS2_M_IF_NEEDED@l
1143 mtspr SPRN_MAS2,r3 /* Write MAS2(EPN) */
1145 #ifdef CONFIG_PHYS_64BIT
1146 ori r8,r6,(MAS3_SW|MAS3_SR|MAS3_SX)
1147 mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */
1148 mtspr SPRN_MAS7,r5
1149 #else
1150 ori r8,r5,(MAS3_SW|MAS3_SR|MAS3_SX)
1151 mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */
1152 #endif
1154 tlbwe /* Write TLB */
1155 isync
1156 sync
1157 blr
1159 /*
1160 * Return to the start of the relocated kernel and run again
1161 * r3 - virtual address of fdt
1162 * r4 - entry of the kernel
1163 */
1164 _GLOBAL(reloc_kernel_entry)
1165 mfmsr r7
1166 rlwinm r7, r7, 0, ~(MSR_IS | MSR_DS)
1168 mtspr SPRN_SRR0,r4
1169 mtspr SPRN_SRR1,r7
1170 rfi
1172 /*
1173 * Create a tlb entry with the same effective and physical address as
1174 * the tlb entry used by the current running code. But set the TS to 1.
1175 * Then switch to the address space 1. It will return with the r3 set to
1176 * the ESEL of the new created tlb.
1177 */
1178 _GLOBAL(switch_to_as1)
1179 mflr r5
1181 /* Find a entry not used */
1182 mfspr r3,SPRN_TLB1CFG
1183 andi. r3,r3,0xfff
1184 mfspr r4,SPRN_PID
1185 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1186 mtspr SPRN_MAS6,r4
1187 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1188 addi r3,r3,-1
1189 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1190 mtspr SPRN_MAS0,r4
1191 tlbre
1192 mfspr r4,SPRN_MAS1
1193 andis. r4,r4,MAS1_VALID@h
1194 bne 1b
1196 /* Get the tlb entry used by the current running code */
1197 bl 0f
1198 0: mflr r4
1199 tlbsx 0,r4
1201 mfspr r4,SPRN_MAS1
1202 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1203 mtspr SPRN_MAS1,r4
1205 mfspr r4,SPRN_MAS0
1206 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1207 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1208 mtspr SPRN_MAS0,r4
1209 tlbwe
1210 isync
1211 sync
1213 mfmsr r4
1214 ori r4,r4,MSR_IS | MSR_DS
1215 mtspr SPRN_SRR0,r5
1216 mtspr SPRN_SRR1,r4
1217 sync
1218 rfi
1220 /*
1221 * Restore to the address space 0 and also invalidate the tlb entry created
1222 * by switch_to_as1.
1223 * r3 - the tlb entry which should be invalidated
1224 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1225 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1226 * r6 - boot cpu
1227 */
1228 _GLOBAL(restore_to_as0)
1229 mflr r0
1231 bl 0f
1232 0: mflr r9
1233 addi r9,r9,1f - 0b
1235 /*
1236 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1237 * so we need calculate the right jump and device tree address based
1238 * on the offset passed by r4.
1239 */
1240 add r9,r9,r4
1241 add r5,r5,r4
1242 add r0,r0,r4
1244 2: mfmsr r7
1245 li r8,(MSR_IS | MSR_DS)
1246 andc r7,r7,r8
1248 mtspr SPRN_SRR0,r9
1249 mtspr SPRN_SRR1,r7
1250 sync
1251 rfi
1253 /* Invalidate the temporary tlb entry for AS1 */
1254 1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */
1255 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1256 mtspr SPRN_MAS0,r9
1257 tlbre
1258 mfspr r9,SPRN_MAS1
1259 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */
1260 mtspr SPRN_MAS1,r9
1261 tlbwe
1262 isync
1264 cmpwi r4,0
1265 cmpwi cr1,r6,0
1266 cror eq,4*cr1+eq,eq
1267 bne 3f /* offset != 0 && is_boot_cpu */
1268 mtlr r0
1269 blr
1271 /*
1272 * The PAGE_OFFSET will map to a different physical address,
1273 * jump to _start to do another relocation again.
1274 */
1275 3: mr r3,r5
1276 bl _start
1278 /*
1279 * We put a few things here that have to be page-aligned. This stuff
1280 * goes at the beginning of the data segment, which is page-aligned.
1281 */
1282 .data
1283 .align 12
1284 .globl sdata
1285 sdata:
1286 .globl empty_zero_page
1287 empty_zero_page:
1288 .space 4096
1289 EXPORT_SYMBOL(empty_zero_page)
1290 .globl swapper_pg_dir
1291 swapper_pg_dir:
1292 .space PGD_TABLE_SIZE
1294 /*
1295 * Room for two PTE pointers, usually the kernel and current user pointers
1296 * to their respective root page table.
1297 */
1298 abatron_pteptrs:
1299 .space 8