arch/powerpc/kernel/pci_64.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Port for PPC64 David Engebretsen, IBM Corp.
   4  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
   5  *
   6  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
   7  *   Rework, based on alpha PCI code.
   8  */
   9
  10 #undef DEBUG
  11
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/string.h>
  15 #include <linux/init.h>
  16 #include <linux/export.h>
  17 #include <linux/mm.h>
  18 #include <linux/list.h>
  19 #include <linux/syscalls.h>
  20 #include <linux/irq.h>
  21 #include <linux/vmalloc.h>
  22
  23 #include <asm/processor.h>
  24 #include <asm/io.h>
  25 #include <asm/prom.h>
  26 #include <asm/pci-bridge.h>
  27 #include <asm/byteorder.h>
  28 #include <asm/machdep.h>
  29 #include <asm/ppc-pci.h>
  30
  31 /* pci_io_base -- the base address from which io bars are offsets.
  32  * This is the lowest I/O base address (so bar values are always positive),
  33  * and it *must* be the start of ISA space if an ISA bus exists because
  34  * ISA drivers use hard coded offsets.  If no ISA bus exists nothing
  35  * is mapped on the first 64K of IO space
  36  */
  37 unsigned long pci_io_base;
  38 EXPORT_SYMBOL(pci_io_base);
  39
  40 static int __init pcibios_init(void)
  41 {
  42         struct pci_controller *hose, *tmp;
  43
  44         printk(KERN_INFO "PCI: Probing PCI hardware\n");
  45
  46         /* For now, override phys_mem_access_prot. If we need it,g
  47          * later, we may move that initialization to each ppc_md
  48          */
  49         ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
  50
  51         /* On ppc64, we always enable PCI domains and we keep domain 0
  52          * backward compatible in /proc for video cards
  53          */
  54         pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
  55
  56         /* Scan all of the recorded PCI controllers.  */
  57         list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
  58                 pcibios_scan_phb(hose);
  59
  60         /* Call common code to handle resource allocation */
  61         pcibios_resource_survey();
  62
  63         /* Add devices. */
  64         list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
  65                 pci_bus_add_devices(hose->bus);
  66
  67         /* Call machine dependent fixup */
  68         if (ppc_md.pcibios_fixup)
  69                 ppc_md.pcibios_fixup();
  70
  71         printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
  72
  73         return 0;
  74 }
  75
  76 subsys_initcall(pcibios_init);
  77
  78 int pcibios_unmap_io_space(struct pci_bus *bus)
  79 {
  80         struct pci_controller *hose;
  81
  82         WARN_ON(bus == NULL);
  83
  84         /* If this is not a PHB, we only flush the hash table over
  85          * the area mapped by this bridge. We don't play with the PTE
  86          * mappings since we might have to deal with sub-page alignments
  87          * so flushing the hash table is the only sane way to make sure
  88          * that no hash entries are covering that removed bridge area
  89          * while still allowing other busses overlapping those pages
  90          *
  91          * Note: If we ever support P2P hotplug on Book3E, we'll have
  92          * to do an appropriate TLB flush here too
  93          */
  94         if (bus->self) {
  95 #ifdef CONFIG_PPC_BOOK3S_64
  96                 struct resource *res = bus->resource[0];
  97 #endif
  98
  99                 pr_debug("IO unmapping for PCI-PCI bridge %s\n",
 100                          pci_name(bus->self));
 101
 102 #ifdef CONFIG_PPC_BOOK3S_64
 103                 __flush_hash_table_range(&init_mm, res->start + _IO_BASE,
 104                                          res->end + _IO_BASE + 1);
 105 #endif
 106                 return 0;
 107         }
 108
 109         /* Get the host bridge */
 110         hose = pci_bus_to_host(bus);
 111
 112         /* Check if we have IOs allocated */
 113         if (hose->io_base_alloc == NULL)
 114                 return 0;
 115
 116         pr_debug("IO unmapping for PHB %pOF\n", hose->dn);
 117         pr_debug("  alloc=0x%p\n", hose->io_base_alloc);
 118
 119         /* This is a PHB, we fully unmap the IO area */
 120         vunmap(hose->io_base_alloc);
 121
 122         return 0;
 123 }
 124 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
 125
 126 static int pcibios_map_phb_io_space(struct pci_controller *hose)
 127 {
 128         struct vm_struct *area;
 129         unsigned long phys_page;
 130         unsigned long size_page;
 131         unsigned long io_virt_offset;
 132
 133         phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
 134         size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
 135
 136         /* Make sure IO area address is clear */
 137         hose->io_base_alloc = NULL;
 138
 139         /* If there's no IO to map on that bus, get away too */
 140         if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
 141                 return 0;
 142
 143         /* Let's allocate some IO space for that guy. We don't pass
 144          * VM_IOREMAP because we don't care about alignment tricks that
 145          * the core does in that case. Maybe we should due to stupid card
 146          * with incomplete address decoding but I'd rather not deal with
 147          * those outside of the reserved 64K legacy region.
 148          */
 149         area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
 150         if (area == NULL)
 151                 return -ENOMEM;
 152         hose->io_base_alloc = area->addr;
 153         hose->io_base_virt = (void __iomem *)(area->addr +
 154                                               hose->io_base_phys - phys_page);
 155
 156         pr_debug("IO mapping for PHB %pOF\n", hose->dn);
 157         pr_debug("  phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
 158                  hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
 159         pr_debug("  size=0x%016llx (alloc=0x%016lx)\n",
 160                  hose->pci_io_size, size_page);
 161
 162         /* Establish the mapping */
 163         if (__ioremap_at(phys_page, area->addr, size_page,
 164                          pgprot_noncached(PAGE_KERNEL)) == NULL)
 165                 return -ENOMEM;
 166
 167         /* Fixup hose IO resource */
 168         io_virt_offset = pcibios_io_space_offset(hose);
 169         hose->io_resource.start += io_virt_offset;
 170         hose->io_resource.end += io_virt_offset;
 171
 172         pr_debug("  hose->io_resource=%pR\n", &hose->io_resource);
 173
 174         return 0;
 175 }
 176
 177 int pcibios_map_io_space(struct pci_bus *bus)
 178 {
 179         WARN_ON(bus == NULL);
 180
 181         /* If this not a PHB, nothing to do, page tables still exist and
 182          * thus HPTEs will be faulted in when needed
 183          */
 184         if (bus->self) {
 185                 pr_debug("IO mapping for PCI-PCI bridge %s\n",
 186                          pci_name(bus->self));
 187                 pr_debug("  virt=0x%016llx...0x%016llx\n",
 188                          bus->resource[0]->start + _IO_BASE,
 189                          bus->resource[0]->end + _IO_BASE);
 190                 return 0;
 191         }
 192
 193         return pcibios_map_phb_io_space(pci_bus_to_host(bus));
 194 }
 195 EXPORT_SYMBOL_GPL(pcibios_map_io_space);
 196
 197 void pcibios_setup_phb_io_space(struct pci_controller *hose)
 198 {
 199         pcibios_map_phb_io_space(hose);
 200 }
 201
 202 #define IOBASE_BRIDGE_NUMBER    0
 203 #define IOBASE_MEMORY           1
 204 #define IOBASE_IO               2
 205 #define IOBASE_ISA_IO           3
 206 #define IOBASE_ISA_MEM          4
 207
 208 SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, in_bus,
 209                           unsigned long, in_devfn)
 210 {
 211         struct pci_controller* hose;
 212         struct pci_bus *tmp_bus, *bus = NULL;
 213         struct device_node *hose_node;
 214
 215         /* Argh ! Please forgive me for that hack, but that's the
 216          * simplest way to get existing XFree to not lockup on some
 217          * G5 machines... So when something asks for bus 0 io base
 218          * (bus 0 is HT root), we return the AGP one instead.
 219          */
 220         if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) {
 221                 struct device_node *agp;
 222
 223                 agp = of_find_compatible_node(NULL, NULL, "u3-agp");
 224                 if (agp)
 225                         in_bus = 0xf0;
 226                 of_node_put(agp);
 227         }
 228
 229         /* That syscall isn't quite compatible with PCI domains, but it's
 230          * used on pre-domains setup. We return the first match
 231          */
 232
 233         list_for_each_entry(tmp_bus, &pci_root_buses, node) {
 234                 if (in_bus >= tmp_bus->number &&
 235                     in_bus <= tmp_bus->busn_res.end) {
 236                         bus = tmp_bus;
 237                         break;
 238                 }
 239         }
 240         if (bus == NULL || bus->dev.of_node == NULL)
 241                 return -ENODEV;
 242
 243         hose_node = bus->dev.of_node;
 244         hose = PCI_DN(hose_node)->phb;
 245
 246         switch (which) {
 247         case IOBASE_BRIDGE_NUMBER:
 248                 return (long)hose->first_busno;
 249         case IOBASE_MEMORY:
 250                 return (long)hose->mem_offset[0];
 251         case IOBASE_IO:
 252                 return (long)hose->io_base_phys;
 253         case IOBASE_ISA_IO:
 254                 return (long)isa_io_base;
 255         case IOBASE_ISA_MEM:
 256                 return -EINVAL;
 257         }
 258
 259         return -EOPNOTSUPP;
 260 }
 261
 262 #ifdef CONFIG_NUMA
 263 int pcibus_to_node(struct pci_bus *bus)
 264 {
 265         struct pci_controller *phb = pci_bus_to_host(bus);
 266         return phb->node;
 267 }
 268 EXPORT_SYMBOL(pcibus_to_node);
 269 #endif