arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc
   4  *
   5  * QorIQ based Cache Controller Memory Mapped Registers
   6  *
   7  * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
   8  */
   9
  10 #ifndef __FSL_85XX_CACHE_CTLR_H__
  11 #define __FSL_85XX_CACHE_CTLR_H__
  12
  13 #define L2CR_L2FI               0x40000000      /* L2 flash invalidate */
  14 #define L2CR_L2IO               0x00200000      /* L2 instruction only */
  15 #define L2CR_SRAM_ZERO          0x00000000      /* L2SRAM zero size */
  16 #define L2CR_SRAM_FULL          0x00010000      /* L2SRAM full size */
  17 #define L2CR_SRAM_HALF          0x00020000      /* L2SRAM half size */
  18 #define L2CR_SRAM_TWO_HALFS     0x00030000      /* L2SRAM two half sizes */
  19 #define L2CR_SRAM_QUART         0x00040000      /* L2SRAM one quarter size */
  20 #define L2CR_SRAM_TWO_QUARTS    0x00050000      /* L2SRAM two quarter size */
  21 #define L2CR_SRAM_EIGHTH        0x00060000      /* L2SRAM one eighth size */
  22 #define L2CR_SRAM_TWO_EIGHTH    0x00070000      /* L2SRAM two eighth size */
  23
  24 #define L2SRAM_OPTIMAL_SZ_SHIFT 0x00000003      /* Optimum size for L2SRAM */
  25
  26 #define L2SRAM_BAR_MSK_LO18     0xFFFFC000      /* Lower 18 bits */
  27 #define L2SRAM_BARE_MSK_HI4     0x0000000F      /* Upper 4 bits */
  28
  29 enum cache_sram_lock_ways {
  30         LOCK_WAYS_ZERO,
  31         LOCK_WAYS_EIGHTH,
  32         LOCK_WAYS_TWO_EIGHTH,
  33         LOCK_WAYS_HALF = 4,
  34         LOCK_WAYS_FULL = 8,
  35 };
  36
  37 struct mpc85xx_l2ctlr {
  38         u32     ctl;            /* 0x000 - L2 control */
  39         u8      res1[0xC];
  40         u32     ewar0;          /* 0x010 - External write address 0 */
  41         u32     ewarea0;        /* 0x014 - External write address extended 0 */
  42         u32     ewcr0;          /* 0x018 - External write ctrl */
  43         u8      res2[4];
  44         u32     ewar1;          /* 0x020 - External write address 1 */
  45         u32     ewarea1;        /* 0x024 - External write address extended 1 */
  46         u32     ewcr1;          /* 0x028 - External write ctrl 1 */
  47         u8      res3[4];
  48         u32     ewar2;          /* 0x030 - External write address 2 */
  49         u32     ewarea2;        /* 0x034 - External write address extended 2 */
  50         u32     ewcr2;          /* 0x038 - External write ctrl 2 */
  51         u8      res4[4];
  52         u32     ewar3;          /* 0x040 - External write address 3 */
  53         u32     ewarea3;        /* 0x044 - External write address extended 3 */
  54         u32     ewcr3;          /* 0x048 - External write ctrl 3 */
  55         u8      res5[0xB4];
  56         u32     srbar0;         /* 0x100 - SRAM base address 0 */
  57         u32     srbarea0;       /* 0x104 - SRAM base addr reg ext address 0 */
  58         u32     srbar1;         /* 0x108 - SRAM base address 1 */
  59         u32     srbarea1;       /* 0x10C - SRAM base addr reg ext address 1 */
  60         u8      res6[0xCF0];
  61         u32     errinjhi;       /* 0xE00 - Error injection mask high */
  62         u32     errinjlo;       /* 0xE04 - Error injection mask low */
  63         u32     errinjctl;      /* 0xE08 - Error injection tag/ecc control */
  64         u8      res7[0x14];
  65         u32     captdatahi;     /* 0xE20 - Error data high capture */
  66         u32     captdatalo;     /* 0xE24 - Error data low capture */
  67         u32     captecc;        /* 0xE28 - Error syndrome */
  68         u8      res8[0x14];
  69         u32     errdet;         /* 0xE40 - Error detect */
  70         u32     errdis;         /* 0xE44 - Error disable */
  71         u32     errinten;       /* 0xE48 - Error interrupt enable */
  72         u32     errattr;        /* 0xE4c - Error attribute capture */
  73         u32     erradrrl;       /* 0xE50 - Error address capture low */
  74         u32     erradrrh;       /* 0xE54 - Error address capture high */
  75         u32     errctl;         /* 0xE58 - Error control */
  76         u8      res9[0x1A4];
  77 };
  78
  79 struct sram_parameters {
  80         unsigned int sram_size;
  81         phys_addr_t sram_offset;
  82 };
  83
  84 extern int instantiate_cache_sram(struct platform_device *dev,
  85                 struct sram_parameters sram_params);
  86 extern void remove_cache_sram(struct platform_device *dev);
  87
  88 #endif /* __FSL_85XX_CACHE_CTLR_H__ */