arch/sparc/kernel/time_32.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* linux/arch/sparc/kernel/time.c
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
   5  * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
   6  *
   7  * Chris Davis (cdavis@cois.on.ca) 03/27/1998
   8  * Added support for the intersil on the sun4/4200
   9  *
  10  * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
  11  * Support for MicroSPARC-IIep, PCI CPU.
  12  *
  13  * This file handles the Sparc specific time handling details.
  14  *
  15  * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
  16  *              "A Kernel Model for Precision Timekeeping" by Dave Mills
  17  */
  18 #include <linux/errno.h>
  19 #include <linux/module.h>
  20 #include <linux/sched.h>
  21 #include <linux/kernel.h>
  22 #include <linux/param.h>
  23 #include <linux/string.h>
  24 #include <linux/mm.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/time.h>
  27 #include <linux/rtc/m48t59.h>
  28 #include <linux/timex.h>
  29 #include <linux/clocksource.h>
  30 #include <linux/clockchips.h>
  31 #include <linux/init.h>
  32 #include <linux/pci.h>
  33 #include <linux/ioport.h>
  34 #include <linux/profile.h>
  35 #include <linux/of.h>
  36 #include <linux/of_device.h>
  37 #include <linux/platform_device.h>
  38
  39 #include <asm/mc146818rtc.h>
  40 #include <asm/oplib.h>
  41 #include <asm/timex.h>
  42 #include <asm/timer.h>
  43 #include <asm/irq.h>
  44 #include <asm/io.h>
  45 #include <asm/idprom.h>
  46 #include <asm/page.h>
  47 #include <asm/pcic.h>
  48 #include <asm/irq_regs.h>
  49 #include <asm/setup.h>
  50
  51 #include "kernel.h"
  52 #include "irq.h"
  53
  54 static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
  55 static __volatile__ u64 timer_cs_internal_counter = 0;
  56 static char timer_cs_enabled = 0;
  57
  58 static struct clock_event_device timer_ce;
  59 static char timer_ce_enabled = 0;
  60
  61 #ifdef CONFIG_SMP
  62 DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
  63 #endif
  64
  65 DEFINE_SPINLOCK(rtc_lock);
  66 EXPORT_SYMBOL(rtc_lock);
  67
  68 unsigned long profile_pc(struct pt_regs *regs)
  69 {
  70         extern char __copy_user_begin[], __copy_user_end[];
  71         extern char __bzero_begin[], __bzero_end[];
  72
  73         unsigned long pc = regs->pc;
  74
  75         if (in_lock_functions(pc) ||
  76             (pc >= (unsigned long) __copy_user_begin &&
  77              pc < (unsigned long) __copy_user_end) ||
  78             (pc >= (unsigned long) __bzero_begin &&
  79              pc < (unsigned long) __bzero_end))
  80                 pc = regs->u_regs[UREG_RETPC];
  81         return pc;
  82 }
  83
  84 EXPORT_SYMBOL(profile_pc);
  85
  86 volatile u32 __iomem *master_l10_counter;
  87
  88 irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
  89 {
  90         if (timer_cs_enabled) {
  91                 write_seqlock(&timer_cs_lock);
  92                 timer_cs_internal_counter++;
  93                 sparc_config.clear_clock_irq();
  94                 write_sequnlock(&timer_cs_lock);
  95         } else {
  96                 sparc_config.clear_clock_irq();
  97         }
  98
  99         if (timer_ce_enabled)
 100                 timer_ce.event_handler(&timer_ce);
 101
 102         return IRQ_HANDLED;
 103 }
 104
 105 static int timer_ce_shutdown(struct clock_event_device *evt)
 106 {
 107         timer_ce_enabled = 0;
 108         smp_mb();
 109         return 0;
 110 }
 111
 112 static int timer_ce_set_periodic(struct clock_event_device *evt)
 113 {
 114         timer_ce_enabled = 1;
 115         smp_mb();
 116         return 0;
 117 }
 118
 119 static __init void setup_timer_ce(void)
 120 {
 121         struct clock_event_device *ce = &timer_ce;
 122
 123         BUG_ON(smp_processor_id() != boot_cpu_id);
 124
 125         ce->name     = "timer_ce";
 126         ce->rating   = 100;
 127         ce->features = CLOCK_EVT_FEAT_PERIODIC;
 128         ce->set_state_shutdown = timer_ce_shutdown;
 129         ce->set_state_periodic = timer_ce_set_periodic;
 130         ce->tick_resume = timer_ce_set_periodic;
 131         ce->cpumask  = cpu_possible_mask;
 132         ce->shift    = 32;
 133         ce->mult     = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
 134                               ce->shift);
 135         clockevents_register_device(ce);
 136 }
 137
 138 static unsigned int sbus_cycles_offset(void)
 139 {
 140         u32 val, offset;
 141
 142         val = sbus_readl(master_l10_counter);
 143         offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
 144
 145         /* Limit hit? */
 146         if (val & TIMER_LIMIT_BIT)
 147                 offset += sparc_config.cs_period;
 148
 149         return offset;
 150 }
 151
 152 static u64 timer_cs_read(struct clocksource *cs)
 153 {
 154         unsigned int seq, offset;
 155         u64 cycles;
 156
 157         do {
 158                 seq = read_seqbegin(&timer_cs_lock);
 159
 160                 cycles = timer_cs_internal_counter;
 161                 offset = sparc_config.get_cycles_offset();
 162         } while (read_seqretry(&timer_cs_lock, seq));
 163
 164         /* Count absolute cycles */
 165         cycles *= sparc_config.cs_period;
 166         cycles += offset;
 167
 168         return cycles;
 169 }
 170
 171 static struct clocksource timer_cs = {
 172         .name   = "timer_cs",
 173         .rating = 100,
 174         .read   = timer_cs_read,
 175         .mask   = CLOCKSOURCE_MASK(64),
 176         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 177 };
 178
 179 static __init int setup_timer_cs(void)
 180 {
 181         timer_cs_enabled = 1;
 182         return clocksource_register_hz(&timer_cs, sparc_config.clock_rate);
 183 }
 184
 185 #ifdef CONFIG_SMP
 186 static int percpu_ce_shutdown(struct clock_event_device *evt)
 187 {
 188         int cpu = cpumask_first(evt->cpumask);
 189
 190         sparc_config.load_profile_irq(cpu, 0);
 191         return 0;
 192 }
 193
 194 static int percpu_ce_set_periodic(struct clock_event_device *evt)
 195 {
 196         int cpu = cpumask_first(evt->cpumask);
 197
 198         sparc_config.load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
 199         return 0;
 200 }
 201
 202 static int percpu_ce_set_next_event(unsigned long delta,
 203                                     struct clock_event_device *evt)
 204 {
 205         int cpu = cpumask_first(evt->cpumask);
 206         unsigned int next = (unsigned int)delta;
 207
 208         sparc_config.load_profile_irq(cpu, next);
 209         return 0;
 210 }
 211
 212 void register_percpu_ce(int cpu)
 213 {
 214         struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
 215         unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
 216
 217         if (sparc_config.features & FEAT_L14_ONESHOT)
 218                 features |= CLOCK_EVT_FEAT_ONESHOT;
 219
 220         ce->name           = "percpu_ce";
 221         ce->rating         = 200;
 222         ce->features       = features;
 223         ce->set_state_shutdown = percpu_ce_shutdown;
 224         ce->set_state_periodic = percpu_ce_set_periodic;
 225         ce->set_state_oneshot = percpu_ce_shutdown;
 226         ce->set_next_event = percpu_ce_set_next_event;
 227         ce->cpumask        = cpumask_of(cpu);
 228         ce->shift          = 32;
 229         ce->mult           = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
 230                                     ce->shift);
 231         ce->max_delta_ns   = clockevent_delta2ns(sparc_config.clock_rate, ce);
 232         ce->max_delta_ticks = (unsigned long)sparc_config.clock_rate;
 233         ce->min_delta_ns   = clockevent_delta2ns(100, ce);
 234         ce->min_delta_ticks = 100;
 235
 236         clockevents_register_device(ce);
 237 }
 238 #endif
 239
 240 static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
 241 {
 242         struct platform_device *pdev = to_platform_device(dev);
 243         struct m48t59_plat_data *pdata = pdev->dev.platform_data;
 244
 245         return readb(pdata->ioaddr + ofs);
 246 }
 247
 248 static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
 249 {
 250         struct platform_device *pdev = to_platform_device(dev);
 251         struct m48t59_plat_data *pdata = pdev->dev.platform_data;
 252
 253         writeb(val, pdata->ioaddr + ofs);
 254 }
 255
 256 static struct m48t59_plat_data m48t59_data = {
 257         .read_byte = mostek_read_byte,
 258         .write_byte = mostek_write_byte,
 259 };
 260
 261 /* resource is set at runtime */
 262 static struct platform_device m48t59_rtc = {
 263         .name           = "rtc-m48t59",
 264         .id             = 0,
 265         .num_resources  = 1,
 266         .dev    = {
 267                 .platform_data = &m48t59_data,
 268         },
 269 };
 270
 271 static int clock_probe(struct platform_device *op)
 272 {
 273         struct device_node *dp = op->dev.of_node;
 274         const char *model = of_get_property(dp, "model", NULL);
 275
 276         if (!model)
 277                 return -ENODEV;
 278
 279         /* Only the primary RTC has an address property */
 280         if (!of_find_property(dp, "address", NULL))
 281                 return -ENODEV;
 282
 283         m48t59_rtc.resource = &op->resource[0];
 284         if (!strcmp(model, "mk48t02")) {
 285                 /* Map the clock register io area read-only */
 286                 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
 287                                                 2048, "rtc-m48t59");
 288                 m48t59_data.type = M48T59RTC_TYPE_M48T02;
 289         } else if (!strcmp(model, "mk48t08")) {
 290                 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
 291                                                 8192, "rtc-m48t59");
 292                 m48t59_data.type = M48T59RTC_TYPE_M48T08;
 293         } else
 294                 return -ENODEV;
 295
 296         if (platform_device_register(&m48t59_rtc) < 0)
 297                 printk(KERN_ERR "Registering RTC device failed\n");
 298
 299         return 0;
 300 }
 301
 302 static const struct of_device_id clock_match[] = {
 303         {
 304                 .name = "eeprom",
 305         },
 306         {},
 307 };
 308
 309 static struct platform_driver clock_driver = {
 310         .probe          = clock_probe,
 311         .driver = {
 312                 .name = "rtc",
 313                 .of_match_table = clock_match,
 314         },
 315 };
 316
 317
 318 /* Probe for the mostek real time clock chip. */
 319 static int __init clock_init(void)
 320 {
 321         return platform_driver_register(&clock_driver);
 322 }
 323 /* Must be after subsys_initcall() so that busses are probed.  Must
 324  * be before device_initcall() because things like the RTC driver
 325  * need to see the clock registers.
 326  */
 327 fs_initcall(clock_init);
 328
 329 static void __init sparc32_late_time_init(void)
 330 {
 331         if (sparc_config.features & FEAT_L10_CLOCKEVENT)
 332                 setup_timer_ce();
 333         if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
 334                 setup_timer_cs();
 335 #ifdef CONFIG_SMP
 336         register_percpu_ce(smp_processor_id());
 337 #endif
 338 }
 339
 340 static void __init sbus_time_init(void)
 341 {
 342         sparc_config.get_cycles_offset = sbus_cycles_offset;
 343         sparc_config.init_timers();
 344 }
 345
 346 void __init time_init(void)
 347 {
 348         sparc_config.features = 0;
 349         late_time_init = sparc32_late_time_init;
 350
 351         if (pcic_present())
 352                 pci_time_init();
 353         else
 354                 sbus_time_init();
 355 }
 356