arch/unicore32/kernel/pci.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * linux/arch/unicore32/kernel/pci.c
   4  *
   5  * Code specific to PKUnity SoC and UniCore ISA
   6  *
   7  * Copyright (C) 2001-2010 GUAN Xue-tao
   8  *
   9  *  PCI bios-type initialisation for PCI machines
  10  */
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/pci.h>
  15 #include <linux/slab.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18
  19 static int debug_pci;
  20
  21 #define CONFIG_CMD(bus, devfn, where)   \
  22         (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
  23
  24 static int
  25 puv3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  26                         int size, u32 *value)
  27 {
  28         writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR);
  29         switch (size) {
  30         case 1:
  31                 *value = (readl(PCICFG_DATA) >> ((where & 3) * 8)) & 0xFF;
  32                 break;
  33         case 2:
  34                 *value = (readl(PCICFG_DATA) >> ((where & 2) * 8)) & 0xFFFF;
  35                 break;
  36         case 4:
  37                 *value = readl(PCICFG_DATA);
  38                 break;
  39         }
  40         return PCIBIOS_SUCCESSFUL;
  41 }
  42
  43 static int
  44 puv3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  45                         int size, u32 value)
  46 {
  47         writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR);
  48         switch (size) {
  49         case 1:
  50                 writel((readl(PCICFG_DATA) & ~FMASK(8, (where&3)*8))
  51                         | FIELD(value, 8, (where&3)*8), PCICFG_DATA);
  52                 break;
  53         case 2:
  54                 writel((readl(PCICFG_DATA) & ~FMASK(16, (where&2)*8))
  55                         | FIELD(value, 16, (where&2)*8), PCICFG_DATA);
  56                 break;
  57         case 4:
  58                 writel(value, PCICFG_DATA);
  59                 break;
  60         }
  61         return PCIBIOS_SUCCESSFUL;
  62 }
  63
  64 struct pci_ops pci_puv3_ops = {
  65         .read  = puv3_read_config,
  66         .write = puv3_write_config,
  67 };
  68
  69 void pci_puv3_preinit(void)
  70 {
  71         printk(KERN_DEBUG "PCI: PKUnity PCI Controller Initializing ...\n");
  72         /* config PCI bridge base */
  73         writel(io_v2p(PKUNITY_PCIBRI_BASE), PCICFG_BRIBASE);
  74
  75         writel(0, PCIBRI_AHBCTL0);
  76         writel(io_v2p(PKUNITY_PCIBRI_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0);
  77         writel(0xFFFF0000, PCIBRI_AHBAMR0);
  78         writel(0, PCIBRI_AHBTAR0);
  79
  80         writel(PCIBRI_CTLx_AT, PCIBRI_AHBCTL1);
  81         writel(io_v2p(PKUNITY_PCILIO_BASE) | PCIBRI_BARx_IO, PCIBRI_AHBBAR1);
  82         writel(0xFFFF0000, PCIBRI_AHBAMR1);
  83         writel(0x00000000, PCIBRI_AHBTAR1);
  84
  85         writel(PCIBRI_CTLx_PREF, PCIBRI_AHBCTL2);
  86         writel(io_v2p(PKUNITY_PCIMEM_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR2);
  87         writel(0xF8000000, PCIBRI_AHBAMR2);
  88         writel(0, PCIBRI_AHBTAR2);
  89
  90         writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_BAR1);
  91
  92         writel(PCIBRI_CTLx_AT | PCIBRI_CTLx_PREF, PCIBRI_PCICTL0);
  93         writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_PCIBAR0);
  94         writel(0xF8000000, PCIBRI_PCIAMR0);
  95         writel(PKUNITY_SDRAM_BASE, PCIBRI_PCITAR0);
  96
  97         writel(readl(PCIBRI_CMD) | PCIBRI_CMD_IO | PCIBRI_CMD_MEM, PCIBRI_CMD);
  98 }
  99
 100 static int pci_puv3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 101 {
 102         if (dev->bus->number == 0) {
 103 #ifdef CONFIG_ARCH_FPGA /* 4 pci slots */
 104                 if      (dev->devfn == 0x00)
 105                         return IRQ_PCIINTA;
 106                 else if (dev->devfn == 0x08)
 107                         return IRQ_PCIINTB;
 108                 else if (dev->devfn == 0x10)
 109                         return IRQ_PCIINTC;
 110                 else if (dev->devfn == 0x18)
 111                         return IRQ_PCIINTD;
 112 #endif
 113 #ifdef CONFIG_PUV3_DB0913 /* 3 pci slots */
 114                 if      (dev->devfn == 0x30)
 115                         return IRQ_PCIINTB;
 116                 else if (dev->devfn == 0x60)
 117                         return IRQ_PCIINTC;
 118                 else if (dev->devfn == 0x58)
 119                         return IRQ_PCIINTD;
 120 #endif
 121 #if     defined(CONFIG_PUV3_NB0916) || defined(CONFIG_PUV3_SMW0919)
 122                 /* only support 2 pci devices */
 123                 if      (dev->devfn == 0x00)
 124                         return IRQ_PCIINTC; /* sata */
 125 #endif
 126         }
 127         return -1;
 128 }
 129
 130 /*
 131  * Only first 128MB of memory can be accessed via PCI.
 132  * We use GFP_DMA to allocate safe buffers to do map/unmap.
 133  * This is really ugly and we need a better way of specifying
 134  * DMA-capable regions of memory.
 135  */
 136 void __init puv3_pci_adjust_zones(unsigned long *zone_size,
 137         unsigned long *zhole_size)
 138 {
 139         unsigned int sz = SZ_128M >> PAGE_SHIFT;
 140
 141         /*
 142          * Only adjust if > 128M on current system
 143          */
 144         if (zone_size[0] <= sz)
 145                 return;
 146
 147         zone_size[1] = zone_size[0] - sz;
 148         zone_size[0] = sz;
 149         zhole_size[1] = zhole_size[0];
 150         zhole_size[0] = 0;
 151 }
 152
 153 /*
 154  * If the bus contains any of these devices, then we must not turn on
 155  * parity checking of any kind.
 156  */
 157 static inline int pdev_bad_for_parity(struct pci_dev *dev)
 158 {
 159         return 0;
 160 }
 161
 162 /*
 163  * pcibios_fixup_bus - Called after each bus is probed,
 164  * but before its children are examined.
 165  */
 166 void pcibios_fixup_bus(struct pci_bus *bus)
 167 {
 168         struct pci_dev *dev;
 169         u16 features = PCI_COMMAND_SERR
 170                 | PCI_COMMAND_PARITY
 171                 | PCI_COMMAND_FAST_BACK;
 172
 173         bus->resource[0] = &ioport_resource;
 174         bus->resource[1] = &iomem_resource;
 175
 176         /*
 177          * Walk the devices on this bus, working out what we can
 178          * and can't support.
 179          */
 180         list_for_each_entry(dev, &bus->devices, bus_list) {
 181                 u16 status;
 182
 183                 pci_read_config_word(dev, PCI_STATUS, &status);
 184
 185                 /*
 186                  * If any device on this bus does not support fast back
 187                  * to back transfers, then the bus as a whole is not able
 188                  * to support them.  Having fast back to back transfers
 189                  * on saves us one PCI cycle per transaction.
 190                  */
 191                 if (!(status & PCI_STATUS_FAST_BACK))
 192                         features &= ~PCI_COMMAND_FAST_BACK;
 193
 194                 if (pdev_bad_for_parity(dev))
 195                         features &= ~(PCI_COMMAND_SERR
 196                                         | PCI_COMMAND_PARITY);
 197
 198                 switch (dev->class >> 8) {
 199                 case PCI_CLASS_BRIDGE_PCI:
 200                         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
 201                         status |= PCI_BRIDGE_CTL_PARITY
 202                                 | PCI_BRIDGE_CTL_MASTER_ABORT;
 203                         status &= ~(PCI_BRIDGE_CTL_BUS_RESET
 204                                 | PCI_BRIDGE_CTL_FAST_BACK);
 205                         pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
 206                         break;
 207
 208                 case PCI_CLASS_BRIDGE_CARDBUS:
 209                         pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL,
 210                                         &status);
 211                         status |= PCI_CB_BRIDGE_CTL_PARITY
 212                                 | PCI_CB_BRIDGE_CTL_MASTER_ABORT;
 213                         pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL,
 214                                         status);
 215                         break;
 216                 }
 217         }
 218
 219         /*
 220          * Now walk the devices again, this time setting them up.
 221          */
 222         list_for_each_entry(dev, &bus->devices, bus_list) {
 223                 u16 cmd;
 224
 225                 pci_read_config_word(dev, PCI_COMMAND, &cmd);
 226                 cmd |= features;
 227                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 228
 229                 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
 230                                       L1_CACHE_BYTES >> 2);
 231         }
 232
 233         /*
 234          * Propagate the flags to the PCI bridge.
 235          */
 236         if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
 237                 if (features & PCI_COMMAND_FAST_BACK)
 238                         bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
 239                 if (features & PCI_COMMAND_PARITY)
 240                         bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
 241         }
 242
 243         /*
 244          * Report what we did for this bus
 245          */
 246         printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
 247                 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
 248 }
 249 EXPORT_SYMBOL(pcibios_fixup_bus);
 250
 251 static struct resource busn_resource = {
 252         .name   = "PCI busn",
 253         .start  = 0,
 254         .end    = 255,
 255         .flags  = IORESOURCE_BUS,
 256 };
 257
 258 static int __init pci_common_init(void)
 259 {
 260         struct pci_bus *puv3_bus;
 261         struct pci_host_bridge *bridge;
 262         int ret;
 263
 264         bridge = pci_alloc_host_bridge(0);
 265         if (!bridge)
 266                 return -ENOMEM;
 267
 268         pci_puv3_preinit();
 269
 270         pci_add_resource(&bridge->windows, &ioport_resource);
 271         pci_add_resource(&bridge->windows, &iomem_resource);
 272         pci_add_resource(&bridge->windows, &busn_resource);
 273         bridge->sysdata = NULL;
 274         bridge->busnr = 0;
 275         bridge->ops = &pci_puv3_ops;
 276         bridge->swizzle_irq = pci_common_swizzle;
 277         bridge->map_irq = pci_puv3_map_irq;
 278
 279         /* Scan our single hose.  */
 280         ret = pci_scan_root_bus_bridge(bridge);
 281         if (ret) {
 282                 pci_free_host_bridge(bridge);
 283                 return;
 284         }
 285
 286         puv3_bus = bridge->bus;
 287
 288         if (!puv3_bus)
 289                 panic("PCI: unable to scan bus!");
 290
 291         pci_bus_size_bridges(puv3_bus);
 292         pci_bus_assign_resources(puv3_bus);
 293         pci_bus_add_devices(puv3_bus);
 294         return 0;
 295 }
 296 subsys_initcall(pci_common_init);
 297
 298 char * __init pcibios_setup(char *str)
 299 {
 300         if (!strcmp(str, "debug")) {
 301                 debug_pci = 1;
 302                 return NULL;
 303         }
 304         return str;
 305 }
 306
 307 void pcibios_set_master(struct pci_dev *dev)
 308 {
 309         /* No special bus mastering setup handling */
 310 }
 311
 312 /*
 313  * From arch/i386/kernel/pci-i386.c:
 314  *
 315  * We need to avoid collisions with `mirrored' VGA ports
 316  * and other strange ISA hardware, so we always want the
 317  * addresses to be allocated in the 0x000-0x0ff region
 318  * modulo 0x400.
 319  *
 320  * Why? Because some silly external IO cards only decode
 321  * the low 10 bits of the IO address. The 0x00-0xff region
 322  * is reserved for motherboard devices that decode all 16
 323  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 324  * but we want to try to avoid allocating at 0x2900-0x2bff
 325  * which might be mirrored at 0x0100-0x03ff..
 326  */
 327 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 328                                 resource_size_t size, resource_size_t align)
 329 {
 330         resource_size_t start = res->start;
 331
 332         if (res->flags & IORESOURCE_IO && start & 0x300)
 333                 start = (start + 0x3ff) & ~0x3ff;
 334
 335         start = (start + align - 1) & ~(align - 1);
 336
 337         return start;
 338 }
 339
 340 /**
 341  * pcibios_enable_device - Enable I/O and memory.
 342  * @dev: PCI device to be enabled
 343  */
 344 int pcibios_enable_device(struct pci_dev *dev, int mask)
 345 {
 346         u16 cmd, old_cmd;
 347         int idx;
 348         struct resource *r;
 349
 350         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 351         old_cmd = cmd;
 352         for (idx = 0; idx < 6; idx++) {
 353                 /* Only set up the requested stuff */
 354                 if (!(mask & (1 << idx)))
 355                         continue;
 356
 357                 r = dev->resource + idx;
 358                 if (!r->start && r->end) {
 359                         printk(KERN_ERR "PCI: Device %s not available because"
 360                                " of resource collisions\n", pci_name(dev));
 361                         return -EINVAL;
 362                 }
 363                 if (r->flags & IORESOURCE_IO)
 364                         cmd |= PCI_COMMAND_IO;
 365                 if (r->flags & IORESOURCE_MEM)
 366                         cmd |= PCI_COMMAND_MEMORY;
 367         }
 368
 369         /*
 370          * Bridges (eg, cardbus bridges) need to be fully enabled
 371          */
 372         if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
 373                 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 374
 375         if (cmd != old_cmd) {
 376                 printk("PCI: enabling device %s (%04x -> %04x)\n",
 377                        pci_name(dev), old_cmd, cmd);
 378                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 379         }
 380         return 0;
 381 }