arch/x86/events/intel/cstate.c

   1 /*
   2  * Support cstate residency counters
   3  *
   4  * Copyright (C) 2015, Intel Corp.
   5  * Author: Kan Liang (kan.liang@intel.com)
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Library General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Library General Public License for more details.
  16  *
  17  */
  18
  19 /*
  20  * This file export cstate related free running (read-only) counters
  21  * for perf. These counters may be use simultaneously by other tools,
  22  * such as turbostat. However, it still make sense to implement them
  23  * in perf. Because we can conveniently collect them together with
  24  * other events, and allow to use them from tools without special MSR
  25  * access code.
  26  *
  27  * The events only support system-wide mode counting. There is no
  28  * sampling support because it is not supported by the hardware.
  29  *
  30  * According to counters' scope and category, two PMUs are registered
  31  * with the perf_event core subsystem.
  32  *  - 'cstate_core': The counter is available for each physical core.
  33  *    The counters include CORE_C*_RESIDENCY.
  34  *  - 'cstate_pkg': The counter is available for each physical package.
  35  *    The counters include PKG_C*_RESIDENCY.
  36  *
  37  * All of these counters are specified in the Intel® 64 and IA-32
  38  * Architectures Software Developer.s Manual Vol3b.
  39  *
  40  * Model specific counters:
  41  *      MSR_CORE_C1_RES: CORE C1 Residency Counter
  42  *                       perf code: 0x00
  43  *                       Available model: SLM,AMT,GLM,CNL
  44  *                       Scope: Core (each processor core has a MSR)
  45  *      MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
  46  *                             perf code: 0x01
  47  *                             Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
  48  *                                              CNL,KBL,CML
  49  *                             Scope: Core
  50  *      MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
  51  *                             perf code: 0x02
  52  *                             Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
  53  *                                              SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL
  54  *                             Scope: Core
  55  *      MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
  56  *                             perf code: 0x03
  57  *                             Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
  58  *                                              ICL,TGL
  59  *                             Scope: Core
  60  *      MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
  61  *                             perf code: 0x00
  62  *                             Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
  63  *                                              KBL,CML,ICL,TGL
  64  *                             Scope: Package (physical package)
  65  *      MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
  66  *                             perf code: 0x01
  67  *                             Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
  68  *                                              GLM,CNL,KBL,CML,ICL,TGL
  69  *                             Scope: Package (physical package)
  70  *      MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.
  71  *                             perf code: 0x02
  72  *                             Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
  73  *                                              SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL
  74  *                             Scope: Package (physical package)
  75  *      MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
  76  *                             perf code: 0x03
  77  *                             Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
  78  *                                              KBL,CML,ICL,TGL
  79  *                             Scope: Package (physical package)
  80  *      MSR_PKG_C8_RESIDENCY:  Package C8 Residency Counter.
  81  *                             perf code: 0x04
  82  *                             Available model: HSW ULT,KBL,CNL,CML,ICL,TGL
  83  *                             Scope: Package (physical package)
  84  *      MSR_PKG_C9_RESIDENCY:  Package C9 Residency Counter.
  85  *                             perf code: 0x05
  86  *                             Available model: HSW ULT,KBL,CNL,CML,ICL,TGL
  87  *                             Scope: Package (physical package)
  88  *      MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
  89  *                             perf code: 0x06
  90  *                             Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL
  91  *                             Scope: Package (physical package)
  92  *
  93  */
  94
  95 #include <linux/module.h>
  96 #include <linux/slab.h>
  97 #include <linux/perf_event.h>
  98 #include <linux/nospec.h>
  99 #include <asm/cpu_device_id.h>
 100 #include <asm/intel-family.h>
 101 #include "../perf_event.h"
 102 #include "../probe.h"
 103
 104 MODULE_LICENSE("GPL");
 105
 106 #define DEFINE_CSTATE_FORMAT_ATTR(_var, _name, _format)         \
 107 static ssize_t __cstate_##_var##_show(struct kobject *kobj,     \
 108                                 struct kobj_attribute *attr,    \
 109                                 char *page)                     \
 110 {                                                               \
 111         BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);             \
 112         return sprintf(page, _format "\n");                     \
 113 }                                                               \
 114 static struct kobj_attribute format_attr_##_var =               \
 115         __ATTR(_name, 0444, __cstate_##_var##_show, NULL)
 116
 117 static ssize_t cstate_get_attr_cpumask(struct device *dev,
 118                                        struct device_attribute *attr,
 119                                        char *buf);
 120
 121 /* Model -> events mapping */
 122 struct cstate_model {
 123         unsigned long           core_events;
 124         unsigned long           pkg_events;
 125         unsigned long           quirks;
 126 };
 127
 128 /* Quirk flags */
 129 #define SLM_PKG_C6_USE_C7_MSR   (1UL << 0)
 130 #define KNL_CORE_C6_MSR         (1UL << 1)
 131
 132 struct perf_cstate_msr {
 133         u64     msr;
 134         struct  perf_pmu_events_attr *attr;
 135 };
 136
 137
 138 /* cstate_core PMU */
 139 static struct pmu cstate_core_pmu;
 140 static bool has_cstate_core;
 141
 142 enum perf_cstate_core_events {
 143         PERF_CSTATE_CORE_C1_RES = 0,
 144         PERF_CSTATE_CORE_C3_RES,
 145         PERF_CSTATE_CORE_C6_RES,
 146         PERF_CSTATE_CORE_C7_RES,
 147
 148         PERF_CSTATE_CORE_EVENT_MAX,
 149 };
 150
 151 PMU_EVENT_ATTR_STRING(c1-residency, attr_cstate_core_c1, "event=0x00");
 152 PMU_EVENT_ATTR_STRING(c3-residency, attr_cstate_core_c3, "event=0x01");
 153 PMU_EVENT_ATTR_STRING(c6-residency, attr_cstate_core_c6, "event=0x02");
 154 PMU_EVENT_ATTR_STRING(c7-residency, attr_cstate_core_c7, "event=0x03");
 155
 156 static unsigned long core_msr_mask;
 157
 158 PMU_EVENT_GROUP(events, cstate_core_c1);
 159 PMU_EVENT_GROUP(events, cstate_core_c3);
 160 PMU_EVENT_GROUP(events, cstate_core_c6);
 161 PMU_EVENT_GROUP(events, cstate_core_c7);
 162
 163 static bool test_msr(int idx, void *data)
 164 {
 165         return test_bit(idx, (unsigned long *) data);
 166 }
 167
 168 static struct perf_msr core_msr[] = {
 169         [PERF_CSTATE_CORE_C1_RES] = { MSR_CORE_C1_RES,          &group_cstate_core_c1,  test_msr },
 170         [PERF_CSTATE_CORE_C3_RES] = { MSR_CORE_C3_RESIDENCY,    &group_cstate_core_c3,  test_msr },
 171         [PERF_CSTATE_CORE_C6_RES] = { MSR_CORE_C6_RESIDENCY,    &group_cstate_core_c6,  test_msr },
 172         [PERF_CSTATE_CORE_C7_RES] = { MSR_CORE_C7_RESIDENCY,    &group_cstate_core_c7,  test_msr },
 173 };
 174
 175 static struct attribute *attrs_empty[] = {
 176         NULL,
 177 };
 178
 179 /*
 180  * There are no default events, but we need to create
 181  * "events" group (with empty attrs) before updating
 182  * it with detected events.
 183  */
 184 static struct attribute_group core_events_attr_group = {
 185         .name = "events",
 186         .attrs = attrs_empty,
 187 };
 188
 189 DEFINE_CSTATE_FORMAT_ATTR(core_event, event, "config:0-63");
 190 static struct attribute *core_format_attrs[] = {
 191         &format_attr_core_event.attr,
 192         NULL,
 193 };
 194
 195 static struct attribute_group core_format_attr_group = {
 196         .name = "format",
 197         .attrs = core_format_attrs,
 198 };
 199
 200 static cpumask_t cstate_core_cpu_mask;
 201 static DEVICE_ATTR(cpumask, S_IRUGO, cstate_get_attr_cpumask, NULL);
 202
 203 static struct attribute *cstate_cpumask_attrs[] = {
 204         &dev_attr_cpumask.attr,
 205         NULL,
 206 };
 207
 208 static struct attribute_group cpumask_attr_group = {
 209         .attrs = cstate_cpumask_attrs,
 210 };
 211
 212 static const struct attribute_group *core_attr_groups[] = {
 213         &core_events_attr_group,
 214         &core_format_attr_group,
 215         &cpumask_attr_group,
 216         NULL,
 217 };
 218
 219 /* cstate_pkg PMU */
 220 static struct pmu cstate_pkg_pmu;
 221 static bool has_cstate_pkg;
 222
 223 enum perf_cstate_pkg_events {
 224         PERF_CSTATE_PKG_C2_RES = 0,
 225         PERF_CSTATE_PKG_C3_RES,
 226         PERF_CSTATE_PKG_C6_RES,
 227         PERF_CSTATE_PKG_C7_RES,
 228         PERF_CSTATE_PKG_C8_RES,
 229         PERF_CSTATE_PKG_C9_RES,
 230         PERF_CSTATE_PKG_C10_RES,
 231
 232         PERF_CSTATE_PKG_EVENT_MAX,
 233 };
 234
 235 PMU_EVENT_ATTR_STRING(c2-residency,  attr_cstate_pkg_c2,  "event=0x00");
 236 PMU_EVENT_ATTR_STRING(c3-residency,  attr_cstate_pkg_c3,  "event=0x01");
 237 PMU_EVENT_ATTR_STRING(c6-residency,  attr_cstate_pkg_c6,  "event=0x02");
 238 PMU_EVENT_ATTR_STRING(c7-residency,  attr_cstate_pkg_c7,  "event=0x03");
 239 PMU_EVENT_ATTR_STRING(c8-residency,  attr_cstate_pkg_c8,  "event=0x04");
 240 PMU_EVENT_ATTR_STRING(c9-residency,  attr_cstate_pkg_c9,  "event=0x05");
 241 PMU_EVENT_ATTR_STRING(c10-residency, attr_cstate_pkg_c10, "event=0x06");
 242
 243 static unsigned long pkg_msr_mask;
 244
 245 PMU_EVENT_GROUP(events, cstate_pkg_c2);
 246 PMU_EVENT_GROUP(events, cstate_pkg_c3);
 247 PMU_EVENT_GROUP(events, cstate_pkg_c6);
 248 PMU_EVENT_GROUP(events, cstate_pkg_c7);
 249 PMU_EVENT_GROUP(events, cstate_pkg_c8);
 250 PMU_EVENT_GROUP(events, cstate_pkg_c9);
 251 PMU_EVENT_GROUP(events, cstate_pkg_c10);
 252
 253 static struct perf_msr pkg_msr[] = {
 254         [PERF_CSTATE_PKG_C2_RES]  = { MSR_PKG_C2_RESIDENCY,     &group_cstate_pkg_c2,   test_msr },
 255         [PERF_CSTATE_PKG_C3_RES]  = { MSR_PKG_C3_RESIDENCY,     &group_cstate_pkg_c3,   test_msr },
 256         [PERF_CSTATE_PKG_C6_RES]  = { MSR_PKG_C6_RESIDENCY,     &group_cstate_pkg_c6,   test_msr },
 257         [PERF_CSTATE_PKG_C7_RES]  = { MSR_PKG_C7_RESIDENCY,     &group_cstate_pkg_c7,   test_msr },
 258         [PERF_CSTATE_PKG_C8_RES]  = { MSR_PKG_C8_RESIDENCY,     &group_cstate_pkg_c8,   test_msr },
 259         [PERF_CSTATE_PKG_C9_RES]  = { MSR_PKG_C9_RESIDENCY,     &group_cstate_pkg_c9,   test_msr },
 260         [PERF_CSTATE_PKG_C10_RES] = { MSR_PKG_C10_RESIDENCY,    &group_cstate_pkg_c10,  test_msr },
 261 };
 262
 263 static struct attribute_group pkg_events_attr_group = {
 264         .name = "events",
 265         .attrs = attrs_empty,
 266 };
 267
 268 DEFINE_CSTATE_FORMAT_ATTR(pkg_event, event, "config:0-63");
 269 static struct attribute *pkg_format_attrs[] = {
 270         &format_attr_pkg_event.attr,
 271         NULL,
 272 };
 273 static struct attribute_group pkg_format_attr_group = {
 274         .name = "format",
 275         .attrs = pkg_format_attrs,
 276 };
 277
 278 static cpumask_t cstate_pkg_cpu_mask;
 279
 280 static const struct attribute_group *pkg_attr_groups[] = {
 281         &pkg_events_attr_group,
 282         &pkg_format_attr_group,
 283         &cpumask_attr_group,
 284         NULL,
 285 };
 286
 287 static ssize_t cstate_get_attr_cpumask(struct device *dev,
 288                                        struct device_attribute *attr,
 289                                        char *buf)
 290 {
 291         struct pmu *pmu = dev_get_drvdata(dev);
 292
 293         if (pmu == &cstate_core_pmu)
 294                 return cpumap_print_to_pagebuf(true, buf, &cstate_core_cpu_mask);
 295         else if (pmu == &cstate_pkg_pmu)
 296                 return cpumap_print_to_pagebuf(true, buf, &cstate_pkg_cpu_mask);
 297         else
 298                 return 0;
 299 }
 300
 301 static int cstate_pmu_event_init(struct perf_event *event)
 302 {
 303         u64 cfg = event->attr.config;
 304         int cpu;
 305
 306         if (event->attr.type != event->pmu->type)
 307                 return -ENOENT;
 308
 309         /* unsupported modes and filters */
 310         if (event->attr.sample_period) /* no sampling */
 311                 return -EINVAL;
 312
 313         if (event->cpu < 0)
 314                 return -EINVAL;
 315
 316         if (event->pmu == &cstate_core_pmu) {
 317                 if (cfg >= PERF_CSTATE_CORE_EVENT_MAX)
 318                         return -EINVAL;
 319                 cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_CORE_EVENT_MAX);
 320                 if (!(core_msr_mask & (1 << cfg)))
 321                         return -EINVAL;
 322                 event->hw.event_base = core_msr[cfg].msr;
 323                 cpu = cpumask_any_and(&cstate_core_cpu_mask,
 324                                       topology_sibling_cpumask(event->cpu));
 325         } else if (event->pmu == &cstate_pkg_pmu) {
 326                 if (cfg >= PERF_CSTATE_PKG_EVENT_MAX)
 327                         return -EINVAL;
 328                 cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_PKG_EVENT_MAX);
 329                 if (!(pkg_msr_mask & (1 << cfg)))
 330                         return -EINVAL;
 331                 event->hw.event_base = pkg_msr[cfg].msr;
 332                 cpu = cpumask_any_and(&cstate_pkg_cpu_mask,
 333                                       topology_die_cpumask(event->cpu));
 334         } else {
 335                 return -ENOENT;
 336         }
 337
 338         if (cpu >= nr_cpu_ids)
 339                 return -ENODEV;
 340
 341         event->cpu = cpu;
 342         event->hw.config = cfg;
 343         event->hw.idx = -1;
 344         return 0;
 345 }
 346
 347 static inline u64 cstate_pmu_read_counter(struct perf_event *event)
 348 {
 349         u64 val;
 350
 351         rdmsrl(event->hw.event_base, val);
 352         return val;
 353 }
 354
 355 static void cstate_pmu_event_update(struct perf_event *event)
 356 {
 357         struct hw_perf_event *hwc = &event->hw;
 358         u64 prev_raw_count, new_raw_count;
 359
 360 again:
 361         prev_raw_count = local64_read(&hwc->prev_count);
 362         new_raw_count = cstate_pmu_read_counter(event);
 363
 364         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 365                             new_raw_count) != prev_raw_count)
 366                 goto again;
 367
 368         local64_add(new_raw_count - prev_raw_count, &event->count);
 369 }
 370
 371 static void cstate_pmu_event_start(struct perf_event *event, int mode)
 372 {
 373         local64_set(&event->hw.prev_count, cstate_pmu_read_counter(event));
 374 }
 375
 376 static void cstate_pmu_event_stop(struct perf_event *event, int mode)
 377 {
 378         cstate_pmu_event_update(event);
 379 }
 380
 381 static void cstate_pmu_event_del(struct perf_event *event, int mode)
 382 {
 383         cstate_pmu_event_stop(event, PERF_EF_UPDATE);
 384 }
 385
 386 static int cstate_pmu_event_add(struct perf_event *event, int mode)
 387 {
 388         if (mode & PERF_EF_START)
 389                 cstate_pmu_event_start(event, mode);
 390
 391         return 0;
 392 }
 393
 394 /*
 395  * Check if exiting cpu is the designated reader. If so migrate the
 396  * events when there is a valid target available
 397  */
 398 static int cstate_cpu_exit(unsigned int cpu)
 399 {
 400         unsigned int target;
 401
 402         if (has_cstate_core &&
 403             cpumask_test_and_clear_cpu(cpu, &cstate_core_cpu_mask)) {
 404
 405                 target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
 406                 /* Migrate events if there is a valid target */
 407                 if (target < nr_cpu_ids) {
 408                         cpumask_set_cpu(target, &cstate_core_cpu_mask);
 409                         perf_pmu_migrate_context(&cstate_core_pmu, cpu, target);
 410                 }
 411         }
 412
 413         if (has_cstate_pkg &&
 414             cpumask_test_and_clear_cpu(cpu, &cstate_pkg_cpu_mask)) {
 415
 416                 target = cpumask_any_but(topology_die_cpumask(cpu), cpu);
 417                 /* Migrate events if there is a valid target */
 418                 if (target < nr_cpu_ids) {
 419                         cpumask_set_cpu(target, &cstate_pkg_cpu_mask);
 420                         perf_pmu_migrate_context(&cstate_pkg_pmu, cpu, target);
 421                 }
 422         }
 423         return 0;
 424 }
 425
 426 static int cstate_cpu_init(unsigned int cpu)
 427 {
 428         unsigned int target;
 429
 430         /*
 431          * If this is the first online thread of that core, set it in
 432          * the core cpu mask as the designated reader.
 433          */
 434         target = cpumask_any_and(&cstate_core_cpu_mask,
 435                                  topology_sibling_cpumask(cpu));
 436
 437         if (has_cstate_core && target >= nr_cpu_ids)
 438                 cpumask_set_cpu(cpu, &cstate_core_cpu_mask);
 439
 440         /*
 441          * If this is the first online thread of that package, set it
 442          * in the package cpu mask as the designated reader.
 443          */
 444         target = cpumask_any_and(&cstate_pkg_cpu_mask,
 445                                  topology_die_cpumask(cpu));
 446         if (has_cstate_pkg && target >= nr_cpu_ids)
 447                 cpumask_set_cpu(cpu, &cstate_pkg_cpu_mask);
 448
 449         return 0;
 450 }
 451
 452 static const struct attribute_group *core_attr_update[] = {
 453         &group_cstate_core_c1,
 454         &group_cstate_core_c3,
 455         &group_cstate_core_c6,
 456         &group_cstate_core_c7,
 457         NULL,
 458 };
 459
 460 static const struct attribute_group *pkg_attr_update[] = {
 461         &group_cstate_pkg_c2,
 462         &group_cstate_pkg_c3,
 463         &group_cstate_pkg_c6,
 464         &group_cstate_pkg_c7,
 465         &group_cstate_pkg_c8,
 466         &group_cstate_pkg_c9,
 467         &group_cstate_pkg_c10,
 468         NULL,
 469 };
 470
 471 static struct pmu cstate_core_pmu = {
 472         .attr_groups    = core_attr_groups,
 473         .attr_update    = core_attr_update,
 474         .name           = "cstate_core",
 475         .task_ctx_nr    = perf_invalid_context,
 476         .event_init     = cstate_pmu_event_init,
 477         .add            = cstate_pmu_event_add,
 478         .del            = cstate_pmu_event_del,
 479         .start          = cstate_pmu_event_start,
 480         .stop           = cstate_pmu_event_stop,
 481         .read           = cstate_pmu_event_update,
 482         .capabilities   = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
 483         .module         = THIS_MODULE,
 484 };
 485
 486 static struct pmu cstate_pkg_pmu = {
 487         .attr_groups    = pkg_attr_groups,
 488         .attr_update    = pkg_attr_update,
 489         .name           = "cstate_pkg",
 490         .task_ctx_nr    = perf_invalid_context,
 491         .event_init     = cstate_pmu_event_init,
 492         .add            = cstate_pmu_event_add,
 493         .del            = cstate_pmu_event_del,
 494         .start          = cstate_pmu_event_start,
 495         .stop           = cstate_pmu_event_stop,
 496         .read           = cstate_pmu_event_update,
 497         .capabilities   = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
 498         .module         = THIS_MODULE,
 499 };
 500
 501 static const struct cstate_model nhm_cstates __initconst = {
 502         .core_events            = BIT(PERF_CSTATE_CORE_C3_RES) |
 503                                   BIT(PERF_CSTATE_CORE_C6_RES),
 504
 505         .pkg_events             = BIT(PERF_CSTATE_PKG_C3_RES) |
 506                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 507                                   BIT(PERF_CSTATE_PKG_C7_RES),
 508 };
 509
 510 static const struct cstate_model snb_cstates __initconst = {
 511         .core_events            = BIT(PERF_CSTATE_CORE_C3_RES) |
 512                                   BIT(PERF_CSTATE_CORE_C6_RES) |
 513                                   BIT(PERF_CSTATE_CORE_C7_RES),
 514
 515         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 516                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 517                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 518                                   BIT(PERF_CSTATE_PKG_C7_RES),
 519 };
 520
 521 static const struct cstate_model hswult_cstates __initconst = {
 522         .core_events            = BIT(PERF_CSTATE_CORE_C3_RES) |
 523                                   BIT(PERF_CSTATE_CORE_C6_RES) |
 524                                   BIT(PERF_CSTATE_CORE_C7_RES),
 525
 526         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 527                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 528                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 529                                   BIT(PERF_CSTATE_PKG_C7_RES) |
 530                                   BIT(PERF_CSTATE_PKG_C8_RES) |
 531                                   BIT(PERF_CSTATE_PKG_C9_RES) |
 532                                   BIT(PERF_CSTATE_PKG_C10_RES),
 533 };
 534
 535 static const struct cstate_model cnl_cstates __initconst = {
 536         .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
 537                                   BIT(PERF_CSTATE_CORE_C3_RES) |
 538                                   BIT(PERF_CSTATE_CORE_C6_RES) |
 539                                   BIT(PERF_CSTATE_CORE_C7_RES),
 540
 541         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 542                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 543                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 544                                   BIT(PERF_CSTATE_PKG_C7_RES) |
 545                                   BIT(PERF_CSTATE_PKG_C8_RES) |
 546                                   BIT(PERF_CSTATE_PKG_C9_RES) |
 547                                   BIT(PERF_CSTATE_PKG_C10_RES),
 548 };
 549
 550 static const struct cstate_model icl_cstates __initconst = {
 551         .core_events            = BIT(PERF_CSTATE_CORE_C6_RES) |
 552                                   BIT(PERF_CSTATE_CORE_C7_RES),
 553
 554         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 555                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 556                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 557                                   BIT(PERF_CSTATE_PKG_C7_RES) |
 558                                   BIT(PERF_CSTATE_PKG_C8_RES) |
 559                                   BIT(PERF_CSTATE_PKG_C9_RES) |
 560                                   BIT(PERF_CSTATE_PKG_C10_RES),
 561 };
 562
 563 static const struct cstate_model slm_cstates __initconst = {
 564         .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
 565                                   BIT(PERF_CSTATE_CORE_C6_RES),
 566
 567         .pkg_events             = BIT(PERF_CSTATE_PKG_C6_RES),
 568         .quirks                 = SLM_PKG_C6_USE_C7_MSR,
 569 };
 570
 571
 572 static const struct cstate_model knl_cstates __initconst = {
 573         .core_events            = BIT(PERF_CSTATE_CORE_C6_RES),
 574
 575         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 576                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 577                                   BIT(PERF_CSTATE_PKG_C6_RES),
 578         .quirks                 = KNL_CORE_C6_MSR,
 579 };
 580
 581
 582 static const struct cstate_model glm_cstates __initconst = {
 583         .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
 584                                   BIT(PERF_CSTATE_CORE_C3_RES) |
 585                                   BIT(PERF_CSTATE_CORE_C6_RES),
 586
 587         .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
 588                                   BIT(PERF_CSTATE_PKG_C3_RES) |
 589                                   BIT(PERF_CSTATE_PKG_C6_RES) |
 590                                   BIT(PERF_CSTATE_PKG_C10_RES),
 591 };
 592
 593
 594 #define X86_CSTATES_MODEL(model, states)                                \
 595         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long) &(states) }
 596
 597 static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 598         X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM,    nhm_cstates),
 599         X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM_EP, nhm_cstates),
 600         X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM_EX, nhm_cstates),
 601
 602         X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE,    nhm_cstates),
 603         X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE_EP, nhm_cstates),
 604         X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE_EX, nhm_cstates),
 605
 606         X86_CSTATES_MODEL(INTEL_FAM6_SANDYBRIDGE,   snb_cstates),
 607         X86_CSTATES_MODEL(INTEL_FAM6_SANDYBRIDGE_X, snb_cstates),
 608
 609         X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE,   snb_cstates),
 610         X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE_X, snb_cstates),
 611
 612         X86_CSTATES_MODEL(INTEL_FAM6_HASWELL,   snb_cstates),
 613         X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_X, snb_cstates),
 614         X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_G, snb_cstates),
 615
 616         X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_L, hswult_cstates),
 617
 618         X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT,   slm_cstates),
 619         X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT_D, slm_cstates),
 620         X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT,      slm_cstates),
 621
 622         X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL,   snb_cstates),
 623         X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_D, snb_cstates),
 624         X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_G, snb_cstates),
 625         X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_X, snb_cstates),
 626
 627         X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_L, snb_cstates),
 628         X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE,   snb_cstates),
 629         X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_X, snb_cstates),
 630
 631         X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_L, hswult_cstates),
 632         X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE,   hswult_cstates),
 633         X86_CSTATES_MODEL(INTEL_FAM6_COMETLAKE_L, hswult_cstates),
 634         X86_CSTATES_MODEL(INTEL_FAM6_COMETLAKE, hswult_cstates),
 635
 636         X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_L, cnl_cstates),
 637
 638         X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
 639         X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
 640
 641         X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT,   glm_cstates),
 642         X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_D, glm_cstates),
 643
 644         X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),
 645
 646         X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates),
 647         X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE,   icl_cstates),
 648         X86_CSTATES_MODEL(INTEL_FAM6_TIGERLAKE_L, icl_cstates),
 649         X86_CSTATES_MODEL(INTEL_FAM6_TIGERLAKE, icl_cstates),
 650         { },
 651 };
 652 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
 653
 654 static int __init cstate_probe(const struct cstate_model *cm)
 655 {
 656         /* SLM has different MSR for PKG C6 */
 657         if (cm->quirks & SLM_PKG_C6_USE_C7_MSR)
 658                 pkg_msr[PERF_CSTATE_PKG_C6_RES].msr = MSR_PKG_C7_RESIDENCY;
 659
 660         /* KNL has different MSR for CORE C6 */
 661         if (cm->quirks & KNL_CORE_C6_MSR)
 662                 pkg_msr[PERF_CSTATE_CORE_C6_RES].msr = MSR_KNL_CORE_C6_RESIDENCY;
 663
 664
 665         core_msr_mask = perf_msr_probe(core_msr, PERF_CSTATE_CORE_EVENT_MAX,
 666                                        true, (void *) &cm->core_events);
 667
 668         pkg_msr_mask = perf_msr_probe(pkg_msr, PERF_CSTATE_PKG_EVENT_MAX,
 669                                       true, (void *) &cm->pkg_events);
 670
 671         has_cstate_core = !!core_msr_mask;
 672         has_cstate_pkg  = !!pkg_msr_mask;
 673
 674         return (has_cstate_core || has_cstate_pkg) ? 0 : -ENODEV;
 675 }
 676
 677 static inline void cstate_cleanup(void)
 678 {
 679         cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_ONLINE);
 680         cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_STARTING);
 681
 682         if (has_cstate_core)
 683                 perf_pmu_unregister(&cstate_core_pmu);
 684
 685         if (has_cstate_pkg)
 686                 perf_pmu_unregister(&cstate_pkg_pmu);
 687 }
 688
 689 static int __init cstate_init(void)
 690 {
 691         int err;
 692
 693         cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_STARTING,
 694                           "perf/x86/cstate:starting", cstate_cpu_init, NULL);
 695         cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_ONLINE,
 696                           "perf/x86/cstate:online", NULL, cstate_cpu_exit);
 697
 698         if (has_cstate_core) {
 699                 err = perf_pmu_register(&cstate_core_pmu, cstate_core_pmu.name, -1);
 700                 if (err) {
 701                         has_cstate_core = false;
 702                         pr_info("Failed to register cstate core pmu\n");
 703                         cstate_cleanup();
 704                         return err;
 705                 }
 706         }
 707
 708         if (has_cstate_pkg) {
 709                 if (topology_max_die_per_package() > 1) {
 710                         err = perf_pmu_register(&cstate_pkg_pmu,
 711                                                 "cstate_die", -1);
 712                 } else {
 713                         err = perf_pmu_register(&cstate_pkg_pmu,
 714                                                 cstate_pkg_pmu.name, -1);
 715                 }
 716                 if (err) {
 717                         has_cstate_pkg = false;
 718                         pr_info("Failed to register cstate pkg pmu\n");
 719                         cstate_cleanup();
 720                         return err;
 721                 }
 722         }
 723         return 0;
 724 }
 725
 726 static int __init cstate_pmu_init(void)
 727 {
 728         const struct x86_cpu_id *id;
 729         int err;
 730
 731         if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 732                 return -ENODEV;
 733
 734         id = x86_match_cpu(intel_cstates_match);
 735         if (!id)
 736                 return -ENODEV;
 737
 738         err = cstate_probe((const struct cstate_model *) id->driver_data);
 739         if (err)
 740                 return err;
 741
 742         return cstate_init();
 743 }
 744 module_init(cstate_pmu_init);
 745
 746 static void __exit cstate_pmu_exit(void)
 747 {
 748         cstate_cleanup();
 749 }
 750 module_exit(cstate_pmu_exit);