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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / ata / pata_arasan_cf.c
blob391dff0f25a2ba61943ddd63b26c11b4c27cc9e7
1 /*
2 * drivers/ata/pata_arasan_cf.c
3 *
4 * Arasan Compact Flash host controller source file
5 *
6 * Copyright (C) 2011 ST Microelectronics
7 * Viresh Kumar <vireshk@kernel.org>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 /*
15 * The Arasan CompactFlash Device Controller IP core has three basic modes of
16 * operation: PC card ATA using I/O mode, PC card ATA using memory mode, PC card
17 * ATA using true IDE modes. This driver supports only True IDE mode currently.
18 *
19 * Arasan CF Controller shares global irq register with Arasan XD Controller.
20 *
21 * Tested on arch/arm/mach-spear13xx
22 */
23
24 #include <linux/ata.h>
25 #include <linux/clk.h>
26 #include <linux/completion.h>
27 #include <linux/delay.h>
28 #include <linux/dmaengine.h>
29 #include <linux/io.h>
30 #include <linux/irq.h>
31 #include <linux/kernel.h>
32 #include <linux/libata.h>
33 #include <linux/module.h>
34 #include <linux/of.h>
35 #include <linux/pata_arasan_cf_data.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm.h>
38 #include <linux/slab.h>
39 #include <linux/spinlock.h>
40 #include <linux/types.h>
41 #include <linux/workqueue.h>
42
43 #define DRIVER_NAME "arasan_cf"
44 #define TIMEOUT msecs_to_jiffies(3000)
45
46 /* Registers */
47 /* CompactFlash Interface Status */
48 #define CFI_STS 0x000
49 #define STS_CHG (1)
50 #define BIN_AUDIO_OUT (1 << 1)
51 #define CARD_DETECT1 (1 << 2)
52 #define CARD_DETECT2 (1 << 3)
53 #define INP_ACK (1 << 4)
54 #define CARD_READY (1 << 5)
55 #define IO_READY (1 << 6)
56 #define B16_IO_PORT_SEL (1 << 7)
57 /* IRQ */
58 #define IRQ_STS 0x004
59 /* Interrupt Enable */
60 #define IRQ_EN 0x008
61 #define CARD_DETECT_IRQ (1)
62 #define STATUS_CHNG_IRQ (1 << 1)
63 #define MEM_MODE_IRQ (1 << 2)
64 #define IO_MODE_IRQ (1 << 3)
65 #define TRUE_IDE_MODE_IRQ (1 << 8)
66 #define PIO_XFER_ERR_IRQ (1 << 9)
67 #define BUF_AVAIL_IRQ (1 << 10)
68 #define XFER_DONE_IRQ (1 << 11)
69 #define IGNORED_IRQS (STATUS_CHNG_IRQ | MEM_MODE_IRQ | IO_MODE_IRQ |\
70 TRUE_IDE_MODE_IRQ)
71 #define TRUE_IDE_IRQS (CARD_DETECT_IRQ | PIO_XFER_ERR_IRQ |\
72 BUF_AVAIL_IRQ | XFER_DONE_IRQ)
73 /* Operation Mode */
74 #define OP_MODE 0x00C
75 #define CARD_MODE_MASK (0x3)
76 #define MEM_MODE (0x0)
77 #define IO_MODE (0x1)
78 #define TRUE_IDE_MODE (0x2)
79
80 #define CARD_TYPE_MASK (1 << 2)
81 #define CF_CARD (0)
82 #define CF_PLUS_CARD (1 << 2)
83
84 #define CARD_RESET (1 << 3)
85 #define CFHOST_ENB (1 << 4)
86 #define OUTPUTS_TRISTATE (1 << 5)
87 #define ULTRA_DMA_ENB (1 << 8)
88 #define MULTI_WORD_DMA_ENB (1 << 9)
89 #define DRQ_BLOCK_SIZE_MASK (0x3 << 11)
90 #define DRQ_BLOCK_SIZE_512 (0)
91 #define DRQ_BLOCK_SIZE_1024 (1 << 11)
92 #define DRQ_BLOCK_SIZE_2048 (2 << 11)
93 #define DRQ_BLOCK_SIZE_4096 (3 << 11)
94 /* CF Interface Clock Configuration */
95 #define CLK_CFG 0x010
96 #define CF_IF_CLK_MASK (0XF)
97 /* CF Timing Mode Configuration */
98 #define TM_CFG 0x014
99 #define MEM_MODE_TIMING_MASK (0x3)
100 #define MEM_MODE_TIMING_250NS (0x0)
101 #define MEM_MODE_TIMING_120NS (0x1)
102 #define MEM_MODE_TIMING_100NS (0x2)
103 #define MEM_MODE_TIMING_80NS (0x3)
104
105 #define IO_MODE_TIMING_MASK (0x3 << 2)
106 #define IO_MODE_TIMING_250NS (0x0 << 2)
107 #define IO_MODE_TIMING_120NS (0x1 << 2)
108 #define IO_MODE_TIMING_100NS (0x2 << 2)
109 #define IO_MODE_TIMING_80NS (0x3 << 2)
110
111 #define TRUEIDE_PIO_TIMING_MASK (0x7 << 4)
112 #define TRUEIDE_PIO_TIMING_SHIFT 4
113
114 #define TRUEIDE_MWORD_DMA_TIMING_MASK (0x7 << 7)
115 #define TRUEIDE_MWORD_DMA_TIMING_SHIFT 7
116
117 #define ULTRA_DMA_TIMING_MASK (0x7 << 10)
118 #define ULTRA_DMA_TIMING_SHIFT 10
119 /* CF Transfer Address */
120 #define XFER_ADDR 0x014
121 #define XFER_ADDR_MASK (0x7FF)
122 #define MAX_XFER_COUNT 0x20000u
123 /* Transfer Control */
124 #define XFER_CTR 0x01C
125 #define XFER_COUNT_MASK (0x3FFFF)
126 #define ADDR_INC_DISABLE (1 << 24)
127 #define XFER_WIDTH_MASK (1 << 25)
128 #define XFER_WIDTH_8B (0)
129 #define XFER_WIDTH_16B (1 << 25)
130
131 #define MEM_TYPE_MASK (1 << 26)
132 #define MEM_TYPE_COMMON (0)
133 #define MEM_TYPE_ATTRIBUTE (1 << 26)
134
135 #define MEM_IO_XFER_MASK (1 << 27)
136 #define MEM_XFER (0)
137 #define IO_XFER (1 << 27)
138
139 #define DMA_XFER_MODE (1 << 28)
140
141 #define AHB_BUS_NORMAL_PIO_OPRTN (~(1 << 29))
142 #define XFER_DIR_MASK (1 << 30)
143 #define XFER_READ (0)
144 #define XFER_WRITE (1 << 30)
145
146 #define XFER_START (1 << 31)
147 /* Write Data Port */
148 #define WRITE_PORT 0x024
149 /* Read Data Port */
150 #define READ_PORT 0x028
151 /* ATA Data Port */
152 #define ATA_DATA_PORT 0x030
153 #define ATA_DATA_PORT_MASK (0xFFFF)
154 /* ATA Error/Features */
155 #define ATA_ERR_FTR 0x034
156 /* ATA Sector Count */
157 #define ATA_SC 0x038
158 /* ATA Sector Number */
159 #define ATA_SN 0x03C
160 /* ATA Cylinder Low */
161 #define ATA_CL 0x040
162 /* ATA Cylinder High */
163 #define ATA_CH 0x044
164 /* ATA Select Card/Head */
165 #define ATA_SH 0x048
166 /* ATA Status-Command */
167 #define ATA_STS_CMD 0x04C
168 /* ATA Alternate Status/Device Control */
169 #define ATA_ASTS_DCTR 0x050
170 /* Extended Write Data Port 0x200-0x3FC */
171 #define EXT_WRITE_PORT 0x200
172 /* Extended Read Data Port 0x400-0x5FC */
173 #define EXT_READ_PORT 0x400
174 #define FIFO_SIZE 0x200u
175 /* Global Interrupt Status */
176 #define GIRQ_STS 0x800
177 /* Global Interrupt Status enable */
178 #define GIRQ_STS_EN 0x804
179 /* Global Interrupt Signal enable */
180 #define GIRQ_SGN_EN 0x808
181 #define GIRQ_CF (1)
182 #define GIRQ_XD (1 << 1)
183
184 /* Compact Flash Controller Dev Structure */
185 struct arasan_cf_dev {
186 /* pointer to ata_host structure */
187 struct ata_host *host;
188 /* clk structure */
189 struct clk *clk;
190
191 /* physical base address of controller */
192 dma_addr_t pbase;
193 /* virtual base address of controller */
194 void __iomem *vbase;
195 /* irq number*/
196 int irq;
197
198 /* status to be updated to framework regarding DMA transfer */
199 u8 dma_status;
200 /* Card is present or Not */
201 u8 card_present;
202
203 /* dma specific */
204 /* Completion for transfer complete interrupt from controller */
205 struct completion cf_completion;
206 /* Completion for DMA transfer complete. */
207 struct completion dma_completion;
208 /* Dma channel allocated */
209 struct dma_chan *dma_chan;
210 /* Mask for DMA transfers */
211 dma_cap_mask_t mask;
212 /* DMA transfer work */
213 struct work_struct work;
214 /* DMA delayed finish work */
215 struct delayed_work dwork;
216 /* qc to be transferred using DMA */
217 struct ata_queued_cmd *qc;
218 };
219
220 static struct scsi_host_template arasan_cf_sht = {
221 ATA_BASE_SHT(DRIVER_NAME),
222 .dma_boundary = 0xFFFFFFFFUL,
223 };
224
225 static void cf_dumpregs(struct arasan_cf_dev *acdev)
226 {
227 struct device *dev = acdev->host->dev;
228
229 dev_dbg(dev, ": =========== REGISTER DUMP ===========");
230 dev_dbg(dev, ": CFI_STS: %x", readl(acdev->vbase + CFI_STS));
231 dev_dbg(dev, ": IRQ_STS: %x", readl(acdev->vbase + IRQ_STS));
232 dev_dbg(dev, ": IRQ_EN: %x", readl(acdev->vbase + IRQ_EN));
233 dev_dbg(dev, ": OP_MODE: %x", readl(acdev->vbase + OP_MODE));
234 dev_dbg(dev, ": CLK_CFG: %x", readl(acdev->vbase + CLK_CFG));
235 dev_dbg(dev, ": TM_CFG: %x", readl(acdev->vbase + TM_CFG));
236 dev_dbg(dev, ": XFER_CTR: %x", readl(acdev->vbase + XFER_CTR));
237 dev_dbg(dev, ": GIRQ_STS: %x", readl(acdev->vbase + GIRQ_STS));
238 dev_dbg(dev, ": GIRQ_STS_EN: %x", readl(acdev->vbase + GIRQ_STS_EN));
239 dev_dbg(dev, ": GIRQ_SGN_EN: %x", readl(acdev->vbase + GIRQ_SGN_EN));
240 dev_dbg(dev, ": =====================================");
241 }
242
243 /* Enable/Disable global interrupts shared between CF and XD ctrlr. */
244 static void cf_ginterrupt_enable(struct arasan_cf_dev *acdev, bool enable)
245 {
246 /* enable should be 0 or 1 */
247 writel(enable, acdev->vbase + GIRQ_STS_EN);
248 writel(enable, acdev->vbase + GIRQ_SGN_EN);
249 }
250
251 /* Enable/Disable CF interrupts */
252 static inline void
253 cf_interrupt_enable(struct arasan_cf_dev *acdev, u32 mask, bool enable)
254 {
255 u32 val = readl(acdev->vbase + IRQ_EN);
256 /* clear & enable/disable irqs */
257 if (enable) {
258 writel(mask, acdev->vbase + IRQ_STS);
259 writel(val | mask, acdev->vbase + IRQ_EN);
260 } else
261 writel(val & ~mask, acdev->vbase + IRQ_EN);
262 }
263
264 static inline void cf_card_reset(struct arasan_cf_dev *acdev)
265 {
266 u32 val = readl(acdev->vbase + OP_MODE);
267
268 writel(val | CARD_RESET, acdev->vbase + OP_MODE);
269 udelay(200);
270 writel(val & ~CARD_RESET, acdev->vbase + OP_MODE);
271 }
272
273 static inline void cf_ctrl_reset(struct arasan_cf_dev *acdev)
274 {
275 writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
276 acdev->vbase + OP_MODE);
277 writel(readl(acdev->vbase + OP_MODE) | CFHOST_ENB,
278 acdev->vbase + OP_MODE);
279 }
280
281 static void cf_card_detect(struct arasan_cf_dev *acdev, bool hotplugged)
282 {
283 struct ata_port *ap = acdev->host->ports[0];
284 struct ata_eh_info *ehi = &ap->link.eh_info;
285 u32 val = readl(acdev->vbase + CFI_STS);
286
287 /* Both CD1 & CD2 should be low if card inserted completely */
288 if (!(val & (CARD_DETECT1 | CARD_DETECT2))) {
289 if (acdev->card_present)
290 return;
291 acdev->card_present = 1;
292 cf_card_reset(acdev);
293 } else {
294 if (!acdev->card_present)
295 return;
296 acdev->card_present = 0;
297 }
298
299 if (hotplugged) {
300 ata_ehi_hotplugged(ehi);
301 ata_port_freeze(ap);
302 }
303 }
304
305 static int cf_init(struct arasan_cf_dev *acdev)
306 {
307 struct arasan_cf_pdata *pdata = dev_get_platdata(acdev->host->dev);
308 unsigned int if_clk;
309 unsigned long flags;
310 int ret = 0;
311
312 ret = clk_prepare_enable(acdev->clk);
313 if (ret) {
314 dev_dbg(acdev->host->dev, "clock enable failed");
315 return ret;
316 }
317
318 ret = clk_set_rate(acdev->clk, 166000000);
319 if (ret) {
320 dev_warn(acdev->host->dev, "clock set rate failed");
321 clk_disable_unprepare(acdev->clk);
322 return ret;
323 }
324
325 spin_lock_irqsave(&acdev->host->lock, flags);
326 /* configure CF interface clock */
327 /* TODO: read from device tree */
328 if_clk = CF_IF_CLK_166M;
329 if (pdata && pdata->cf_if_clk <= CF_IF_CLK_200M)
330 if_clk = pdata->cf_if_clk;
331
332 writel(if_clk, acdev->vbase + CLK_CFG);
333
334 writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE);
335 cf_interrupt_enable(acdev, CARD_DETECT_IRQ, 1);
336 cf_ginterrupt_enable(acdev, 1);
337 spin_unlock_irqrestore(&acdev->host->lock, flags);
338
339 return ret;
340 }
341
342 static void cf_exit(struct arasan_cf_dev *acdev)
343 {
344 unsigned long flags;
345
346 spin_lock_irqsave(&acdev->host->lock, flags);
347 cf_ginterrupt_enable(acdev, 0);
348 cf_interrupt_enable(acdev, TRUE_IDE_IRQS, 0);
349 cf_card_reset(acdev);
350 writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
351 acdev->vbase + OP_MODE);
352 spin_unlock_irqrestore(&acdev->host->lock, flags);
353 clk_disable_unprepare(acdev->clk);
354 }
355
356 static void dma_callback(void *dev)
357 {
358 struct arasan_cf_dev *acdev = dev;
359
360 complete(&acdev->dma_completion);
361 }
362
363 static inline void dma_complete(struct arasan_cf_dev *acdev)
364 {
365 struct ata_queued_cmd *qc = acdev->qc;
366 unsigned long flags;
367
368 acdev->qc = NULL;
369 ata_sff_interrupt(acdev->irq, acdev->host);
370
371 spin_lock_irqsave(&acdev->host->lock, flags);
372 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
373 ata_ehi_push_desc(&qc->ap->link.eh_info, "DMA Failed: Timeout");
374 spin_unlock_irqrestore(&acdev->host->lock, flags);
375 }
376
377 static inline int wait4buf(struct arasan_cf_dev *acdev)
378 {
379 if (!wait_for_completion_timeout(&acdev->cf_completion, TIMEOUT)) {
380 u32 rw = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
381
382 dev_err(acdev->host->dev, "%s TimeOut", rw ? "write" : "read");
383 return -ETIMEDOUT;
384 }
385
386 /* Check if PIO Error interrupt has occurred */
387 if (acdev->dma_status & ATA_DMA_ERR)
388 return -EAGAIN;
389
390 return 0;
391 }
392
393 static int
394 dma_xfer(struct arasan_cf_dev *acdev, dma_addr_t src, dma_addr_t dest, u32 len)
395 {
396 struct dma_async_tx_descriptor *tx;
397 struct dma_chan *chan = acdev->dma_chan;
398 dma_cookie_t cookie;
399 unsigned long flags = DMA_PREP_INTERRUPT;
400 int ret = 0;
401
402 tx = chan->device->device_prep_dma_memcpy(chan, dest, src, len, flags);
403 if (!tx) {
404 dev_err(acdev->host->dev, "device_prep_dma_memcpy failed\n");
405 return -EAGAIN;
406 }
407
408 tx->callback = dma_callback;
409 tx->callback_param = acdev;
410 cookie = tx->tx_submit(tx);
411
412 ret = dma_submit_error(cookie);
413 if (ret) {
414 dev_err(acdev->host->dev, "dma_submit_error\n");
415 return ret;
416 }
417
418 chan->device->device_issue_pending(chan);
419
420 /* Wait for DMA to complete */
421 if (!wait_for_completion_timeout(&acdev->dma_completion, TIMEOUT)) {
422 dmaengine_terminate_all(chan);
423 dev_err(acdev->host->dev, "wait_for_completion_timeout\n");
424 return -ETIMEDOUT;
425 }
426
427 return ret;
428 }
429
430 static int sg_xfer(struct arasan_cf_dev *acdev, struct scatterlist *sg)
431 {
432 dma_addr_t dest = 0, src = 0;
433 u32 xfer_cnt, sglen, dma_len, xfer_ctr;
434 u32 write = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
435 unsigned long flags;
436 int ret = 0;
437
438 sglen = sg_dma_len(sg);
439 if (write) {
440 src = sg_dma_address(sg);
441 dest = acdev->pbase + EXT_WRITE_PORT;
442 } else {
443 dest = sg_dma_address(sg);
444 src = acdev->pbase + EXT_READ_PORT;
445 }
446
447 /*
448 * For each sg:
449 * MAX_XFER_COUNT data will be transferred before we get transfer
450 * complete interrupt. Between after FIFO_SIZE data
451 * buffer available interrupt will be generated. At this time we will
452 * fill FIFO again: max FIFO_SIZE data.
453 */
454 while (sglen) {
455 xfer_cnt = min(sglen, MAX_XFER_COUNT);
456 spin_lock_irqsave(&acdev->host->lock, flags);
457 xfer_ctr = readl(acdev->vbase + XFER_CTR) &
458 ~XFER_COUNT_MASK;
459 writel(xfer_ctr | xfer_cnt | XFER_START,
460 acdev->vbase + XFER_CTR);
461 spin_unlock_irqrestore(&acdev->host->lock, flags);
462
463 /* continue dma xfers until current sg is completed */
464 while (xfer_cnt) {
465 /* wait for read to complete */
466 if (!write) {
467 ret = wait4buf(acdev);
468 if (ret)
469 goto fail;
470 }
471
472 /* read/write FIFO in chunk of FIFO_SIZE */
473 dma_len = min(xfer_cnt, FIFO_SIZE);
474 ret = dma_xfer(acdev, src, dest, dma_len);
475 if (ret) {
476 dev_err(acdev->host->dev, "dma failed");
477 goto fail;
478 }
479
480 if (write)
481 src += dma_len;
482 else
483 dest += dma_len;
484
485 sglen -= dma_len;
486 xfer_cnt -= dma_len;
487
488 /* wait for write to complete */
489 if (write) {
490 ret = wait4buf(acdev);
491 if (ret)
492 goto fail;
493 }
494 }
495 }
496
497 fail:
498 spin_lock_irqsave(&acdev->host->lock, flags);
499 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
500 acdev->vbase + XFER_CTR);
501 spin_unlock_irqrestore(&acdev->host->lock, flags);
502
503 return ret;
504 }
505
506 /*
507 * This routine uses External DMA controller to read/write data to FIFO of CF
508 * controller. There are two xfer related interrupt supported by CF controller:
509 * - buf_avail: This interrupt is generated as soon as we have buffer of 512
510 * bytes available for reading or empty buffer available for writing.
511 * - xfer_done: This interrupt is generated on transfer of "xfer_size" amount of
512 * data to/from FIFO. xfer_size is programmed in XFER_CTR register.
513 *
514 * Max buffer size = FIFO_SIZE = 512 Bytes.
515 * Max xfer_size = MAX_XFER_COUNT = 256 KB.
516 */
517 static void data_xfer(struct work_struct *work)
518 {
519 struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev,
520 work);
521 struct ata_queued_cmd *qc = acdev->qc;
522 struct scatterlist *sg;
523 unsigned long flags;
524 u32 temp;
525 int ret = 0;
526
527 /* request dma channels */
528 /* dma_request_channel may sleep, so calling from process context */
529 acdev->dma_chan = dma_request_slave_channel(acdev->host->dev, "data");
530 if (!acdev->dma_chan) {
531 dev_err(acdev->host->dev, "Unable to get dma_chan\n");
532 goto chan_request_fail;
533 }
534
535 for_each_sg(qc->sg, sg, qc->n_elem, temp) {
536 ret = sg_xfer(acdev, sg);
537 if (ret)
538 break;
539 }
540
541 dma_release_channel(acdev->dma_chan);
542
543 /* data xferred successfully */
544 if (!ret) {
545 u32 status;
546
547 spin_lock_irqsave(&acdev->host->lock, flags);
548 status = ioread8(qc->ap->ioaddr.altstatus_addr);
549 spin_unlock_irqrestore(&acdev->host->lock, flags);
550 if (status & (ATA_BUSY | ATA_DRQ)) {
551 ata_sff_queue_delayed_work(&acdev->dwork, 1);
552 return;
553 }
554
555 goto sff_intr;
556 }
557
558 cf_dumpregs(acdev);
559
560 chan_request_fail:
561 spin_lock_irqsave(&acdev->host->lock, flags);
562 /* error when transferring data to/from memory */
563 qc->err_mask |= AC_ERR_HOST_BUS;
564 qc->ap->hsm_task_state = HSM_ST_ERR;
565
566 cf_ctrl_reset(acdev);
567 spin_unlock_irqrestore(&acdev->host->lock, flags);
568 sff_intr:
569 dma_complete(acdev);
570 }
571
572 static void delayed_finish(struct work_struct *work)
573 {
574 struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev,
575 dwork.work);
576 struct ata_queued_cmd *qc = acdev->qc;
577 unsigned long flags;
578 u8 status;
579
580 spin_lock_irqsave(&acdev->host->lock, flags);
581 status = ioread8(qc->ap->ioaddr.altstatus_addr);
582 spin_unlock_irqrestore(&acdev->host->lock, flags);
583
584 if (status & (ATA_BUSY | ATA_DRQ))
585 ata_sff_queue_delayed_work(&acdev->dwork, 1);
586 else
587 dma_complete(acdev);
588 }
589
590 static irqreturn_t arasan_cf_interrupt(int irq, void *dev)
591 {
592 struct arasan_cf_dev *acdev = ((struct ata_host *)dev)->private_data;
593 unsigned long flags;
594 u32 irqsts;
595
596 irqsts = readl(acdev->vbase + GIRQ_STS);
597 if (!(irqsts & GIRQ_CF))
598 return IRQ_NONE;
599
600 spin_lock_irqsave(&acdev->host->lock, flags);
601 irqsts = readl(acdev->vbase + IRQ_STS);
602 writel(irqsts, acdev->vbase + IRQ_STS); /* clear irqs */
603 writel(GIRQ_CF, acdev->vbase + GIRQ_STS); /* clear girqs */
604
605 /* handle only relevant interrupts */
606 irqsts &= ~IGNORED_IRQS;
607
608 if (irqsts & CARD_DETECT_IRQ) {
609 cf_card_detect(acdev, 1);
610 spin_unlock_irqrestore(&acdev->host->lock, flags);
611 return IRQ_HANDLED;
612 }
613
614 if (irqsts & PIO_XFER_ERR_IRQ) {
615 acdev->dma_status = ATA_DMA_ERR;
616 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
617 acdev->vbase + XFER_CTR);
618 spin_unlock_irqrestore(&acdev->host->lock, flags);
619 complete(&acdev->cf_completion);
620 dev_err(acdev->host->dev, "pio xfer err irq\n");
621 return IRQ_HANDLED;
622 }
623
624 spin_unlock_irqrestore(&acdev->host->lock, flags);
625
626 if (irqsts & BUF_AVAIL_IRQ) {
627 complete(&acdev->cf_completion);
628 return IRQ_HANDLED;
629 }
630
631 if (irqsts & XFER_DONE_IRQ) {
632 struct ata_queued_cmd *qc = acdev->qc;
633
634 /* Send Complete only for write */
635 if (qc->tf.flags & ATA_TFLAG_WRITE)
636 complete(&acdev->cf_completion);
637 }
638
639 return IRQ_HANDLED;
640 }
641
642 static void arasan_cf_freeze(struct ata_port *ap)
643 {
644 struct arasan_cf_dev *acdev = ap->host->private_data;
645
646 /* stop transfer and reset controller */
647 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
648 acdev->vbase + XFER_CTR);
649 cf_ctrl_reset(acdev);
650 acdev->dma_status = ATA_DMA_ERR;
651
652 ata_sff_dma_pause(ap);
653 ata_sff_freeze(ap);
654 }
655
656 static void arasan_cf_error_handler(struct ata_port *ap)
657 {
658 struct arasan_cf_dev *acdev = ap->host->private_data;
659
660 /*
661 * DMA transfers using an external DMA controller may be scheduled.
662 * Abort them before handling error. Refer data_xfer() for further
663 * details.
664 */
665 cancel_work_sync(&acdev->work);
666 cancel_delayed_work_sync(&acdev->dwork);
667 return ata_sff_error_handler(ap);
668 }
669
670 static void arasan_cf_dma_start(struct arasan_cf_dev *acdev)
671 {
672 struct ata_queued_cmd *qc = acdev->qc;
673 struct ata_port *ap = qc->ap;
674 struct ata_taskfile *tf = &qc->tf;
675 u32 xfer_ctr = readl(acdev->vbase + XFER_CTR) & ~XFER_DIR_MASK;
676 u32 write = tf->flags & ATA_TFLAG_WRITE;
677
678 xfer_ctr |= write ? XFER_WRITE : XFER_READ;
679 writel(xfer_ctr, acdev->vbase + XFER_CTR);
680
681 ap->ops->sff_exec_command(ap, tf);
682 ata_sff_queue_work(&acdev->work);
683 }
684
685 static unsigned int arasan_cf_qc_issue(struct ata_queued_cmd *qc)
686 {
687 struct ata_port *ap = qc->ap;
688 struct arasan_cf_dev *acdev = ap->host->private_data;
689
690 /* defer PIO handling to sff_qc_issue */
691 if (!ata_is_dma(qc->tf.protocol))
692 return ata_sff_qc_issue(qc);
693
694 /* select the device */
695 ata_wait_idle(ap);
696 ata_sff_dev_select(ap, qc->dev->devno);
697 ata_wait_idle(ap);
698
699 /* start the command */
700 switch (qc->tf.protocol) {
701 case ATA_PROT_DMA:
702 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
703
704 ap->ops->sff_tf_load(ap, &qc->tf);
705 acdev->dma_status = 0;
706 acdev->qc = qc;
707 arasan_cf_dma_start(acdev);
708 ap->hsm_task_state = HSM_ST_LAST;
709 break;
710
711 default:
712 WARN_ON(1);
713 return AC_ERR_SYSTEM;
714 }
715
716 return 0;
717 }
718
719 static void arasan_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
720 {
721 struct arasan_cf_dev *acdev = ap->host->private_data;
722 u8 pio = adev->pio_mode - XFER_PIO_0;
723 unsigned long flags;
724 u32 val;
725
726 /* Arasan ctrl supports Mode0 -> Mode6 */
727 if (pio > 6) {
728 dev_err(ap->dev, "Unknown PIO mode\n");
729 return;
730 }
731
732 spin_lock_irqsave(&acdev->host->lock, flags);
733 val = readl(acdev->vbase + OP_MODE) &
734 ~(ULTRA_DMA_ENB | MULTI_WORD_DMA_ENB | DRQ_BLOCK_SIZE_MASK);
735 writel(val, acdev->vbase + OP_MODE);
736 val = readl(acdev->vbase + TM_CFG) & ~TRUEIDE_PIO_TIMING_MASK;
737 val |= pio << TRUEIDE_PIO_TIMING_SHIFT;
738 writel(val, acdev->vbase + TM_CFG);
739
740 cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 0);
741 cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 1);
742 spin_unlock_irqrestore(&acdev->host->lock, flags);
743 }
744
745 static void arasan_cf_set_dmamode(struct ata_port *ap, struct ata_device *adev)
746 {
747 struct arasan_cf_dev *acdev = ap->host->private_data;
748 u32 opmode, tmcfg, dma_mode = adev->dma_mode;
749 unsigned long flags;
750
751 spin_lock_irqsave(&acdev->host->lock, flags);
752 opmode = readl(acdev->vbase + OP_MODE) &
753 ~(MULTI_WORD_DMA_ENB | ULTRA_DMA_ENB);
754 tmcfg = readl(acdev->vbase + TM_CFG);
755
756 if ((dma_mode >= XFER_UDMA_0) && (dma_mode <= XFER_UDMA_6)) {
757 opmode |= ULTRA_DMA_ENB;
758 tmcfg &= ~ULTRA_DMA_TIMING_MASK;
759 tmcfg |= (dma_mode - XFER_UDMA_0) << ULTRA_DMA_TIMING_SHIFT;
760 } else if ((dma_mode >= XFER_MW_DMA_0) && (dma_mode <= XFER_MW_DMA_4)) {
761 opmode |= MULTI_WORD_DMA_ENB;
762 tmcfg &= ~TRUEIDE_MWORD_DMA_TIMING_MASK;
763 tmcfg |= (dma_mode - XFER_MW_DMA_0) <<
764 TRUEIDE_MWORD_DMA_TIMING_SHIFT;
765 } else {
766 dev_err(ap->dev, "Unknown DMA mode\n");
767 spin_unlock_irqrestore(&acdev->host->lock, flags);
768 return;
769 }
770
771 writel(opmode, acdev->vbase + OP_MODE);
772 writel(tmcfg, acdev->vbase + TM_CFG);
773 writel(DMA_XFER_MODE, acdev->vbase + XFER_CTR);
774
775 cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 0);
776 cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 1);
777 spin_unlock_irqrestore(&acdev->host->lock, flags);
778 }
779
780 static struct ata_port_operations arasan_cf_ops = {
781 .inherits = &ata_sff_port_ops,
782 .freeze = arasan_cf_freeze,
783 .error_handler = arasan_cf_error_handler,
784 .qc_issue = arasan_cf_qc_issue,
785 .set_piomode = arasan_cf_set_piomode,
786 .set_dmamode = arasan_cf_set_dmamode,
787 };
788
789 static int arasan_cf_probe(struct platform_device *pdev)
790 {
791 struct arasan_cf_dev *acdev;
792 struct arasan_cf_pdata *pdata = dev_get_platdata(&pdev->dev);
793 struct ata_host *host;
794 struct ata_port *ap;
795 struct resource *res;
796 u32 quirk;
797 irq_handler_t irq_handler = NULL;
798 int ret;
799
800 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
801 if (!res)
802 return -EINVAL;
803
804 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
805 DRIVER_NAME)) {
806 dev_warn(&pdev->dev, "Failed to get memory region resource\n");
807 return -ENOENT;
808 }
809
810 acdev = devm_kzalloc(&pdev->dev, sizeof(*acdev), GFP_KERNEL);
811 if (!acdev)
812 return -ENOMEM;
813
814 if (pdata)
815 quirk = pdata->quirk;
816 else
817 quirk = CF_BROKEN_UDMA; /* as it is on spear1340 */
818
819 /* if irq is 0, support only PIO */
820 acdev->irq = platform_get_irq(pdev, 0);
821 if (acdev->irq)
822 irq_handler = arasan_cf_interrupt;
823 else
824 quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA;
825
826 acdev->pbase = res->start;
827 acdev->vbase = devm_ioremap(&pdev->dev, res->start,
828 resource_size(res));
829 if (!acdev->vbase) {
830 dev_warn(&pdev->dev, "ioremap fail\n");
831 return -ENOMEM;
832 }
833
834 acdev->clk = devm_clk_get(&pdev->dev, NULL);
835 if (IS_ERR(acdev->clk)) {
836 dev_warn(&pdev->dev, "Clock not found\n");
837 return PTR_ERR(acdev->clk);
838 }
839
840 /* allocate host */
841 host = ata_host_alloc(&pdev->dev, 1);
842 if (!host) {
843 dev_warn(&pdev->dev, "alloc host fail\n");
844 return -ENOMEM;
845 }
846
847 ap = host->ports[0];
848 host->private_data = acdev;
849 acdev->host = host;
850 ap->ops = &arasan_cf_ops;
851 ap->pio_mask = ATA_PIO6;
852 ap->mwdma_mask = ATA_MWDMA4;
853 ap->udma_mask = ATA_UDMA6;
854
855 init_completion(&acdev->cf_completion);
856 init_completion(&acdev->dma_completion);
857 INIT_WORK(&acdev->work, data_xfer);
858 INIT_DELAYED_WORK(&acdev->dwork, delayed_finish);
859 dma_cap_set(DMA_MEMCPY, acdev->mask);
860
861 /* Handle platform specific quirks */
862 if (quirk) {
863 if (quirk & CF_BROKEN_PIO) {
864 ap->ops->set_piomode = NULL;
865 ap->pio_mask = 0;
866 }
867 if (quirk & CF_BROKEN_MWDMA)
868 ap->mwdma_mask = 0;
869 if (quirk & CF_BROKEN_UDMA)
870 ap->udma_mask = 0;
871 }
872 ap->flags |= ATA_FLAG_PIO_POLLING | ATA_FLAG_NO_ATAPI;
873
874 ap->ioaddr.cmd_addr = acdev->vbase + ATA_DATA_PORT;
875 ap->ioaddr.data_addr = acdev->vbase + ATA_DATA_PORT;
876 ap->ioaddr.error_addr = acdev->vbase + ATA_ERR_FTR;
877 ap->ioaddr.feature_addr = acdev->vbase + ATA_ERR_FTR;
878 ap->ioaddr.nsect_addr = acdev->vbase + ATA_SC;
879 ap->ioaddr.lbal_addr = acdev->vbase + ATA_SN;
880 ap->ioaddr.lbam_addr = acdev->vbase + ATA_CL;
881 ap->ioaddr.lbah_addr = acdev->vbase + ATA_CH;
882 ap->ioaddr.device_addr = acdev->vbase + ATA_SH;
883 ap->ioaddr.status_addr = acdev->vbase + ATA_STS_CMD;
884 ap->ioaddr.command_addr = acdev->vbase + ATA_STS_CMD;
885 ap->ioaddr.altstatus_addr = acdev->vbase + ATA_ASTS_DCTR;
886 ap->ioaddr.ctl_addr = acdev->vbase + ATA_ASTS_DCTR;
887
888 ata_port_desc(ap, "phy_addr %llx virt_addr %p",
889 (unsigned long long) res->start, acdev->vbase);
890
891 ret = cf_init(acdev);
892 if (ret)
893 return ret;
894
895 cf_card_detect(acdev, 0);
896
897 ret = ata_host_activate(host, acdev->irq, irq_handler, 0,
898 &arasan_cf_sht);
899 if (!ret)
900 return 0;
901
902 cf_exit(acdev);
903
904 return ret;
905 }
906
907 static int arasan_cf_remove(struct platform_device *pdev)
908 {
909 struct ata_host *host = platform_get_drvdata(pdev);
910 struct arasan_cf_dev *acdev = host->ports[0]->private_data;
911
912 ata_host_detach(host);
913 cf_exit(acdev);
914
915 return 0;
916 }
917
918 #ifdef CONFIG_PM_SLEEP
919 static int arasan_cf_suspend(struct device *dev)
920 {
921 struct ata_host *host = dev_get_drvdata(dev);
922 struct arasan_cf_dev *acdev = host->ports[0]->private_data;
923
924 if (acdev->dma_chan)
925 dmaengine_terminate_all(acdev->dma_chan);
926
927 cf_exit(acdev);
928 return ata_host_suspend(host, PMSG_SUSPEND);
929 }
930
931 static int arasan_cf_resume(struct device *dev)
932 {
933 struct ata_host *host = dev_get_drvdata(dev);
934 struct arasan_cf_dev *acdev = host->ports[0]->private_data;
935
936 cf_init(acdev);
937 ata_host_resume(host);
938
939 return 0;
940 }
941 #endif
942
943 static SIMPLE_DEV_PM_OPS(arasan_cf_pm_ops, arasan_cf_suspend, arasan_cf_resume);
944
945 #ifdef CONFIG_OF
946 static const struct of_device_id arasan_cf_id_table[] = {
947 { .compatible = "arasan,cf-spear1340" },
948 {}
949 };
950 MODULE_DEVICE_TABLE(of, arasan_cf_id_table);
951 #endif
952
953 static struct platform_driver arasan_cf_driver = {
954 .probe = arasan_cf_probe,
955 .remove = arasan_cf_remove,
956 .driver = {
957 .name = DRIVER_NAME,
958 .pm = &arasan_cf_pm_ops,
959 .of_match_table = of_match_ptr(arasan_cf_id_table),
960 },
961 };
962
963 module_platform_driver(arasan_cf_driver);
964
965 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
966 MODULE_DESCRIPTION("Arasan ATA Compact Flash driver");
967 MODULE_LICENSE("GPL");
968 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support