drivers/block/rsxx/rsxx_priv.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3 * Filename: rsxx_priv.h
   4 *
   5 * Authors: Joshua Morris <josh.h.morris@us.ibm.com>
   6 *       Philip Kelleher <pjk1939@linux.vnet.ibm.com>
   7 *
   8 * (C) Copyright 2013 IBM Corporation
   9 */
  10
  11 #ifndef __RSXX_PRIV_H__
  12 #define __RSXX_PRIV_H__
  13
  14 #include <linux/version.h>
  15 #include <linux/semaphore.h>
  16
  17 #include <linux/fs.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/mutex.h>
  20 #include <linux/pci.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/sysfs.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/bio.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/timer.h>
  27 #include <linux/ioctl.h>
  28 #include <linux/delay.h>
  29
  30 #include "rsxx.h"
  31 #include "rsxx_cfg.h"
  32
  33 struct proc_cmd;
  34
  35 #define PCI_DEVICE_ID_FS70_FLASH        0x04A9
  36 #define PCI_DEVICE_ID_FS80_FLASH        0x04AA
  37
  38 #define RS70_PCI_REV_SUPPORTED  4
  39
  40 #define DRIVER_NAME "rsxx"
  41 #define DRIVER_VERSION "4.0.3.2516"
  42
  43 /* Block size is 4096 */
  44 #define RSXX_HW_BLK_SHIFT               12
  45 #define RSXX_HW_BLK_SIZE                (1 << RSXX_HW_BLK_SHIFT)
  46 #define RSXX_HW_BLK_MASK                (RSXX_HW_BLK_SIZE - 1)
  47
  48 #define MAX_CREG_DATA8  32
  49 #define LOG_BUF_SIZE8   128
  50
  51 #define RSXX_MAX_OUTSTANDING_CMDS       255
  52 #define RSXX_CS_IDX_MASK                0xff
  53
  54 #define STATUS_BUFFER_SIZE8     4096
  55 #define COMMAND_BUFFER_SIZE8    4096
  56
  57 #define RSXX_MAX_TARGETS        8
  58
  59 struct dma_tracker_list;
  60
  61 /* DMA Command/Status Buffer structure */
  62 struct rsxx_cs_buffer {
  63         dma_addr_t      dma_addr;
  64         void            *buf;
  65         u32             idx;
  66 };
  67
  68 struct rsxx_dma_stats {
  69         u32 crc_errors;
  70         u32 hard_errors;
  71         u32 soft_errors;
  72         u32 writes_issued;
  73         u32 writes_failed;
  74         u32 reads_issued;
  75         u32 reads_failed;
  76         u32 reads_retried;
  77         u32 discards_issued;
  78         u32 discards_failed;
  79         u32 done_rescheduled;
  80         u32 issue_rescheduled;
  81         u32 dma_sw_err;
  82         u32 dma_hw_fault;
  83         u32 dma_cancelled;
  84         u32 sw_q_depth;         /* Number of DMAs on the SW queue. */
  85         atomic_t hw_q_depth;    /* Number of DMAs queued to HW. */
  86 };
  87
  88 struct rsxx_dma_ctrl {
  89         struct rsxx_cardinfo            *card;
  90         int                             id;
  91         void                            __iomem *regmap;
  92         struct rsxx_cs_buffer           status;
  93         struct rsxx_cs_buffer           cmd;
  94         u16                             e_cnt;
  95         spinlock_t                      queue_lock;
  96         struct list_head                queue;
  97         struct workqueue_struct         *issue_wq;
  98         struct work_struct              issue_dma_work;
  99         struct workqueue_struct         *done_wq;
 100         struct work_struct              dma_done_work;
 101         struct timer_list               activity_timer;
 102         struct dma_tracker_list         *trackers;
 103         struct rsxx_dma_stats           stats;
 104         struct mutex                    work_lock;
 105 };
 106
 107 struct rsxx_cardinfo {
 108         struct pci_dev          *dev;
 109         unsigned int            halt;
 110         unsigned int            eeh_state;
 111
 112         void                    __iomem *regmap;
 113         spinlock_t              irq_lock;
 114         unsigned int            isr_mask;
 115         unsigned int            ier_mask;
 116
 117         struct rsxx_card_cfg    config;
 118         int                     config_valid;
 119
 120         /* Embedded CPU Communication */
 121         struct {
 122                 spinlock_t              lock;
 123                 bool                    active;
 124                 struct creg_cmd         *active_cmd;
 125                 struct workqueue_struct *creg_wq;
 126                 struct work_struct      done_work;
 127                 struct list_head        queue;
 128                 unsigned int            q_depth;
 129                 /* Cache the creg status to prevent ioreads */
 130                 struct {
 131                         u32             stat;
 132                         u32             failed_cancel_timer;
 133                         u32             creg_timeout;
 134                 } creg_stats;
 135                 struct timer_list       cmd_timer;
 136                 struct mutex            reset_lock;
 137                 int                     reset;
 138         } creg_ctrl;
 139
 140         struct {
 141                 char tmp[MAX_CREG_DATA8];
 142                 char buf[LOG_BUF_SIZE8]; /* terminated */
 143                 int buf_len;
 144         } log;
 145
 146         struct workqueue_struct *event_wq;
 147         struct work_struct      event_work;
 148         unsigned int            state;
 149         u64                     size8;
 150
 151         /* Lock the device attach/detach function */
 152         struct mutex            dev_lock;
 153
 154         /* Block Device Variables */
 155         bool                    bdev_attached;
 156         int                     disk_id;
 157         int                     major;
 158         struct request_queue    *queue;
 159         struct gendisk          *gendisk;
 160         struct {
 161                 /* Used to convert a byte address to a device address. */
 162                 u64 lower_mask;
 163                 u64 upper_shift;
 164                 u64 upper_mask;
 165                 u64 target_mask;
 166                 u64 target_shift;
 167         } _stripe;
 168         unsigned int            dma_fault;
 169
 170         int                     scrub_hard;
 171
 172         int                     n_targets;
 173         struct rsxx_dma_ctrl    *ctrl;
 174
 175         struct dentry           *debugfs_dir;
 176 };
 177
 178 enum rsxx_pci_regmap {
 179         HWID            = 0x00, /* Hardware Identification Register */
 180         SCRATCH         = 0x04, /* Scratch/Debug Register */
 181         RESET           = 0x08, /* Reset Register */
 182         ISR             = 0x10, /* Interrupt Status Register */
 183         IER             = 0x14, /* Interrupt Enable Register */
 184         IPR             = 0x18, /* Interrupt Poll Register */
 185         CB_ADD_LO       = 0x20, /* Command Host Buffer Address [31:0] */
 186         CB_ADD_HI       = 0x24, /* Command Host Buffer Address [63:32]*/
 187         HW_CMD_IDX      = 0x28, /* Hardware Processed Command Index */
 188         SW_CMD_IDX      = 0x2C, /* Software Processed Command Index */
 189         SB_ADD_LO       = 0x30, /* Status Host Buffer Address [31:0] */
 190         SB_ADD_HI       = 0x34, /* Status Host Buffer Address [63:32] */
 191         HW_STATUS_CNT   = 0x38, /* Hardware Status Counter */
 192         SW_STATUS_CNT   = 0x3C, /* Deprecated */
 193         CREG_CMD        = 0x40, /* CPU Command Register */
 194         CREG_ADD        = 0x44, /* CPU Address Register */
 195         CREG_CNT        = 0x48, /* CPU Count Register */
 196         CREG_STAT       = 0x4C, /* CPU Status Register */
 197         CREG_DATA0      = 0x50, /* CPU Data Registers */
 198         CREG_DATA1      = 0x54,
 199         CREG_DATA2      = 0x58,
 200         CREG_DATA3      = 0x5C,
 201         CREG_DATA4      = 0x60,
 202         CREG_DATA5      = 0x64,
 203         CREG_DATA6      = 0x68,
 204         CREG_DATA7      = 0x6c,
 205         INTR_COAL       = 0x70, /* Interrupt Coalescing Register */
 206         HW_ERROR        = 0x74, /* Card Error Register */
 207         PCI_DEBUG0      = 0x78, /* PCI Debug Registers */
 208         PCI_DEBUG1      = 0x7C,
 209         PCI_DEBUG2      = 0x80,
 210         PCI_DEBUG3      = 0x84,
 211         PCI_DEBUG4      = 0x88,
 212         PCI_DEBUG5      = 0x8C,
 213         PCI_DEBUG6      = 0x90,
 214         PCI_DEBUG7      = 0x94,
 215         PCI_POWER_THROTTLE = 0x98,
 216         PERF_CTRL       = 0x9c,
 217         PERF_TIMER_LO   = 0xa0,
 218         PERF_TIMER_HI   = 0xa4,
 219         PERF_RD512_LO   = 0xa8,
 220         PERF_RD512_HI   = 0xac,
 221         PERF_WR512_LO   = 0xb0,
 222         PERF_WR512_HI   = 0xb4,
 223         PCI_RECONFIG    = 0xb8,
 224 };
 225
 226 enum rsxx_intr {
 227         CR_INTR_DMA0    = 0x00000001,
 228         CR_INTR_CREG    = 0x00000002,
 229         CR_INTR_DMA1    = 0x00000004,
 230         CR_INTR_EVENT   = 0x00000008,
 231         CR_INTR_DMA2    = 0x00000010,
 232         CR_INTR_DMA3    = 0x00000020,
 233         CR_INTR_DMA4    = 0x00000040,
 234         CR_INTR_DMA5    = 0x00000080,
 235         CR_INTR_DMA6    = 0x00000100,
 236         CR_INTR_DMA7    = 0x00000200,
 237         CR_INTR_ALL_C   = 0x0000003f,
 238         CR_INTR_ALL_G   = 0x000003ff,
 239         CR_INTR_DMA_ALL = 0x000003f5,
 240         CR_INTR_ALL     = 0xffffffff,
 241 };
 242
 243 static inline int CR_INTR_DMA(int N)
 244 {
 245         static const unsigned int _CR_INTR_DMA[] = {
 246                 CR_INTR_DMA0, CR_INTR_DMA1, CR_INTR_DMA2, CR_INTR_DMA3,
 247                 CR_INTR_DMA4, CR_INTR_DMA5, CR_INTR_DMA6, CR_INTR_DMA7
 248         };
 249         return _CR_INTR_DMA[N];
 250 }
 251 enum rsxx_pci_reset {
 252         DMA_QUEUE_RESET         = 0x00000001,
 253 };
 254
 255 enum rsxx_hw_fifo_flush {
 256         RSXX_FLUSH_BUSY         = 0x00000002,
 257         RSXX_FLUSH_TIMEOUT      = 0x00000004,
 258 };
 259
 260 enum rsxx_pci_revision {
 261         RSXX_DISCARD_SUPPORT = 2,
 262         RSXX_EEH_SUPPORT     = 3,
 263 };
 264
 265 enum rsxx_creg_cmd {
 266         CREG_CMD_TAG_MASK       = 0x0000FF00,
 267         CREG_OP_WRITE           = 0x000000C0,
 268         CREG_OP_READ            = 0x000000E0,
 269 };
 270
 271 enum rsxx_creg_addr {
 272         CREG_ADD_CARD_CMD               = 0x80001000,
 273         CREG_ADD_CARD_STATE             = 0x80001004,
 274         CREG_ADD_CARD_SIZE              = 0x8000100c,
 275         CREG_ADD_CAPABILITIES           = 0x80001050,
 276         CREG_ADD_LOG                    = 0x80002000,
 277         CREG_ADD_NUM_TARGETS            = 0x80003000,
 278         CREG_ADD_CRAM                   = 0xA0000000,
 279         CREG_ADD_CONFIG                 = 0xB0000000,
 280 };
 281
 282 enum rsxx_creg_card_cmd {
 283         CARD_CMD_STARTUP                = 1,
 284         CARD_CMD_SHUTDOWN               = 2,
 285         CARD_CMD_LOW_LEVEL_FORMAT       = 3,
 286         CARD_CMD_FPGA_RECONFIG_BR       = 4,
 287         CARD_CMD_FPGA_RECONFIG_MAIN     = 5,
 288         CARD_CMD_BACKUP                 = 6,
 289         CARD_CMD_RESET                  = 7,
 290         CARD_CMD_deprecated             = 8,
 291         CARD_CMD_UNINITIALIZE           = 9,
 292         CARD_CMD_DSTROY_EMERGENCY       = 10,
 293         CARD_CMD_DSTROY_NORMAL          = 11,
 294         CARD_CMD_DSTROY_EXTENDED        = 12,
 295         CARD_CMD_DSTROY_ABORT           = 13,
 296 };
 297
 298 enum rsxx_card_state {
 299         CARD_STATE_SHUTDOWN             = 0x00000001,
 300         CARD_STATE_STARTING             = 0x00000002,
 301         CARD_STATE_FORMATTING           = 0x00000004,
 302         CARD_STATE_UNINITIALIZED        = 0x00000008,
 303         CARD_STATE_GOOD                 = 0x00000010,
 304         CARD_STATE_SHUTTING_DOWN        = 0x00000020,
 305         CARD_STATE_FAULT                = 0x00000040,
 306         CARD_STATE_RD_ONLY_FAULT        = 0x00000080,
 307         CARD_STATE_DSTROYING            = 0x00000100,
 308 };
 309
 310 enum rsxx_led {
 311         LED_DEFAULT     = 0x0,
 312         LED_IDENTIFY    = 0x1,
 313         LED_SOAK        = 0x2,
 314 };
 315
 316 enum rsxx_creg_flash_lock {
 317         CREG_FLASH_LOCK         = 1,
 318         CREG_FLASH_UNLOCK       = 2,
 319 };
 320
 321 enum rsxx_card_capabilities {
 322         CARD_CAP_SUBPAGE_WRITES = 0x00000080,
 323 };
 324
 325 enum rsxx_creg_stat {
 326         CREG_STAT_STATUS_MASK   = 0x00000003,
 327         CREG_STAT_SUCCESS       = 0x1,
 328         CREG_STAT_ERROR         = 0x2,
 329         CREG_STAT_CHAR_PENDING  = 0x00000004, /* Character I/O pending bit */
 330         CREG_STAT_LOG_PENDING   = 0x00000008, /* HW log message pending bit */
 331         CREG_STAT_TAG_MASK      = 0x0000ff00,
 332 };
 333
 334 enum rsxx_dma_finish {
 335         FREE_DMA        = 0x0,
 336         COMPLETE_DMA    = 0x1,
 337 };
 338
 339 static inline unsigned int CREG_DATA(int N)
 340 {
 341         return CREG_DATA0 + (N << 2);
 342 }
 343
 344 /*----------------- Convenient Log Wrappers -------------------*/
 345 #define CARD_TO_DEV(__CARD)     (&(__CARD)->dev->dev)
 346
 347 /***** config.c *****/
 348 int rsxx_load_config(struct rsxx_cardinfo *card);
 349
 350 /***** core.c *****/
 351 void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr);
 352 void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr);
 353 void rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card,
 354                                  unsigned int intr);
 355 void rsxx_disable_ier_and_isr(struct rsxx_cardinfo *card,
 356                                   unsigned int intr);
 357
 358 /***** dev.c *****/
 359 int rsxx_attach_dev(struct rsxx_cardinfo *card);
 360 void rsxx_detach_dev(struct rsxx_cardinfo *card);
 361 int rsxx_setup_dev(struct rsxx_cardinfo *card);
 362 void rsxx_destroy_dev(struct rsxx_cardinfo *card);
 363 int rsxx_dev_init(void);
 364 void rsxx_dev_cleanup(void);
 365
 366 /***** dma.c ****/
 367 typedef void (*rsxx_dma_cb)(struct rsxx_cardinfo *card,
 368                                 void *cb_data,
 369                                 unsigned int status);
 370 int rsxx_dma_setup(struct rsxx_cardinfo *card);
 371 void rsxx_dma_destroy(struct rsxx_cardinfo *card);
 372 int rsxx_dma_init(void);
 373 int rsxx_cleanup_dma_queue(struct rsxx_dma_ctrl *ctrl,
 374                                 struct list_head *q,
 375                                 unsigned int done);
 376 int rsxx_dma_cancel(struct rsxx_dma_ctrl *ctrl);
 377 void rsxx_dma_cleanup(void);
 378 void rsxx_dma_queue_reset(struct rsxx_cardinfo *card);
 379 int rsxx_dma_configure(struct rsxx_cardinfo *card);
 380 blk_status_t rsxx_dma_queue_bio(struct rsxx_cardinfo *card,
 381                            struct bio *bio,
 382                            atomic_t *n_dmas,
 383                            rsxx_dma_cb cb,
 384                            void *cb_data);
 385 int rsxx_hw_buffers_init(struct pci_dev *dev, struct rsxx_dma_ctrl *ctrl);
 386 int rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card);
 387 int rsxx_eeh_remap_dmas(struct rsxx_cardinfo *card);
 388
 389 /***** cregs.c *****/
 390 int rsxx_creg_write(struct rsxx_cardinfo *card, u32 addr,
 391                         unsigned int size8,
 392                         void *data,
 393                         int byte_stream);
 394 int rsxx_creg_read(struct rsxx_cardinfo *card,
 395                        u32 addr,
 396                        unsigned int size8,
 397                        void *data,
 398                        int byte_stream);
 399 int rsxx_read_hw_log(struct rsxx_cardinfo *card);
 400 int rsxx_get_card_state(struct rsxx_cardinfo *card,
 401                             unsigned int *state);
 402 int rsxx_get_card_size8(struct rsxx_cardinfo *card, u64 *size8);
 403 int rsxx_get_num_targets(struct rsxx_cardinfo *card,
 404                              unsigned int *n_targets);
 405 int rsxx_get_card_capabilities(struct rsxx_cardinfo *card,
 406                                    u32 *capabilities);
 407 int rsxx_issue_card_cmd(struct rsxx_cardinfo *card, u32 cmd);
 408 int rsxx_creg_setup(struct rsxx_cardinfo *card);
 409 void rsxx_creg_destroy(struct rsxx_cardinfo *card);
 410 int rsxx_creg_init(void);
 411 void rsxx_creg_cleanup(void);
 412 int rsxx_reg_access(struct rsxx_cardinfo *card,
 413                         struct rsxx_reg_access __user *ucmd,
 414                         int read);
 415 void rsxx_eeh_save_issued_creg(struct rsxx_cardinfo *card);
 416 void rsxx_kick_creg_queue(struct rsxx_cardinfo *card);
 417
 418
 419
 420 #endif /* __DRIVERS_BLOCK_RSXX_H__ */