drivers/clk/qcom/gdsc.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef __QCOM_GDSC_H__
   7 #define __QCOM_GDSC_H__
   8
   9 #include <linux/err.h>
  10 #include <linux/pm_domain.h>
  11
  12 struct regmap;
  13 struct reset_controller_dev;
  14
  15 /**
  16  * struct gdsc - Globally Distributed Switch Controller
  17  * @pd: generic power domain
  18  * @regmap: regmap for MMIO accesses
  19  * @gdscr: gsdc control register
  20  * @gds_hw_ctrl: gds_hw_ctrl register
  21  * @cxcs: offsets of branch registers to toggle mem/periph bits in
  22  * @cxc_count: number of @cxcs
  23  * @pwrsts: Possible powerdomain power states
  24  * @resets: ids of resets associated with this gdsc
  25  * @reset_count: number of @resets
  26  * @rcdev: reset controller
  27  */
  28 struct gdsc {
  29         struct generic_pm_domain        pd;
  30         struct generic_pm_domain        *parent;
  31         struct regmap                   *regmap;
  32         unsigned int                    gdscr;
  33         unsigned int                    gds_hw_ctrl;
  34         unsigned int                    clamp_io_ctrl;
  35         unsigned int                    *cxcs;
  36         unsigned int                    cxc_count;
  37         const u8                        pwrsts;
  38 /* Powerdomain allowable state bitfields */
  39 #define PWRSTS_OFF              BIT(0)
  40 #define PWRSTS_RET              BIT(1)
  41 #define PWRSTS_ON               BIT(2)
  42 #define PWRSTS_OFF_ON           (PWRSTS_OFF | PWRSTS_ON)
  43 #define PWRSTS_RET_ON           (PWRSTS_RET | PWRSTS_ON)
  44         const u8                        flags;
  45 #define VOTABLE         BIT(0)
  46 #define CLAMP_IO        BIT(1)
  47 #define HW_CTRL         BIT(2)
  48 #define SW_RESET        BIT(3)
  49 #define AON_RESET       BIT(4)
  50 #define POLL_CFG_GDSCR  BIT(5)
  51 #define ALWAYS_ON       BIT(6)
  52         struct reset_controller_dev     *rcdev;
  53         unsigned int                    *resets;
  54         unsigned int                    reset_count;
  55 };
  56
  57 struct gdsc_desc {
  58         struct device *dev;
  59         struct gdsc **scs;
  60         size_t num;
  61 };
  62
  63 #ifdef CONFIG_QCOM_GDSC
  64 int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
  65                   struct regmap *);
  66 void gdsc_unregister(struct gdsc_desc *desc);
  67 #else
  68 static inline int gdsc_register(struct gdsc_desc *desc,
  69                                 struct reset_controller_dev *rcdev,
  70                                 struct regmap *r)
  71 {
  72         return -ENOSYS;
  73 }
  74
  75 static inline void gdsc_unregister(struct gdsc_desc *desc) {};
  76 #endif /* CONFIG_QCOM_GDSC */
  77 #endif /* __QCOM_GDSC_H__ */