drivers/clk/renesas/r8a77995-cpg-mssr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a77995 Clock Pulse Generator / Module Standby and Software Reset
   4  *
   5  * Copyright (C) 2017 Glider bvba
   6  *
   7  * Based on r8a7795-cpg-mssr.c
   8  *
   9  * Copyright (C) 2015 Glider bvba
  10  * Copyright (C) 2015 Renesas Electronics Corp.
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/soc/renesas/rcar-rst.h>
  17
  18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
  19
  20 #include "renesas-cpg-mssr.h"
  21 #include "rcar-gen3-cpg.h"
  22
  23 enum clk_ids {
  24         /* Core Clock Outputs exported to DT */
  25         LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
  26
  27         /* External Input Clocks */
  28         CLK_EXTAL,
  29
  30         /* Internal Core Clocks */
  31         CLK_MAIN,
  32         CLK_PLL0,
  33         CLK_PLL1,
  34         CLK_PLL3,
  35         CLK_PLL0D2,
  36         CLK_PLL0D3,
  37         CLK_PLL0D5,
  38         CLK_PLL1D2,
  39         CLK_PE,
  40         CLK_S0,
  41         CLK_S1,
  42         CLK_S2,
  43         CLK_S3,
  44         CLK_SDSRC,
  45         CLK_RINT,
  46         CLK_OCO,
  47
  48         /* Module Clocks */
  49         MOD_CLK_BASE
  50 };
  51
  52 static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
  53         /* External Clock Inputs */
  54         DEF_INPUT("extal",     CLK_EXTAL),
  55
  56         /* Internal Core Clocks */
  57         DEF_BASE(".main",      CLK_MAIN, CLK_TYPE_GEN3_MAIN,       CLK_EXTAL),
  58         DEF_BASE(".pll1",      CLK_PLL1, CLK_TYPE_GEN3_PLL1,       CLK_MAIN),
  59         DEF_BASE(".pll3",      CLK_PLL3, CLK_TYPE_GEN3_PLL3,       CLK_MAIN),
  60
  61         DEF_FIXED(".pll0",     CLK_PLL0,           CLK_MAIN,       4, 250),
  62         DEF_FIXED(".pll0d2",   CLK_PLL0D2,         CLK_PLL0,       2, 1),
  63         DEF_FIXED(".pll0d3",   CLK_PLL0D3,         CLK_PLL0,       3, 1),
  64         DEF_FIXED(".pll0d5",   CLK_PLL0D5,         CLK_PLL0,       5, 1),
  65         DEF_FIXED(".pll1d2",   CLK_PLL1D2,         CLK_PLL1,       2, 1),
  66         DEF_FIXED(".pe",       CLK_PE,             CLK_PLL0D3,     4, 1),
  67         DEF_FIXED(".s0",       CLK_S0,             CLK_PLL1,       2, 1),
  68         DEF_FIXED(".s1",       CLK_S1,             CLK_PLL1,       3, 1),
  69         DEF_FIXED(".s2",       CLK_S2,             CLK_PLL1,       4, 1),
  70         DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
  71         DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
  72
  73         DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),
  74
  75         DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
  76
  77         /* Core Clock Outputs */
  78         DEF_FIXED("z2",        R8A77995_CLK_Z2,    CLK_PLL0D3,     1, 1),
  79         DEF_FIXED("ztr",       R8A77995_CLK_ZTR,   CLK_PLL1,       6, 1),
  80         DEF_FIXED("zt",        R8A77995_CLK_ZT,    CLK_PLL1,       4, 1),
  81         DEF_FIXED("zx",        R8A77995_CLK_ZX,    CLK_PLL1,       3, 1),
  82         DEF_FIXED("s0d1",      R8A77995_CLK_S0D1,  CLK_S0,         1, 1),
  83         DEF_FIXED("s1d1",      R8A77995_CLK_S1D1,  CLK_S1,         1, 1),
  84         DEF_FIXED("s1d2",      R8A77995_CLK_S1D2,  CLK_S1,         2, 1),
  85         DEF_FIXED("s1d4",      R8A77995_CLK_S1D4,  CLK_S1,         4, 1),
  86         DEF_FIXED("s2d1",      R8A77995_CLK_S2D1,  CLK_S2,         1, 1),
  87         DEF_FIXED("s2d2",      R8A77995_CLK_S2D2,  CLK_S2,         2, 1),
  88         DEF_FIXED("s2d4",      R8A77995_CLK_S2D4,  CLK_S2,         4, 1),
  89         DEF_FIXED("s3d1",      R8A77995_CLK_S3D1,  CLK_S3,         1, 1),
  90         DEF_FIXED("s3d2",      R8A77995_CLK_S3D2,  CLK_S3,         2, 1),
  91         DEF_FIXED("s3d4",      R8A77995_CLK_S3D4,  CLK_S3,         4, 1),
  92
  93         DEF_FIXED("cl",        R8A77995_CLK_CL,    CLK_PLL1,      48, 1),
  94         DEF_FIXED("cp",        R8A77995_CLK_CP,    CLK_EXTAL,      2, 1),
  95         DEF_FIXED("cpex",      R8A77995_CLK_CPEX,  CLK_EXTAL,      4, 1),
  96
  97         DEF_DIV6_RO("osc",     R8A77995_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
  98
  99         DEF_GEN3_PE("s1d4c",   R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
 100         DEF_GEN3_PE("s3d1c",   R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
 101         DEF_GEN3_PE("s3d2c",   R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
 102         DEF_GEN3_PE("s3d4c",   R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
 103
 104         DEF_GEN3_SD("sd0",     R8A77995_CLK_SD0,   CLK_SDSRC,     0x268),
 105
 106         DEF_DIV6P1("canfd",    R8A77995_CLK_CANFD, CLK_PLL0D3,    0x244),
 107         DEF_DIV6P1("mso",      R8A77995_CLK_MSO,   CLK_PLL1D2,    0x014),
 108
 109         DEF_GEN3_RCKSEL("r",   R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
 110 };
 111
 112 static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
 113         DEF_MOD("scif5",                 202,   R8A77995_CLK_S3D4C),
 114         DEF_MOD("scif4",                 203,   R8A77995_CLK_S3D4C),
 115         DEF_MOD("scif3",                 204,   R8A77995_CLK_S3D4C),
 116         DEF_MOD("scif1",                 206,   R8A77995_CLK_S3D4C),
 117         DEF_MOD("scif0",                 207,   R8A77995_CLK_S3D4C),
 118         DEF_MOD("msiof3",                208,   R8A77995_CLK_MSO),
 119         DEF_MOD("msiof2",                209,   R8A77995_CLK_MSO),
 120         DEF_MOD("msiof1",                210,   R8A77995_CLK_MSO),
 121         DEF_MOD("msiof0",                211,   R8A77995_CLK_MSO),
 122         DEF_MOD("sys-dmac2",             217,   R8A77995_CLK_S3D1),
 123         DEF_MOD("sys-dmac1",             218,   R8A77995_CLK_S3D1),
 124         DEF_MOD("sys-dmac0",             219,   R8A77995_CLK_S3D1),
 125         DEF_MOD("cmt3",                  300,   R8A77995_CLK_R),
 126         DEF_MOD("cmt2",                  301,   R8A77995_CLK_R),
 127         DEF_MOD("cmt1",                  302,   R8A77995_CLK_R),
 128         DEF_MOD("cmt0",                  303,   R8A77995_CLK_R),
 129         DEF_MOD("scif2",                 310,   R8A77995_CLK_S3D4C),
 130         DEF_MOD("emmc0",                 312,   R8A77995_CLK_SD0),
 131         DEF_MOD("usb-dmac0",             330,   R8A77995_CLK_S3D1),
 132         DEF_MOD("usb-dmac1",             331,   R8A77995_CLK_S3D1),
 133         DEF_MOD("rwdt",                  402,   R8A77995_CLK_R),
 134         DEF_MOD("intc-ex",               407,   R8A77995_CLK_CP),
 135         DEF_MOD("intc-ap",               408,   R8A77995_CLK_S1D2),
 136         DEF_MOD("audmac0",               502,   R8A77995_CLK_S1D2),
 137         DEF_MOD("hscif3",                517,   R8A77995_CLK_S3D1C),
 138         DEF_MOD("hscif0",                520,   R8A77995_CLK_S3D1C),
 139         DEF_MOD("thermal",               522,   R8A77995_CLK_CP),
 140         DEF_MOD("pwm",                   523,   R8A77995_CLK_S3D4C),
 141         DEF_MOD("fcpvd1",                602,   R8A77995_CLK_S1D2),
 142         DEF_MOD("fcpvd0",                603,   R8A77995_CLK_S1D2),
 143         DEF_MOD("fcpvbs",                607,   R8A77995_CLK_S0D1),
 144         DEF_MOD("vspd1",                 622,   R8A77995_CLK_S1D2),
 145         DEF_MOD("vspd0",                 623,   R8A77995_CLK_S1D2),
 146         DEF_MOD("vspbs",                 627,   R8A77995_CLK_S0D1),
 147         DEF_MOD("ehci0",                 703,   R8A77995_CLK_S3D2),
 148         DEF_MOD("hsusb",                 704,   R8A77995_CLK_S3D2),
 149         DEF_MOD("cmm1",                  710,   R8A77995_CLK_S1D1),
 150         DEF_MOD("cmm0",                  711,   R8A77995_CLK_S1D1),
 151         DEF_MOD("du1",                   723,   R8A77995_CLK_S1D1),
 152         DEF_MOD("du0",                   724,   R8A77995_CLK_S1D1),
 153         DEF_MOD("lvds",                  727,   R8A77995_CLK_S2D1),
 154         DEF_MOD("vin4",                  807,   R8A77995_CLK_S1D2),
 155         DEF_MOD("etheravb",              812,   R8A77995_CLK_S3D2),
 156         DEF_MOD("imr0",                  823,   R8A77995_CLK_S1D2),
 157         DEF_MOD("gpio6",                 906,   R8A77995_CLK_S3D4),
 158         DEF_MOD("gpio5",                 907,   R8A77995_CLK_S3D4),
 159         DEF_MOD("gpio4",                 908,   R8A77995_CLK_S3D4),
 160         DEF_MOD("gpio3",                 909,   R8A77995_CLK_S3D4),
 161         DEF_MOD("gpio2",                 910,   R8A77995_CLK_S3D4),
 162         DEF_MOD("gpio1",                 911,   R8A77995_CLK_S3D4),
 163         DEF_MOD("gpio0",                 912,   R8A77995_CLK_S3D4),
 164         DEF_MOD("can-fd",                914,   R8A77995_CLK_S3D2),
 165         DEF_MOD("can-if1",               915,   R8A77995_CLK_S3D4),
 166         DEF_MOD("can-if0",               916,   R8A77995_CLK_S3D4),
 167         DEF_MOD("i2c3",                  928,   R8A77995_CLK_S3D2),
 168         DEF_MOD("i2c2",                  929,   R8A77995_CLK_S3D2),
 169         DEF_MOD("i2c1",                  930,   R8A77995_CLK_S3D2),
 170         DEF_MOD("i2c0",                  931,   R8A77995_CLK_S3D2),
 171         DEF_MOD("ssi-all",              1005,   R8A77995_CLK_S3D4),
 172         DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
 173         DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
 174         DEF_MOD("scu-all",              1017,   R8A77995_CLK_S3D4),
 175         DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
 176         DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
 177         DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
 178         DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
 179         DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
 180         DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
 181 };
 182
 183 static const unsigned int r8a77995_crit_mod_clks[] __initconst = {
 184         MOD_CLK_ID(408),        /* INTC-AP (GIC) */
 185 };
 186
 187
 188 /*
 189  * CPG Clock Data
 190  */
 191
 192 /*
 193  * MD19         EXTAL (MHz)     PLL0            PLL1            PLL3
 194  *--------------------------------------------------------------------
 195  * 0            48 x 1          x250/4          x100/3          x100/3
 196  * 1            48 x 1          x250/4          x100/3          x58/3
 197  */
 198 #define CPG_PLL_CONFIG_INDEX(md)        (((md) & BIT(19)) >> 19)
 199
 200 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
 201         /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
 202         { 1,            100,    3,      100,    3,      },
 203         { 1,            100,    3,      58,     3,      },
 204 };
 205
 206 static int __init r8a77995_cpg_mssr_init(struct device *dev)
 207 {
 208         const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
 209         u32 cpg_mode;
 210         int error;
 211
 212         error = rcar_rst_read_mode_pins(&cpg_mode);
 213         if (error)
 214                 return error;
 215
 216         cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 217
 218         return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
 219 }
 220
 221 const struct cpg_mssr_info r8a77995_cpg_mssr_info __initconst = {
 222         /* Core Clocks */
 223         .core_clks = r8a77995_core_clks,
 224         .num_core_clks = ARRAY_SIZE(r8a77995_core_clks),
 225         .last_dt_core_clk = LAST_DT_CORE_CLK,
 226         .num_total_core_clks = MOD_CLK_BASE,
 227
 228         /* Module Clocks */
 229         .mod_clks = r8a77995_mod_clks,
 230         .num_mod_clks = ARRAY_SIZE(r8a77995_mod_clks),
 231         .num_hw_mod_clks = 12 * 32,
 232
 233         /* Critical Module Clocks */
 234         .crit_mod_clks = r8a77995_crit_mod_clks,
 235         .num_crit_mod_clks = ARRAY_SIZE(r8a77995_crit_mod_clks),
 236
 237         /* Callbacks */
 238         .init = r8a77995_cpg_mssr_init,
 239         .cpg_clk_register = rcar_gen3_cpg_clk_register,
 240 };