?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / clk / samsung / clk-exynos5433.c
blob4b1aa9382ad28e01e755e6207d78c0720ec5c665
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
4 * Author: Chanwoo Choi <cw00.choi@samsung.com>
5 *
6 * Common Clock Framework support for Exynos5433 SoC.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/slab.h>
17
18 #include <dt-bindings/clock/exynos5433.h>
19
20 #include "clk.h"
21 #include "clk-cpu.h"
22 #include "clk-pll.h"
23
24 /*
25 * Register offset definitions for CMU_TOP
26 */
27 #define ISP_PLL_LOCK 0x0000
28 #define AUD_PLL_LOCK 0x0004
29 #define ISP_PLL_CON0 0x0100
30 #define ISP_PLL_CON1 0x0104
31 #define ISP_PLL_FREQ_DET 0x0108
32 #define AUD_PLL_CON0 0x0110
33 #define AUD_PLL_CON1 0x0114
34 #define AUD_PLL_CON2 0x0118
35 #define AUD_PLL_FREQ_DET 0x011c
36 #define MUX_SEL_TOP0 0x0200
37 #define MUX_SEL_TOP1 0x0204
38 #define MUX_SEL_TOP2 0x0208
39 #define MUX_SEL_TOP3 0x020c
40 #define MUX_SEL_TOP4 0x0210
41 #define MUX_SEL_TOP_MSCL 0x0220
42 #define MUX_SEL_TOP_CAM1 0x0224
43 #define MUX_SEL_TOP_DISP 0x0228
44 #define MUX_SEL_TOP_FSYS0 0x0230
45 #define MUX_SEL_TOP_FSYS1 0x0234
46 #define MUX_SEL_TOP_PERIC0 0x0238
47 #define MUX_SEL_TOP_PERIC1 0x023c
48 #define MUX_ENABLE_TOP0 0x0300
49 #define MUX_ENABLE_TOP1 0x0304
50 #define MUX_ENABLE_TOP2 0x0308
51 #define MUX_ENABLE_TOP3 0x030c
52 #define MUX_ENABLE_TOP4 0x0310
53 #define MUX_ENABLE_TOP_MSCL 0x0320
54 #define MUX_ENABLE_TOP_CAM1 0x0324
55 #define MUX_ENABLE_TOP_DISP 0x0328
56 #define MUX_ENABLE_TOP_FSYS0 0x0330
57 #define MUX_ENABLE_TOP_FSYS1 0x0334
58 #define MUX_ENABLE_TOP_PERIC0 0x0338
59 #define MUX_ENABLE_TOP_PERIC1 0x033c
60 #define MUX_STAT_TOP0 0x0400
61 #define MUX_STAT_TOP1 0x0404
62 #define MUX_STAT_TOP2 0x0408
63 #define MUX_STAT_TOP3 0x040c
64 #define MUX_STAT_TOP4 0x0410
65 #define MUX_STAT_TOP_MSCL 0x0420
66 #define MUX_STAT_TOP_CAM1 0x0424
67 #define MUX_STAT_TOP_FSYS0 0x0430
68 #define MUX_STAT_TOP_FSYS1 0x0434
69 #define MUX_STAT_TOP_PERIC0 0x0438
70 #define MUX_STAT_TOP_PERIC1 0x043c
71 #define DIV_TOP0 0x0600
72 #define DIV_TOP1 0x0604
73 #define DIV_TOP2 0x0608
74 #define DIV_TOP3 0x060c
75 #define DIV_TOP4 0x0610
76 #define DIV_TOP_MSCL 0x0618
77 #define DIV_TOP_CAM10 0x061c
78 #define DIV_TOP_CAM11 0x0620
79 #define DIV_TOP_FSYS0 0x062c
80 #define DIV_TOP_FSYS1 0x0630
81 #define DIV_TOP_FSYS2 0x0634
82 #define DIV_TOP_PERIC0 0x0638
83 #define DIV_TOP_PERIC1 0x063c
84 #define DIV_TOP_PERIC2 0x0640
85 #define DIV_TOP_PERIC3 0x0644
86 #define DIV_TOP_PERIC4 0x0648
87 #define DIV_TOP_PLL_FREQ_DET 0x064c
88 #define DIV_STAT_TOP0 0x0700
89 #define DIV_STAT_TOP1 0x0704
90 #define DIV_STAT_TOP2 0x0708
91 #define DIV_STAT_TOP3 0x070c
92 #define DIV_STAT_TOP4 0x0710
93 #define DIV_STAT_TOP_MSCL 0x0718
94 #define DIV_STAT_TOP_CAM10 0x071c
95 #define DIV_STAT_TOP_CAM11 0x0720
96 #define DIV_STAT_TOP_FSYS0 0x072c
97 #define DIV_STAT_TOP_FSYS1 0x0730
98 #define DIV_STAT_TOP_FSYS2 0x0734
99 #define DIV_STAT_TOP_PERIC0 0x0738
100 #define DIV_STAT_TOP_PERIC1 0x073c
101 #define DIV_STAT_TOP_PERIC2 0x0740
102 #define DIV_STAT_TOP_PERIC3 0x0744
103 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
104 #define ENABLE_ACLK_TOP 0x0800
105 #define ENABLE_SCLK_TOP 0x0a00
106 #define ENABLE_SCLK_TOP_MSCL 0x0a04
107 #define ENABLE_SCLK_TOP_CAM1 0x0a08
108 #define ENABLE_SCLK_TOP_DISP 0x0a0c
109 #define ENABLE_SCLK_TOP_FSYS 0x0a10
110 #define ENABLE_SCLK_TOP_PERIC 0x0a14
111 #define ENABLE_IP_TOP 0x0b00
112 #define ENABLE_CMU_TOP 0x0c00
113 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04
114
115 static const unsigned long top_clk_regs[] __initconst = {
116 ISP_PLL_LOCK,
117 AUD_PLL_LOCK,
118 ISP_PLL_CON0,
119 ISP_PLL_CON1,
120 ISP_PLL_FREQ_DET,
121 AUD_PLL_CON0,
122 AUD_PLL_CON1,
123 AUD_PLL_CON2,
124 AUD_PLL_FREQ_DET,
125 MUX_SEL_TOP0,
126 MUX_SEL_TOP1,
127 MUX_SEL_TOP2,
128 MUX_SEL_TOP3,
129 MUX_SEL_TOP4,
130 MUX_SEL_TOP_MSCL,
131 MUX_SEL_TOP_CAM1,
132 MUX_SEL_TOP_DISP,
133 MUX_SEL_TOP_FSYS0,
134 MUX_SEL_TOP_FSYS1,
135 MUX_SEL_TOP_PERIC0,
136 MUX_SEL_TOP_PERIC1,
137 MUX_ENABLE_TOP0,
138 MUX_ENABLE_TOP1,
139 MUX_ENABLE_TOP2,
140 MUX_ENABLE_TOP3,
141 MUX_ENABLE_TOP4,
142 MUX_ENABLE_TOP_MSCL,
143 MUX_ENABLE_TOP_CAM1,
144 MUX_ENABLE_TOP_DISP,
145 MUX_ENABLE_TOP_FSYS0,
146 MUX_ENABLE_TOP_FSYS1,
147 MUX_ENABLE_TOP_PERIC0,
148 MUX_ENABLE_TOP_PERIC1,
149 DIV_TOP0,
150 DIV_TOP1,
151 DIV_TOP2,
152 DIV_TOP3,
153 DIV_TOP4,
154 DIV_TOP_MSCL,
155 DIV_TOP_CAM10,
156 DIV_TOP_CAM11,
157 DIV_TOP_FSYS0,
158 DIV_TOP_FSYS1,
159 DIV_TOP_FSYS2,
160 DIV_TOP_PERIC0,
161 DIV_TOP_PERIC1,
162 DIV_TOP_PERIC2,
163 DIV_TOP_PERIC3,
164 DIV_TOP_PERIC4,
165 DIV_TOP_PLL_FREQ_DET,
166 ENABLE_ACLK_TOP,
167 ENABLE_SCLK_TOP,
168 ENABLE_SCLK_TOP_MSCL,
169 ENABLE_SCLK_TOP_CAM1,
170 ENABLE_SCLK_TOP_DISP,
171 ENABLE_SCLK_TOP_FSYS,
172 ENABLE_SCLK_TOP_PERIC,
173 ENABLE_IP_TOP,
174 ENABLE_CMU_TOP,
175 ENABLE_CMU_TOP_DIV_STAT,
176 };
177
178 static const struct samsung_clk_reg_dump top_suspend_regs[] = {
179 /* force all aclk clocks enabled */
180 { ENABLE_ACLK_TOP, 0x67ecffed },
181 /* force all sclk_uart clocks enabled */
182 { ENABLE_SCLK_TOP_PERIC, 0x38 },
183 /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
184 { ISP_PLL_CON0, 0x85cc0502 },
185 /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
186 { AUD_PLL_CON0, 0x84830202 },
187 };
188
189 /* list of all parent clock list */
190 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
191 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
192 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
193 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
194 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
195 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
196 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
197 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
198
199 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
200 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
201 PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
202 "mout_mfc_pll_user", };
203 PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
204
205 PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
206 "mout_mphy_pll_user", };
207 PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
208 "mout_bus_pll_user", };
209 PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
210
211 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
212 "mout_mphy_pll_user", };
213 PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
214 "mout_mphy_pll_user", };
215 PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
216 "mout_mphy_pll_user", };
217
218 PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
219 PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
220
221 PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
222 PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
223 PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
224 PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
225 PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
226
227 PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
228 "oscclk", "ioclk_spdif_extclk", };
229 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
230 "mout_aud_pll_user_t",};
231 PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
232 "mout_aud_pll_user_t",};
233
234 PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
235
236 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
237 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
238 };
239
240 static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
241 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
242 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
243 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
244 /* Xi2s1SDI input clock for SPDIF */
245 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
246 /* XspiCLK[4:0] input clock for SPI */
247 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
248 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
249 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
250 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
251 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
252 /* Xi2s1SCLK input clock for I2S1_BCLK */
253 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
254 };
255
256 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
257 /* MUX_SEL_TOP0 */
258 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
259 4, 1),
260 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
261 0, 1),
262
263 /* MUX_SEL_TOP1 */
264 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
265 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
266 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
267 MUX_SEL_TOP1, 8, 1),
268 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
269 MUX_SEL_TOP1, 4, 1),
270 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
271 MUX_SEL_TOP1, 0, 1),
272
273 /* MUX_SEL_TOP2 */
274 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
275 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
276 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
277 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
278 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
279 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
280 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
281 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
282 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
283 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
284 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
285 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
286
287 /* MUX_SEL_TOP3 */
288 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
289 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
290 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
291 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
292 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
293 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
294 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
295 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
296 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
297 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
298 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
299 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
300
301 /* MUX_SEL_TOP4 */
302 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
303 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
304 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
305 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
306 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
307 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
308
309 /* MUX_SEL_TOP_MSCL */
310 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
311 MUX_SEL_TOP_MSCL, 8, 1),
312 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
313 MUX_SEL_TOP_MSCL, 4, 1),
314 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
315 MUX_SEL_TOP_MSCL, 0, 1),
316
317 /* MUX_SEL_TOP_CAM1 */
318 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
319 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
320 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
321 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
322 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
323 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
324 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
325 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
326 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
327 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
328 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
329 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
330
331 /* MUX_SEL_TOP_FSYS0 */
332 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
333 MUX_SEL_TOP_FSYS0, 28, 1),
334 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
335 MUX_SEL_TOP_FSYS0, 24, 1),
336 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
337 MUX_SEL_TOP_FSYS0, 20, 1),
338 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
339 MUX_SEL_TOP_FSYS0, 16, 1),
340 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
341 MUX_SEL_TOP_FSYS0, 12, 1),
342 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
343 MUX_SEL_TOP_FSYS0, 8, 1),
344 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
345 MUX_SEL_TOP_FSYS0, 4, 1),
346 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
347 MUX_SEL_TOP_FSYS0, 0, 1),
348
349 /* MUX_SEL_TOP_FSYS1 */
350 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
351 MUX_SEL_TOP_FSYS1, 12, 1),
352 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
353 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
354 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
355 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
356 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
357 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
358
359 /* MUX_SEL_TOP_PERIC0 */
360 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
361 MUX_SEL_TOP_PERIC0, 28, 1),
362 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
363 MUX_SEL_TOP_PERIC0, 24, 1),
364 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
365 MUX_SEL_TOP_PERIC0, 20, 1),
366 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
367 MUX_SEL_TOP_PERIC0, 16, 1),
368 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
369 MUX_SEL_TOP_PERIC0, 12, 1),
370 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
371 MUX_SEL_TOP_PERIC0, 8, 1),
372 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
373 MUX_SEL_TOP_PERIC0, 4, 1),
374 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
375 MUX_SEL_TOP_PERIC0, 0, 1),
376
377 /* MUX_SEL_TOP_PERIC1 */
378 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
379 MUX_SEL_TOP_PERIC1, 16, 1),
380 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
381 MUX_SEL_TOP_PERIC1, 12, 2),
382 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
383 MUX_SEL_TOP_PERIC1, 4, 2),
384 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
385 MUX_SEL_TOP_PERIC1, 0, 2),
386
387 /* MUX_SEL_TOP_DISP */
388 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
389 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
390 };
391
392 static const struct samsung_div_clock top_div_clks[] __initconst = {
393 /* DIV_TOP0 */
394 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
395 DIV_TOP0, 28, 3),
396 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
397 DIV_TOP0, 24, 3),
398 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
399 DIV_TOP0, 20, 3),
400 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
401 DIV_TOP0, 16, 3),
402 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
403 DIV_TOP0, 12, 3),
404 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
405 DIV_TOP0, 8, 3),
406 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
407 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
408 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
409 "mout_aclk_isp_400", DIV_TOP0, 0, 4),
410
411 /* DIV_TOP1 */
412 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
413 DIV_TOP1, 28, 3),
414 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
415 DIV_TOP1, 24, 3),
416 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
417 DIV_TOP1, 20, 3),
418 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
419 DIV_TOP1, 12, 3),
420 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
421 DIV_TOP1, 8, 3),
422 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
423 DIV_TOP1, 0, 3),
424
425 /* DIV_TOP2 */
426 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
427 DIV_TOP2, 4, 3),
428 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
429 DIV_TOP2, 0, 3),
430
431 /* DIV_TOP3 */
432 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
433 "mout_bus_pll_user", DIV_TOP3, 24, 3),
434 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
435 "mout_bus_pll_user", DIV_TOP3, 20, 3),
436 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
437 "mout_bus_pll_user", DIV_TOP3, 16, 3),
438 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
439 "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
440 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
441 "mout_bus_pll_user", DIV_TOP3, 8, 3),
442 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
443 "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
444 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
445 "mout_bus_pll_user", DIV_TOP3, 0, 3),
446
447 /* DIV_TOP4 */
448 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
449 DIV_TOP4, 8, 3),
450 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
451 DIV_TOP4, 4, 3),
452 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
453 DIV_TOP4, 0, 3),
454
455 /* DIV_TOP_MSCL */
456 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
457 DIV_TOP_MSCL, 0, 4),
458
459 /* DIV_TOP_CAM10 */
460 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
461 DIV_TOP_CAM10, 24, 5),
462 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
463 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
464 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
465 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
466 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
467 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
468 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
469 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
470
471 /* DIV_TOP_CAM11 */
472 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
473 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
474 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
475 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
476 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
477 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
478 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
479 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
480 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
481 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4),
482 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
483 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
484
485 /* DIV_TOP_FSYS0 */
486 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
487 DIV_TOP_FSYS0, 16, 8),
488 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
489 DIV_TOP_FSYS0, 12, 4),
490 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
491 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
492 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
493 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
494
495 /* DIV_TOP_FSYS1 */
496 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
497 DIV_TOP_FSYS1, 4, 8),
498 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
499 DIV_TOP_FSYS1, 0, 4),
500
501 /* DIV_TOP_FSYS2 */
502 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
503 DIV_TOP_FSYS2, 12, 3),
504 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
505 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
506 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
507 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
508 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
509 DIV_TOP_FSYS2, 0, 4),
510
511 /* DIV_TOP_PERIC0 */
512 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
513 DIV_TOP_PERIC0, 16, 8),
514 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
515 DIV_TOP_PERIC0, 12, 4),
516 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
517 DIV_TOP_PERIC0, 4, 8),
518 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
519 DIV_TOP_PERIC0, 0, 4),
520
521 /* DIV_TOP_PERIC1 */
522 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
523 DIV_TOP_PERIC1, 4, 8),
524 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
525 DIV_TOP_PERIC1, 0, 4),
526
527 /* DIV_TOP_PERIC2 */
528 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
529 DIV_TOP_PERIC2, 8, 4),
530 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
531 DIV_TOP_PERIC2, 4, 4),
532 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
533 DIV_TOP_PERIC2, 0, 4),
534
535 /* DIV_TOP_PERIC3 */
536 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
537 DIV_TOP_PERIC3, 16, 6),
538 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
539 DIV_TOP_PERIC3, 8, 8),
540 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
541 DIV_TOP_PERIC3, 4, 4),
542 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
543 DIV_TOP_PERIC3, 0, 4),
544
545 /* DIV_TOP_PERIC4 */
546 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
547 DIV_TOP_PERIC4, 16, 8),
548 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
549 DIV_TOP_PERIC4, 12, 4),
550 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
551 DIV_TOP_PERIC4, 4, 8),
552 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
553 DIV_TOP_PERIC4, 0, 4),
554 };
555
556 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
557 /* ENABLE_ACLK_TOP */
558 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
559 ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
560 GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266",
561 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
562 29, CLK_IGNORE_UNUSED, 0),
563 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
564 ENABLE_ACLK_TOP, 26,
565 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
566 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
567 ENABLE_ACLK_TOP, 25,
568 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
569 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200",
570 ENABLE_ACLK_TOP, 24,
571 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
572 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266",
573 ENABLE_ACLK_TOP, 23,
574 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
575 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
576 ENABLE_ACLK_TOP, 22,
577 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
578 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
579 ENABLE_ACLK_TOP, 21,
580 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
581 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
582 ENABLE_ACLK_TOP, 19,
583 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
584 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
585 ENABLE_ACLK_TOP, 18,
586 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
587 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
588 ENABLE_ACLK_TOP, 15,
589 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
590 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
591 ENABLE_ACLK_TOP, 14,
592 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
593 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
594 ENABLE_ACLK_TOP, 13,
595 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
596 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
597 ENABLE_ACLK_TOP, 12,
598 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
599 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
600 ENABLE_ACLK_TOP, 11,
601 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
602 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
603 ENABLE_ACLK_TOP, 10,
604 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
605 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
606 ENABLE_ACLK_TOP, 9,
607 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
608 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
609 ENABLE_ACLK_TOP, 8,
610 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
611 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
612 ENABLE_ACLK_TOP, 7,
613 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
614 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
615 ENABLE_ACLK_TOP, 6,
616 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
617 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
618 ENABLE_ACLK_TOP, 5,
619 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
620 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
621 ENABLE_ACLK_TOP, 3,
622 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
623 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
624 ENABLE_ACLK_TOP, 2,
625 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
626 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
627 ENABLE_ACLK_TOP, 0,
628 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
629
630 /* ENABLE_SCLK_TOP_MSCL */
631 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
632 ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0),
633
634 /* ENABLE_SCLK_TOP_CAM1 */
635 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
636 ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
637 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
638 ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
639 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
640 ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
641 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
642 ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
643 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
644 ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
645 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
646 ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
647 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
648 ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
649
650 /* ENABLE_SCLK_TOP_DISP */
651 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
652 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
653 CLK_IGNORE_UNUSED, 0),
654
655 /* ENABLE_SCLK_TOP_FSYS */
656 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
657 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
658 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
659 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
660 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
661 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
662 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
663 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
664 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
665 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
666 3, CLK_SET_RATE_PARENT, 0),
667 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
668 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
669 1, CLK_SET_RATE_PARENT, 0),
670 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
671 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
672 0, CLK_SET_RATE_PARENT, 0),
673
674 /* ENABLE_SCLK_TOP_PERIC */
675 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
676 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
677 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
678 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
679 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
680 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
681 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
682 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
683 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
684 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
685 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
686 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
687 CLK_IGNORE_UNUSED, 0),
688 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
689 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
690 CLK_IGNORE_UNUSED, 0),
691 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
692 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
693 CLK_IGNORE_UNUSED, 0),
694 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
695 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
696 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
697 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
698 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
699 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
700
701 /* MUX_ENABLE_TOP_PERIC1 */
702 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
703 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
704 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
705 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
706 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
707 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
708 };
709
710 /*
711 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
712 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
713 */
714 static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {
715 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
716 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
717 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
718 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
719 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
720 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
721 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
722 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
723 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
724 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
725 PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4, 0),
726 PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6, 0),
727 PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4, 0),
728 PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6, 0),
729 PLL_35XX_RATE(24 * MHZ, 1200000000U, 500, 5, 1),
730 PLL_35XX_RATE(24 * MHZ, 1100000000U, 550, 6, 1),
731 PLL_35XX_RATE(24 * MHZ, 1086000000U, 362, 4, 1),
732 PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 6, 1),
733 PLL_35XX_RATE(24 * MHZ, 1000000000U, 500, 6, 1),
734 PLL_35XX_RATE(24 * MHZ, 933000000U, 311, 4, 1),
735 PLL_35XX_RATE(24 * MHZ, 921000000U, 307, 4, 1),
736 PLL_35XX_RATE(24 * MHZ, 900000000U, 375, 5, 1),
737 PLL_35XX_RATE(24 * MHZ, 825000000U, 275, 4, 1),
738 PLL_35XX_RATE(24 * MHZ, 800000000U, 400, 6, 1),
739 PLL_35XX_RATE(24 * MHZ, 733000000U, 733, 12, 1),
740 PLL_35XX_RATE(24 * MHZ, 700000000U, 175, 3, 1),
741 PLL_35XX_RATE(24 * MHZ, 666000000U, 222, 4, 1),
742 PLL_35XX_RATE(24 * MHZ, 633000000U, 211, 4, 1),
743 PLL_35XX_RATE(24 * MHZ, 600000000U, 500, 5, 2),
744 PLL_35XX_RATE(24 * MHZ, 552000000U, 460, 5, 2),
745 PLL_35XX_RATE(24 * MHZ, 550000000U, 550, 6, 2),
746 PLL_35XX_RATE(24 * MHZ, 543000000U, 362, 4, 2),
747 PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2),
748 PLL_35XX_RATE(24 * MHZ, 500000000U, 500, 6, 2),
749 PLL_35XX_RATE(24 * MHZ, 444000000U, 370, 5, 2),
750 PLL_35XX_RATE(24 * MHZ, 420000000U, 350, 5, 2),
751 PLL_35XX_RATE(24 * MHZ, 400000000U, 400, 6, 2),
752 PLL_35XX_RATE(24 * MHZ, 350000000U, 350, 6, 2),
753 PLL_35XX_RATE(24 * MHZ, 333000000U, 222, 4, 2),
754 PLL_35XX_RATE(24 * MHZ, 300000000U, 500, 5, 3),
755 PLL_35XX_RATE(24 * MHZ, 278000000U, 556, 6, 3),
756 PLL_35XX_RATE(24 * MHZ, 266000000U, 532, 6, 3),
757 PLL_35XX_RATE(24 * MHZ, 250000000U, 500, 6, 3),
758 PLL_35XX_RATE(24 * MHZ, 200000000U, 400, 6, 3),
759 PLL_35XX_RATE(24 * MHZ, 166000000U, 332, 6, 3),
760 PLL_35XX_RATE(24 * MHZ, 160000000U, 320, 6, 3),
761 PLL_35XX_RATE(24 * MHZ, 133000000U, 532, 6, 4),
762 PLL_35XX_RATE(24 * MHZ, 100000000U, 400, 6, 4),
763 { /* sentinel */ }
764 };
765
766 /* AUD_PLL */
767 static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {
768 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
769 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
770 PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0),
771 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
772 PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
773 PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816),
774 PLL_36XX_RATE(24 * MHZ, 294912002U, 98, 1, 3, 19923),
775 PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0),
776 PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0),
777 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
778 { /* sentinel */ }
779 };
780
781 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
782 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
783 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates),
784 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
785 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates),
786 };
787
788 static const struct samsung_cmu_info top_cmu_info __initconst = {
789 .pll_clks = top_pll_clks,
790 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
791 .mux_clks = top_mux_clks,
792 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
793 .div_clks = top_div_clks,
794 .nr_div_clks = ARRAY_SIZE(top_div_clks),
795 .gate_clks = top_gate_clks,
796 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
797 .fixed_clks = top_fixed_clks,
798 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
799 .fixed_factor_clks = top_fixed_factor_clks,
800 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
801 .nr_clk_ids = TOP_NR_CLK,
802 .clk_regs = top_clk_regs,
803 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
804 .suspend_regs = top_suspend_regs,
805 .nr_suspend_regs = ARRAY_SIZE(top_suspend_regs),
806 };
807
808 static void __init exynos5433_cmu_top_init(struct device_node *np)
809 {
810 samsung_cmu_register_one(np, &top_cmu_info);
811 }
812 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
813 exynos5433_cmu_top_init);
814
815 /*
816 * Register offset definitions for CMU_CPIF
817 */
818 #define MPHY_PLL_LOCK 0x0000
819 #define MPHY_PLL_CON0 0x0100
820 #define MPHY_PLL_CON1 0x0104
821 #define MPHY_PLL_FREQ_DET 0x010c
822 #define MUX_SEL_CPIF0 0x0200
823 #define DIV_CPIF 0x0600
824 #define ENABLE_SCLK_CPIF 0x0a00
825
826 static const unsigned long cpif_clk_regs[] __initconst = {
827 MPHY_PLL_LOCK,
828 MPHY_PLL_CON0,
829 MPHY_PLL_CON1,
830 MPHY_PLL_FREQ_DET,
831 MUX_SEL_CPIF0,
832 DIV_CPIF,
833 ENABLE_SCLK_CPIF,
834 };
835
836 static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {
837 /* force all sclk clocks enabled */
838 { ENABLE_SCLK_CPIF, 0x3ff },
839 /* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */
840 { MPHY_PLL_CON0, 0x81c70601 },
841 };
842
843 /* list of all parent clock list */
844 PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
845
846 static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
847 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
848 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates),
849 };
850
851 static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
852 /* MUX_SEL_CPIF0 */
853 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
854 0, 1),
855 };
856
857 static const struct samsung_div_clock cpif_div_clks[] __initconst = {
858 /* DIV_CPIF */
859 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
860 0, 6),
861 };
862
863 static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
864 /* ENABLE_SCLK_CPIF */
865 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
866 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
867 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
868 ENABLE_SCLK_CPIF, 4, 0, 0),
869 };
870
871 static const struct samsung_cmu_info cpif_cmu_info __initconst = {
872 .pll_clks = cpif_pll_clks,
873 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
874 .mux_clks = cpif_mux_clks,
875 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
876 .div_clks = cpif_div_clks,
877 .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
878 .gate_clks = cpif_gate_clks,
879 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
880 .nr_clk_ids = CPIF_NR_CLK,
881 .clk_regs = cpif_clk_regs,
882 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
883 .suspend_regs = cpif_suspend_regs,
884 .nr_suspend_regs = ARRAY_SIZE(cpif_suspend_regs),
885 };
886
887 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
888 {
889 samsung_cmu_register_one(np, &cpif_cmu_info);
890 }
891 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
892 exynos5433_cmu_cpif_init);
893
894 /*
895 * Register offset definitions for CMU_MIF
896 */
897 #define MEM0_PLL_LOCK 0x0000
898 #define MEM1_PLL_LOCK 0x0004
899 #define BUS_PLL_LOCK 0x0008
900 #define MFC_PLL_LOCK 0x000c
901 #define MEM0_PLL_CON0 0x0100
902 #define MEM0_PLL_CON1 0x0104
903 #define MEM0_PLL_FREQ_DET 0x010c
904 #define MEM1_PLL_CON0 0x0110
905 #define MEM1_PLL_CON1 0x0114
906 #define MEM1_PLL_FREQ_DET 0x011c
907 #define BUS_PLL_CON0 0x0120
908 #define BUS_PLL_CON1 0x0124
909 #define BUS_PLL_FREQ_DET 0x012c
910 #define MFC_PLL_CON0 0x0130
911 #define MFC_PLL_CON1 0x0134
912 #define MFC_PLL_FREQ_DET 0x013c
913 #define MUX_SEL_MIF0 0x0200
914 #define MUX_SEL_MIF1 0x0204
915 #define MUX_SEL_MIF2 0x0208
916 #define MUX_SEL_MIF3 0x020c
917 #define MUX_SEL_MIF4 0x0210
918 #define MUX_SEL_MIF5 0x0214
919 #define MUX_SEL_MIF6 0x0218
920 #define MUX_SEL_MIF7 0x021c
921 #define MUX_ENABLE_MIF0 0x0300
922 #define MUX_ENABLE_MIF1 0x0304
923 #define MUX_ENABLE_MIF2 0x0308
924 #define MUX_ENABLE_MIF3 0x030c
925 #define MUX_ENABLE_MIF4 0x0310
926 #define MUX_ENABLE_MIF5 0x0314
927 #define MUX_ENABLE_MIF6 0x0318
928 #define MUX_ENABLE_MIF7 0x031c
929 #define MUX_STAT_MIF0 0x0400
930 #define MUX_STAT_MIF1 0x0404
931 #define MUX_STAT_MIF2 0x0408
932 #define MUX_STAT_MIF3 0x040c
933 #define MUX_STAT_MIF4 0x0410
934 #define MUX_STAT_MIF5 0x0414
935 #define MUX_STAT_MIF6 0x0418
936 #define MUX_STAT_MIF7 0x041c
937 #define DIV_MIF1 0x0604
938 #define DIV_MIF2 0x0608
939 #define DIV_MIF3 0x060c
940 #define DIV_MIF4 0x0610
941 #define DIV_MIF5 0x0614
942 #define DIV_MIF_PLL_FREQ_DET 0x0618
943 #define DIV_STAT_MIF1 0x0704
944 #define DIV_STAT_MIF2 0x0708
945 #define DIV_STAT_MIF3 0x070c
946 #define DIV_STAT_MIF4 0x0710
947 #define DIV_STAT_MIF5 0x0714
948 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
949 #define ENABLE_ACLK_MIF0 0x0800
950 #define ENABLE_ACLK_MIF1 0x0804
951 #define ENABLE_ACLK_MIF2 0x0808
952 #define ENABLE_ACLK_MIF3 0x080c
953 #define ENABLE_PCLK_MIF 0x0900
954 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
955 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
956 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
957 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
958 #define ENABLE_SCLK_MIF 0x0a00
959 #define ENABLE_IP_MIF0 0x0b00
960 #define ENABLE_IP_MIF1 0x0b04
961 #define ENABLE_IP_MIF2 0x0b08
962 #define ENABLE_IP_MIF3 0x0b0c
963 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
964 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
965 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
966 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
967 #define CLKOUT_CMU_MIF 0x0c00
968 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
969 #define DREX_FREQ_CTRL0 0x1000
970 #define DREX_FREQ_CTRL1 0x1004
971 #define PAUSE 0x1008
972 #define DDRPHY_LOCK_CTRL 0x100c
973
974 static const unsigned long mif_clk_regs[] __initconst = {
975 MEM0_PLL_LOCK,
976 MEM1_PLL_LOCK,
977 BUS_PLL_LOCK,
978 MFC_PLL_LOCK,
979 MEM0_PLL_CON0,
980 MEM0_PLL_CON1,
981 MEM0_PLL_FREQ_DET,
982 MEM1_PLL_CON0,
983 MEM1_PLL_CON1,
984 MEM1_PLL_FREQ_DET,
985 BUS_PLL_CON0,
986 BUS_PLL_CON1,
987 BUS_PLL_FREQ_DET,
988 MFC_PLL_CON0,
989 MFC_PLL_CON1,
990 MFC_PLL_FREQ_DET,
991 MUX_SEL_MIF0,
992 MUX_SEL_MIF1,
993 MUX_SEL_MIF2,
994 MUX_SEL_MIF3,
995 MUX_SEL_MIF4,
996 MUX_SEL_MIF5,
997 MUX_SEL_MIF6,
998 MUX_SEL_MIF7,
999 MUX_ENABLE_MIF0,
1000 MUX_ENABLE_MIF1,
1001 MUX_ENABLE_MIF2,
1002 MUX_ENABLE_MIF3,
1003 MUX_ENABLE_MIF4,
1004 MUX_ENABLE_MIF5,
1005 MUX_ENABLE_MIF6,
1006 MUX_ENABLE_MIF7,
1007 DIV_MIF1,
1008 DIV_MIF2,
1009 DIV_MIF3,
1010 DIV_MIF4,
1011 DIV_MIF5,
1012 DIV_MIF_PLL_FREQ_DET,
1013 ENABLE_ACLK_MIF0,
1014 ENABLE_ACLK_MIF1,
1015 ENABLE_ACLK_MIF2,
1016 ENABLE_ACLK_MIF3,
1017 ENABLE_PCLK_MIF,
1018 ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
1019 ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
1020 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
1021 ENABLE_PCLK_MIF_SECURE_RTC,
1022 ENABLE_SCLK_MIF,
1023 ENABLE_IP_MIF0,
1024 ENABLE_IP_MIF1,
1025 ENABLE_IP_MIF2,
1026 ENABLE_IP_MIF3,
1027 ENABLE_IP_MIF_SECURE_DREX0_TZ,
1028 ENABLE_IP_MIF_SECURE_DREX1_TZ,
1029 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
1030 ENABLE_IP_MIF_SECURE_RTC,
1031 CLKOUT_CMU_MIF,
1032 CLKOUT_CMU_MIF_DIV_STAT,
1033 DREX_FREQ_CTRL0,
1034 DREX_FREQ_CTRL1,
1035 PAUSE,
1036 DDRPHY_LOCK_CTRL,
1037 };
1038
1039 static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1040 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1041 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates),
1042 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1043 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates),
1044 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1045 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates),
1046 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
1047 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates),
1048 };
1049
1050 /* list of all parent clock list */
1051 PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
1052 PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
1053 PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
1054 PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
1055 PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
1056 PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
1057 PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
1058 PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
1059
1060 PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1061 PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1062 PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1063 PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1064
1065 PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
1066 PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1067
1068 PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
1069 "mout_bus_pll_div2", };
1070 PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1071
1072 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
1073 "sclk_mphy_pll", };
1074 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
1075 "mout_mfc_pll_div2", };
1076 PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
1077 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
1078 "sclk_mphy_pll", };
1079 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1080 "mout_mfc_pll_div2", };
1081
1082 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1083 "sclk_mphy_pll", };
1084 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1085 "mout_mfc_pll_div2", };
1086 PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1087 PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1088 PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
1089
1090 PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1091 PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1092
1093 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1094 "sclk_mphy_pll", };
1095 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1096 "mout_mfc_pll_div2", };
1097 PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1098 PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1099
1100 static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
1101 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1102 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1103 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1104 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1105 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1106 };
1107
1108 static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1109 /* MUX_SEL_MIF0 */
1110 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1111 MUX_SEL_MIF0, 28, 1),
1112 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1113 MUX_SEL_MIF0, 24, 1),
1114 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1115 MUX_SEL_MIF0, 20, 1),
1116 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1117 MUX_SEL_MIF0, 16, 1),
1118 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1119 12, 1),
1120 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1121 8, 1),
1122 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1123 4, 1),
1124 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1125 0, 1),
1126
1127 /* MUX_SEL_MIF1 */
1128 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1129 MUX_SEL_MIF1, 24, 1),
1130 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1131 MUX_SEL_MIF1, 20, 1),
1132 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1133 MUX_SEL_MIF1, 16, 1),
1134 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1135 MUX_SEL_MIF1, 12, 1),
1136 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1137 MUX_SEL_MIF1, 8, 1),
1138 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1139 MUX_SEL_MIF1, 4, 1),
1140
1141 /* MUX_SEL_MIF2 */
1142 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1143 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1144 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1145 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1146
1147 /* MUX_SEL_MIF3 */
1148 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1149 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1150 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1151 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1152
1153 /* MUX_SEL_MIF4 */
1154 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1155 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1156 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1157 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1158 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1159 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1160 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1161 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1162 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1163 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1164 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1165 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1166
1167 /* MUX_SEL_MIF5 */
1168 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1169 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1170 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1171 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1172 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1173 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1174 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1175 MUX_SEL_MIF5, 8, 1),
1176 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1177 MUX_SEL_MIF5, 4, 1),
1178 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1179 MUX_SEL_MIF5, 0, 1),
1180
1181 /* MUX_SEL_MIF6 */
1182 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1183 MUX_SEL_MIF6, 8, 1),
1184 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1185 MUX_SEL_MIF6, 4, 1),
1186 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1187 MUX_SEL_MIF6, 0, 1),
1188
1189 /* MUX_SEL_MIF7 */
1190 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1191 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1192 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1193 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1194 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1195 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1196 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1197 MUX_SEL_MIF7, 8, 1),
1198 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1199 MUX_SEL_MIF7, 4, 1),
1200 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1201 MUX_SEL_MIF7, 0, 1),
1202 };
1203
1204 static const struct samsung_div_clock mif_div_clks[] __initconst = {
1205 /* DIV_MIF1 */
1206 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1207 DIV_MIF1, 16, 2),
1208 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1209 12, 2),
1210 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1211 8, 2),
1212 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1213 4, 4),
1214
1215 /* DIV_MIF2 */
1216 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1217 DIV_MIF2, 20, 3),
1218 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1219 DIV_MIF2, 16, 4),
1220 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1221 DIV_MIF2, 12, 4),
1222 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1223 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1224 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1225 DIV_MIF2, 4, 2),
1226 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1227 DIV_MIF2, 0, 3),
1228
1229 /* DIV_MIF3 */
1230 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1231 DIV_MIF3, 16, 4),
1232 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1233 DIV_MIF3, 4, 3),
1234 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1235 DIV_MIF3, 0, 3),
1236
1237 /* DIV_MIF4 */
1238 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1239 DIV_MIF4, 24, 4),
1240 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1241 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1242 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1243 DIV_MIF4, 16, 4),
1244 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1245 DIV_MIF4, 12, 4),
1246 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1247 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1248 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1249 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1250 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1251 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1252
1253 /* DIV_MIF5 */
1254 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1255 0, 3),
1256 };
1257
1258 static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1259 /* ENABLE_ACLK_MIF0 */
1260 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1261 19, CLK_IGNORE_UNUSED, 0),
1262 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1263 18, CLK_IGNORE_UNUSED, 0),
1264 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1265 17, CLK_IGNORE_UNUSED, 0),
1266 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1267 16, CLK_IGNORE_UNUSED, 0),
1268 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1269 15, CLK_IGNORE_UNUSED, 0),
1270 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1271 14, CLK_IGNORE_UNUSED, 0),
1272 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1273 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1274 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1275 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1276 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1277 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1278 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1279 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1280 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1281 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1282 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1283 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1284 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1285 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1286 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1287 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1288 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1289 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1290 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1291 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1292 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1293 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1294 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1295 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1296 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1297 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1298 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1299 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1300
1301 /* ENABLE_ACLK_MIF1 */
1302 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1303 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1304 CLK_IGNORE_UNUSED, 0),
1305 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1306 "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1307 27, CLK_IGNORE_UNUSED, 0),
1308 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1309 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1310 26, CLK_IGNORE_UNUSED, 0),
1311 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1312 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1313 25, CLK_IGNORE_UNUSED, 0),
1314 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1315 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1316 24, CLK_IGNORE_UNUSED, 0),
1317 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1318 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1319 23, CLK_IGNORE_UNUSED, 0),
1320 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1321 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1322 22, CLK_IGNORE_UNUSED, 0),
1323 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1324 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1325 21, CLK_IGNORE_UNUSED, 0),
1326 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1327 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1328 20, CLK_IGNORE_UNUSED, 0),
1329 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1330 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1331 19, CLK_IGNORE_UNUSED, 0),
1332 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1333 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1334 18, CLK_IGNORE_UNUSED, 0),
1335 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1336 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1337 17, CLK_IGNORE_UNUSED, 0),
1338 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1339 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1340 16, CLK_IGNORE_UNUSED, 0),
1341 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1342 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1343 15, CLK_IGNORE_UNUSED, 0),
1344 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1345 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1346 14, CLK_IGNORE_UNUSED, 0),
1347 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1348 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1349 13, CLK_IGNORE_UNUSED, 0),
1350 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1351 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1352 12, CLK_IGNORE_UNUSED, 0),
1353 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1354 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1355 11, CLK_IGNORE_UNUSED, 0),
1356 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1357 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1358 10, CLK_IGNORE_UNUSED, 0),
1359 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1360 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1361 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1362 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1363 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1364 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1365 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1366 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1367 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1368 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1369 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1370 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1371 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1372 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1373 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1374 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1375 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1376 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1377 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1378 0, CLK_IGNORE_UNUSED, 0),
1379
1380 /* ENABLE_ACLK_MIF2 */
1381 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1382 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1383 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1384 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1385 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1386 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1387 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1388 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1389 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1390 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1391 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1392 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1393 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1394 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1395 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1396 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1397 CLK_IGNORE_UNUSED, 0),
1398 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1399 "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1400 5, CLK_IGNORE_UNUSED, 0),
1401 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1402 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1403 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1404 "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1405 3, CLK_IGNORE_UNUSED, 0),
1406 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1407 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1408
1409 /* ENABLE_ACLK_MIF3 */
1410 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1411 ENABLE_ACLK_MIF3, 4,
1412 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1413 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1414 ENABLE_ACLK_MIF3, 1,
1415 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1416 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1417 ENABLE_ACLK_MIF3, 0,
1418 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1419
1420 /* ENABLE_PCLK_MIF */
1421 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1422 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1423 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1424 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1425 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1426 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1427 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1428 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1429 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1430 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1431 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1432 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1433 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1434 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1435 CLK_IGNORE_UNUSED, 0),
1436 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1437 ENABLE_PCLK_MIF, 19, 0, 0),
1438 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1439 ENABLE_PCLK_MIF, 18, 0, 0),
1440 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1441 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1442 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1443 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1444 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1445 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1446 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1447 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1448 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1449 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1450 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1451 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1452 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1453 ENABLE_PCLK_MIF, 11, 0, 0),
1454 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1455 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1456 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1457 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1458 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1459 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1460 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1461 ENABLE_PCLK_MIF, 7, 0, 0),
1462 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1463 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1464 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1465 ENABLE_PCLK_MIF, 5, 0, 0),
1466 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1467 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1468 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1469 ENABLE_PCLK_MIF, 2, 0, 0),
1470 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1471 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1472
1473 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1474 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1475 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
1476 CLK_IGNORE_UNUSED, 0),
1477
1478 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1479 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1480 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
1481 CLK_IGNORE_UNUSED, 0),
1482
1483 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1484 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1485 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1486
1487 /* ENABLE_PCLK_MIF_SECURE_RTC */
1488 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1489 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1490
1491 /* ENABLE_SCLK_MIF */
1492 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1493 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1494 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1495 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1496 14, CLK_IGNORE_UNUSED, 0),
1497 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1498 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1499 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1500 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1501 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1502 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1503 7, CLK_IGNORE_UNUSED, 0),
1504 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1505 "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1506 6, CLK_IGNORE_UNUSED, 0),
1507 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1508 "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1509 5, CLK_IGNORE_UNUSED, 0),
1510 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1511 ENABLE_SCLK_MIF, 4,
1512 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1513 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1514 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1515 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1516 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1517 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1518 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1519 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1520 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1521 };
1522
1523 static const struct samsung_cmu_info mif_cmu_info __initconst = {
1524 .pll_clks = mif_pll_clks,
1525 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1526 .mux_clks = mif_mux_clks,
1527 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1528 .div_clks = mif_div_clks,
1529 .nr_div_clks = ARRAY_SIZE(mif_div_clks),
1530 .gate_clks = mif_gate_clks,
1531 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
1532 .fixed_factor_clks = mif_fixed_factor_clks,
1533 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
1534 .nr_clk_ids = MIF_NR_CLK,
1535 .clk_regs = mif_clk_regs,
1536 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
1537 };
1538
1539 static void __init exynos5433_cmu_mif_init(struct device_node *np)
1540 {
1541 samsung_cmu_register_one(np, &mif_cmu_info);
1542 }
1543 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1544 exynos5433_cmu_mif_init);
1545
1546 /*
1547 * Register offset definitions for CMU_PERIC
1548 */
1549 #define DIV_PERIC 0x0600
1550 #define DIV_STAT_PERIC 0x0700
1551 #define ENABLE_ACLK_PERIC 0x0800
1552 #define ENABLE_PCLK_PERIC0 0x0900
1553 #define ENABLE_PCLK_PERIC1 0x0904
1554 #define ENABLE_SCLK_PERIC 0x0A00
1555 #define ENABLE_IP_PERIC0 0x0B00
1556 #define ENABLE_IP_PERIC1 0x0B04
1557 #define ENABLE_IP_PERIC2 0x0B08
1558
1559 static const unsigned long peric_clk_regs[] __initconst = {
1560 DIV_PERIC,
1561 ENABLE_ACLK_PERIC,
1562 ENABLE_PCLK_PERIC0,
1563 ENABLE_PCLK_PERIC1,
1564 ENABLE_SCLK_PERIC,
1565 ENABLE_IP_PERIC0,
1566 ENABLE_IP_PERIC1,
1567 ENABLE_IP_PERIC2,
1568 };
1569
1570 static const struct samsung_clk_reg_dump peric_suspend_regs[] = {
1571 /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
1572 { ENABLE_PCLK_PERIC0, 0xe00ff000 },
1573 /* sclk: uart2-0 */
1574 { ENABLE_SCLK_PERIC, 0x7 },
1575 };
1576
1577 static const struct samsung_div_clock peric_div_clks[] __initconst = {
1578 /* DIV_PERIC */
1579 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1580 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1581 };
1582
1583 static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
1584 /* ENABLE_ACLK_PERIC */
1585 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1586 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1587 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1588 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1589 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1590 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1591 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1592 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1593
1594 /* ENABLE_PCLK_PERIC0 */
1595 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1596 31, CLK_SET_RATE_PARENT, 0),
1597 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1598 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1599 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1600 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1601 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1602 28, CLK_SET_RATE_PARENT, 0),
1603 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1604 26, CLK_SET_RATE_PARENT, 0),
1605 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1606 25, CLK_SET_RATE_PARENT, 0),
1607 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1608 24, CLK_SET_RATE_PARENT, 0),
1609 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1610 23, CLK_SET_RATE_PARENT, 0),
1611 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1612 22, CLK_SET_RATE_PARENT, 0),
1613 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1614 21, CLK_SET_RATE_PARENT, 0),
1615 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1616 20, CLK_SET_RATE_PARENT, 0),
1617 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1618 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1619 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1620 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1621 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1622 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1623 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1624 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1625 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1626 ENABLE_PCLK_PERIC0, 15,
1627 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1628 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1629 14, CLK_SET_RATE_PARENT, 0),
1630 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1631 13, CLK_SET_RATE_PARENT, 0),
1632 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1633 12, CLK_SET_RATE_PARENT, 0),
1634 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1635 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1636 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1637 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1638 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1639 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1640 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1641 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1642 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1643 7, CLK_SET_RATE_PARENT, 0),
1644 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1645 6, CLK_SET_RATE_PARENT, 0),
1646 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1647 5, CLK_SET_RATE_PARENT, 0),
1648 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1649 4, CLK_SET_RATE_PARENT, 0),
1650 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1651 3, CLK_SET_RATE_PARENT, 0),
1652 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1653 2, CLK_SET_RATE_PARENT, 0),
1654 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1655 1, CLK_SET_RATE_PARENT, 0),
1656 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1657 0, CLK_SET_RATE_PARENT, 0),
1658
1659 /* ENABLE_PCLK_PERIC1 */
1660 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1661 9, CLK_SET_RATE_PARENT, 0),
1662 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1663 8, CLK_SET_RATE_PARENT, 0),
1664 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1665 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1666 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1667 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1668 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1669 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1670 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1671 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1672 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1673 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1674 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1675 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1676 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1677 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1678 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1679 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1680
1681 /* ENABLE_SCLK_PERIC */
1682 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1683 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1684 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1685 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1686 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1687 19, CLK_SET_RATE_PARENT, 0),
1688 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1689 18, CLK_SET_RATE_PARENT, 0),
1690 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1691 17, 0, 0),
1692 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1693 16, 0, 0),
1694 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1695 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1696 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1697 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1698 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1699 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1700 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1701 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1702 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1703 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1704 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1705 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1706 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1707 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1708 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1709 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1710 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1711 5, CLK_SET_RATE_PARENT, 0),
1712 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1713 4, CLK_SET_RATE_PARENT, 0),
1714 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1715 3, CLK_SET_RATE_PARENT, 0),
1716 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1717 ENABLE_SCLK_PERIC, 2,
1718 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1719 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1720 ENABLE_SCLK_PERIC, 1,
1721 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1722 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1723 ENABLE_SCLK_PERIC, 0,
1724 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1725 };
1726
1727 static const struct samsung_cmu_info peric_cmu_info __initconst = {
1728 .div_clks = peric_div_clks,
1729 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
1730 .gate_clks = peric_gate_clks,
1731 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
1732 .nr_clk_ids = PERIC_NR_CLK,
1733 .clk_regs = peric_clk_regs,
1734 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
1735 .suspend_regs = peric_suspend_regs,
1736 .nr_suspend_regs = ARRAY_SIZE(peric_suspend_regs),
1737 };
1738
1739 static void __init exynos5433_cmu_peric_init(struct device_node *np)
1740 {
1741 samsung_cmu_register_one(np, &peric_cmu_info);
1742 }
1743
1744 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1745 exynos5433_cmu_peric_init);
1746
1747 /*
1748 * Register offset definitions for CMU_PERIS
1749 */
1750 #define ENABLE_ACLK_PERIS 0x0800
1751 #define ENABLE_PCLK_PERIS 0x0900
1752 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1753 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1754 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1755 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1756 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1757 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1758 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1759 #define ENABLE_SCLK_PERIS 0x0a00
1760 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1761 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1762 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1763 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1764 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1765 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1766 #define ENABLE_IP_PERIS0 0x0b00
1767 #define ENABLE_IP_PERIS1 0x0b04
1768 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1769 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1770 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1771 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1772 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1773 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1774 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1775
1776 static const unsigned long peris_clk_regs[] __initconst = {
1777 ENABLE_ACLK_PERIS,
1778 ENABLE_PCLK_PERIS,
1779 ENABLE_PCLK_PERIS_SECURE_TZPC,
1780 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1781 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1782 ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1783 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1784 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1785 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1786 ENABLE_SCLK_PERIS,
1787 ENABLE_SCLK_PERIS_SECURE_SECKEY,
1788 ENABLE_SCLK_PERIS_SECURE_CHIPID,
1789 ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1790 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1791 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1792 ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1793 ENABLE_IP_PERIS0,
1794 ENABLE_IP_PERIS1,
1795 ENABLE_IP_PERIS_SECURE_TZPC,
1796 ENABLE_IP_PERIS_SECURE_SECKEY,
1797 ENABLE_IP_PERIS_SECURE_CHIPID,
1798 ENABLE_IP_PERIS_SECURE_TOPRTC,
1799 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1800 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1801 ENABLE_IP_PERIS_SECURE_OTP_CON,
1802 };
1803
1804 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1805 /* ENABLE_ACLK_PERIS */
1806 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1807 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1808 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1809 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1810 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1811 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1812
1813 /* ENABLE_PCLK_PERIS */
1814 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1815 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1816 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1817 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1818 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1819 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1820 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1821 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1822 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1823 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1824 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1825 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1826 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1827 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1828 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1829 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1830 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1831 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1832 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1833 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1834
1835 /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1836 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1837 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1838 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1839 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1840 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1841 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1842 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1843 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1844 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1845 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1846 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1847 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1848 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1849 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1850 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1851 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1852 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1853 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1854 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1855 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1856 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1857 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1858 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1859 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1860 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1861 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1862
1863 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1864 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1865 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1866
1867 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1868 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1869 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1870
1871 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1872 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1873 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1874
1875 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1876 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1877 "aclk_peris_66",
1878 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1879
1880 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1881 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1882 "aclk_peris_66",
1883 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1884
1885 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1886 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1887 "aclk_peris_66",
1888 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1889
1890 /* ENABLE_SCLK_PERIS */
1891 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1892 ENABLE_SCLK_PERIS, 10, 0, 0),
1893 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1894 ENABLE_SCLK_PERIS, 4, 0, 0),
1895 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1896 ENABLE_SCLK_PERIS, 3, 0, 0),
1897
1898 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1899 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1900 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1901
1902 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1903 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1904 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1905
1906 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1907 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1908 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1909
1910 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1911 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1912 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1913
1914 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1915 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1916 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1917
1918 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1919 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1920 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1921 };
1922
1923 static const struct samsung_cmu_info peris_cmu_info __initconst = {
1924 .gate_clks = peris_gate_clks,
1925 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1926 .nr_clk_ids = PERIS_NR_CLK,
1927 .clk_regs = peris_clk_regs,
1928 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1929 };
1930
1931 static void __init exynos5433_cmu_peris_init(struct device_node *np)
1932 {
1933 samsung_cmu_register_one(np, &peris_cmu_info);
1934 }
1935
1936 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1937 exynos5433_cmu_peris_init);
1938
1939 /*
1940 * Register offset definitions for CMU_FSYS
1941 */
1942 #define MUX_SEL_FSYS0 0x0200
1943 #define MUX_SEL_FSYS1 0x0204
1944 #define MUX_SEL_FSYS2 0x0208
1945 #define MUX_SEL_FSYS3 0x020c
1946 #define MUX_SEL_FSYS4 0x0210
1947 #define MUX_ENABLE_FSYS0 0x0300
1948 #define MUX_ENABLE_FSYS1 0x0304
1949 #define MUX_ENABLE_FSYS2 0x0308
1950 #define MUX_ENABLE_FSYS3 0x030c
1951 #define MUX_ENABLE_FSYS4 0x0310
1952 #define MUX_STAT_FSYS0 0x0400
1953 #define MUX_STAT_FSYS1 0x0404
1954 #define MUX_STAT_FSYS2 0x0408
1955 #define MUX_STAT_FSYS3 0x040c
1956 #define MUX_STAT_FSYS4 0x0410
1957 #define MUX_IGNORE_FSYS2 0x0508
1958 #define MUX_IGNORE_FSYS3 0x050c
1959 #define ENABLE_ACLK_FSYS0 0x0800
1960 #define ENABLE_ACLK_FSYS1 0x0804
1961 #define ENABLE_PCLK_FSYS 0x0900
1962 #define ENABLE_SCLK_FSYS 0x0a00
1963 #define ENABLE_IP_FSYS0 0x0b00
1964 #define ENABLE_IP_FSYS1 0x0b04
1965
1966 /* list of all parent clock list */
1967 PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
1968 PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "aclk_fsys_200", };
1969 PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
1970 PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
1971 PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
1972 PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
1973 PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
1974 PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
1975 PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
1976
1977 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1978 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1979 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1980 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1981 PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1982 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1983 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1984 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1985 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1986 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1987 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1988 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1989 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1990 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1991 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1992 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1993 PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1994 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1995 PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1996 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1997 PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1998 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1999 PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
2000 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
2001 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
2002 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
2003 PNAME(mout_sclk_mphy_p)
2004 = { "mout_sclk_ufs_mphy_user",
2005 "mout_phyclk_lli_mphy_to_ufs_user", };
2006
2007 static const unsigned long fsys_clk_regs[] __initconst = {
2008 MUX_SEL_FSYS0,
2009 MUX_SEL_FSYS1,
2010 MUX_SEL_FSYS2,
2011 MUX_SEL_FSYS3,
2012 MUX_SEL_FSYS4,
2013 MUX_ENABLE_FSYS0,
2014 MUX_ENABLE_FSYS1,
2015 MUX_ENABLE_FSYS2,
2016 MUX_ENABLE_FSYS3,
2017 MUX_ENABLE_FSYS4,
2018 MUX_IGNORE_FSYS2,
2019 MUX_IGNORE_FSYS3,
2020 ENABLE_ACLK_FSYS0,
2021 ENABLE_ACLK_FSYS1,
2022 ENABLE_PCLK_FSYS,
2023 ENABLE_SCLK_FSYS,
2024 ENABLE_IP_FSYS0,
2025 ENABLE_IP_FSYS1,
2026 };
2027
2028 static const struct samsung_clk_reg_dump fsys_suspend_regs[] = {
2029 { MUX_SEL_FSYS0, 0 },
2030 { MUX_SEL_FSYS1, 0 },
2031 { MUX_SEL_FSYS2, 0 },
2032 { MUX_SEL_FSYS3, 0 },
2033 { MUX_SEL_FSYS4, 0 },
2034 };
2035
2036 static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
2037 /* PHY clocks from USBDRD30_PHY */
2038 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
2039 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
2040 0, 60000000),
2041 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
2042 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
2043 0, 125000000),
2044 /* PHY clocks from USBHOST30_PHY */
2045 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
2046 "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
2047 0, 60000000),
2048 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
2049 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
2050 0, 125000000),
2051 /* PHY clocks from USBHOST20_PHY */
2052 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
2053 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
2054 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
2055 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
2056 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
2057 "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
2058 0, 48000000),
2059 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
2060 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
2061 60000000),
2062 /* PHY clocks from UFS_PHY */
2063 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
2064 NULL, 0, 300000000),
2065 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
2066 NULL, 0, 300000000),
2067 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
2068 NULL, 0, 300000000),
2069 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
2070 NULL, 0, 300000000),
2071 /* PHY clocks from LLI_PHY */
2072 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
2073 NULL, 0, 26000000),
2074 };
2075
2076 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
2077 /* MUX_SEL_FSYS0 */
2078 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2079 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2080 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2081 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2082
2083 /* MUX_SEL_FSYS1 */
2084 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2085 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2086 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2087 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2088 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2089 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2090 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2091 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2092 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2093 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2094 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2095 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2096 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2097 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2098
2099 /* MUX_SEL_FSYS2 */
2100 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2101 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2102 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2103 MUX_SEL_FSYS2, 28, 1),
2104 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2105 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2106 mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2107 MUX_SEL_FSYS2, 24, 1),
2108 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2109 "mout_phyclk_usbhost20_phy_hsic1",
2110 mout_phyclk_usbhost20_phy_hsic1_p,
2111 MUX_SEL_FSYS2, 20, 1),
2112 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2113 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2114 mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2115 MUX_SEL_FSYS2, 16, 1),
2116 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2117 "mout_phyclk_usbhost20_phy_phyclock_user",
2118 mout_phyclk_usbhost20_phy_phyclock_user_p,
2119 MUX_SEL_FSYS2, 12, 1),
2120 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2121 "mout_phyclk_usbhost20_phy_freeclk_user",
2122 mout_phyclk_usbhost20_phy_freeclk_user_p,
2123 MUX_SEL_FSYS2, 8, 1),
2124 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2125 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2126 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2127 MUX_SEL_FSYS2, 4, 1),
2128 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2129 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2130 mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2131 MUX_SEL_FSYS2, 0, 1),
2132
2133 /* MUX_SEL_FSYS3 */
2134 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2135 "mout_phyclk_ufs_rx1_symbol_user",
2136 mout_phyclk_ufs_rx1_symbol_user_p,
2137 MUX_SEL_FSYS3, 16, 1),
2138 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2139 "mout_phyclk_ufs_rx0_symbol_user",
2140 mout_phyclk_ufs_rx0_symbol_user_p,
2141 MUX_SEL_FSYS3, 12, 1),
2142 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2143 "mout_phyclk_ufs_tx1_symbol_user",
2144 mout_phyclk_ufs_tx1_symbol_user_p,
2145 MUX_SEL_FSYS3, 8, 1),
2146 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2147 "mout_phyclk_ufs_tx0_symbol_user",
2148 mout_phyclk_ufs_tx0_symbol_user_p,
2149 MUX_SEL_FSYS3, 4, 1),
2150 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2151 "mout_phyclk_lli_mphy_to_ufs_user",
2152 mout_phyclk_lli_mphy_to_ufs_user_p,
2153 MUX_SEL_FSYS3, 0, 1),
2154
2155 /* MUX_SEL_FSYS4 */
2156 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2157 MUX_SEL_FSYS4, 0, 1),
2158 };
2159
2160 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
2161 /* ENABLE_ACLK_FSYS0 */
2162 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2163 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2164 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2165 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2166 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2167 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2168 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2169 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2170 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2171 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2172 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2173 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2174 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2175 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2176 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2177 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2178 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2179 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2180 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2181 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2182 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2183 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2184
2185 /* ENABLE_ACLK_FSYS1 */
2186 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2187 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2188 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2189 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2190 26, CLK_IGNORE_UNUSED, 0),
2191 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2192 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2193 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2194 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2195 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2196 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2197 22, CLK_IGNORE_UNUSED, 0),
2198 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2199 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2200 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2201 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2202 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2203 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2204 13, 0, 0),
2205 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2206 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2207 12, 0, 0),
2208 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2209 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2210 11, CLK_IGNORE_UNUSED, 0),
2211 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2212 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2213 10, CLK_IGNORE_UNUSED, 0),
2214 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2215 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2216 9, CLK_IGNORE_UNUSED, 0),
2217 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2218 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2219 8, CLK_IGNORE_UNUSED, 0),
2220 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2221 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2222 7, CLK_IGNORE_UNUSED, 0),
2223 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2224 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2225 6, CLK_IGNORE_UNUSED, 0),
2226 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2227 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2228 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2229 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2230 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2231 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2232 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2233 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2234 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2235 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2236 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2237 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2238
2239 /* ENABLE_PCLK_FSYS */
2240 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2241 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2242 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2243 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2244 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2245 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2246 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2247 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2248 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2249 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2250 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2251 ENABLE_PCLK_FSYS, 5, 0, 0),
2252 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2253 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2254 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2255 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2256 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2257 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2258 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2259 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2260 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2261 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2262 0, CLK_IGNORE_UNUSED, 0),
2263
2264 /* ENABLE_SCLK_FSYS */
2265 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2266 ENABLE_SCLK_FSYS, 21, 0, 0),
2267 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2268 "phyclk_usbhost30_uhost30_pipe_pclk",
2269 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2270 ENABLE_SCLK_FSYS, 18, 0, 0),
2271 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2272 "phyclk_usbhost30_uhost30_phyclock",
2273 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2274 ENABLE_SCLK_FSYS, 17, 0, 0),
2275 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2276 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2277 16, 0, 0),
2278 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2279 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2280 15, 0, 0),
2281 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2282 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2283 14, 0, 0),
2284 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2285 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2286 13, 0, 0),
2287 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2288 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2289 12, 0, 0),
2290 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2291 "phyclk_usbhost20_phy_clk48mohci",
2292 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2293 ENABLE_SCLK_FSYS, 11, 0, 0),
2294 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2295 "phyclk_usbhost20_phy_phyclock",
2296 "mout_phyclk_usbhost20_phy_phyclock_user",
2297 ENABLE_SCLK_FSYS, 10, 0, 0),
2298 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2299 "phyclk_usbhost20_phy_freeclk",
2300 "mout_phyclk_usbhost20_phy_freeclk_user",
2301 ENABLE_SCLK_FSYS, 9, 0, 0),
2302 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2303 "phyclk_usbdrd30_udrd30_pipe_pclk",
2304 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2305 ENABLE_SCLK_FSYS, 8, 0, 0),
2306 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2307 "phyclk_usbdrd30_udrd30_phyclock",
2308 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2309 ENABLE_SCLK_FSYS, 7, 0, 0),
2310 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2311 ENABLE_SCLK_FSYS, 6, 0, 0),
2312 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2313 ENABLE_SCLK_FSYS, 5, 0, 0),
2314 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2315 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2316 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2317 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2318 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2319 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2320 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2321 ENABLE_SCLK_FSYS, 1, 0, 0),
2322 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2323 ENABLE_SCLK_FSYS, 0, 0, 0),
2324
2325 /* ENABLE_IP_FSYS0 */
2326 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2327 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2328 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2329 };
2330
2331 static const struct samsung_cmu_info fsys_cmu_info __initconst = {
2332 .mux_clks = fsys_mux_clks,
2333 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
2334 .gate_clks = fsys_gate_clks,
2335 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
2336 .fixed_clks = fsys_fixed_clks,
2337 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
2338 .nr_clk_ids = FSYS_NR_CLK,
2339 .clk_regs = fsys_clk_regs,
2340 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
2341 .suspend_regs = fsys_suspend_regs,
2342 .nr_suspend_regs = ARRAY_SIZE(fsys_suspend_regs),
2343 .clk_name = "aclk_fsys_200",
2344 };
2345
2346 /*
2347 * Register offset definitions for CMU_G2D
2348 */
2349 #define MUX_SEL_G2D0 0x0200
2350 #define MUX_SEL_ENABLE_G2D0 0x0300
2351 #define MUX_SEL_STAT_G2D0 0x0400
2352 #define DIV_G2D 0x0600
2353 #define DIV_STAT_G2D 0x0700
2354 #define DIV_ENABLE_ACLK_G2D 0x0800
2355 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2356 #define DIV_ENABLE_PCLK_G2D 0x0900
2357 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2358 #define DIV_ENABLE_IP_G2D0 0x0b00
2359 #define DIV_ENABLE_IP_G2D1 0x0b04
2360 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2361
2362 static const unsigned long g2d_clk_regs[] __initconst = {
2363 MUX_SEL_G2D0,
2364 MUX_SEL_ENABLE_G2D0,
2365 DIV_G2D,
2366 DIV_ENABLE_ACLK_G2D,
2367 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2368 DIV_ENABLE_PCLK_G2D,
2369 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2370 DIV_ENABLE_IP_G2D0,
2371 DIV_ENABLE_IP_G2D1,
2372 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2373 };
2374
2375 static const struct samsung_clk_reg_dump g2d_suspend_regs[] = {
2376 { MUX_SEL_G2D0, 0 },
2377 };
2378
2379 /* list of all parent clock list */
2380 PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2381 PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
2382
2383 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
2384 /* MUX_SEL_G2D0 */
2385 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2386 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2387 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2388 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2389 };
2390
2391 static const struct samsung_div_clock g2d_div_clks[] __initconst = {
2392 /* DIV_G2D */
2393 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2394 DIV_G2D, 0, 2),
2395 };
2396
2397 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
2398 /* DIV_ENABLE_ACLK_G2D */
2399 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2400 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2401 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2402 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2403 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2404 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2405 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2406 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2407 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2408 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2409 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2410 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2411 7, 0, 0),
2412 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2413 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2414 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2415 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2416 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2417 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2418 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2419 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2420 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2421 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2422 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2423 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2424 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2425 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2426
2427 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2428 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2429 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2430
2431 /* DIV_ENABLE_PCLK_G2D */
2432 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2433 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2434 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2435 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2436 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2437 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2438 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2439 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2440 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2441 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2442 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2443 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2444 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2445 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2446 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2447 0, 0, 0),
2448
2449 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2450 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2451 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2452 };
2453
2454 static const struct samsung_cmu_info g2d_cmu_info __initconst = {
2455 .mux_clks = g2d_mux_clks,
2456 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
2457 .div_clks = g2d_div_clks,
2458 .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
2459 .gate_clks = g2d_gate_clks,
2460 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
2461 .nr_clk_ids = G2D_NR_CLK,
2462 .clk_regs = g2d_clk_regs,
2463 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
2464 .suspend_regs = g2d_suspend_regs,
2465 .nr_suspend_regs = ARRAY_SIZE(g2d_suspend_regs),
2466 .clk_name = "aclk_g2d_400",
2467 };
2468
2469 /*
2470 * Register offset definitions for CMU_DISP
2471 */
2472 #define DISP_PLL_LOCK 0x0000
2473 #define DISP_PLL_CON0 0x0100
2474 #define DISP_PLL_CON1 0x0104
2475 #define DISP_PLL_FREQ_DET 0x0108
2476 #define MUX_SEL_DISP0 0x0200
2477 #define MUX_SEL_DISP1 0x0204
2478 #define MUX_SEL_DISP2 0x0208
2479 #define MUX_SEL_DISP3 0x020c
2480 #define MUX_SEL_DISP4 0x0210
2481 #define MUX_ENABLE_DISP0 0x0300
2482 #define MUX_ENABLE_DISP1 0x0304
2483 #define MUX_ENABLE_DISP2 0x0308
2484 #define MUX_ENABLE_DISP3 0x030c
2485 #define MUX_ENABLE_DISP4 0x0310
2486 #define MUX_STAT_DISP0 0x0400
2487 #define MUX_STAT_DISP1 0x0404
2488 #define MUX_STAT_DISP2 0x0408
2489 #define MUX_STAT_DISP3 0x040c
2490 #define MUX_STAT_DISP4 0x0410
2491 #define MUX_IGNORE_DISP2 0x0508
2492 #define DIV_DISP 0x0600
2493 #define DIV_DISP_PLL_FREQ_DET 0x0604
2494 #define DIV_STAT_DISP 0x0700
2495 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2496 #define ENABLE_ACLK_DISP0 0x0800
2497 #define ENABLE_ACLK_DISP1 0x0804
2498 #define ENABLE_PCLK_DISP 0x0900
2499 #define ENABLE_SCLK_DISP 0x0a00
2500 #define ENABLE_IP_DISP0 0x0b00
2501 #define ENABLE_IP_DISP1 0x0b04
2502 #define CLKOUT_CMU_DISP 0x0c00
2503 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2504
2505 static const unsigned long disp_clk_regs[] __initconst = {
2506 DISP_PLL_LOCK,
2507 DISP_PLL_CON0,
2508 DISP_PLL_CON1,
2509 DISP_PLL_FREQ_DET,
2510 MUX_SEL_DISP0,
2511 MUX_SEL_DISP1,
2512 MUX_SEL_DISP2,
2513 MUX_SEL_DISP3,
2514 MUX_SEL_DISP4,
2515 MUX_ENABLE_DISP0,
2516 MUX_ENABLE_DISP1,
2517 MUX_ENABLE_DISP2,
2518 MUX_ENABLE_DISP3,
2519 MUX_ENABLE_DISP4,
2520 MUX_IGNORE_DISP2,
2521 DIV_DISP,
2522 DIV_DISP_PLL_FREQ_DET,
2523 ENABLE_ACLK_DISP0,
2524 ENABLE_ACLK_DISP1,
2525 ENABLE_PCLK_DISP,
2526 ENABLE_SCLK_DISP,
2527 ENABLE_IP_DISP0,
2528 ENABLE_IP_DISP1,
2529 CLKOUT_CMU_DISP,
2530 CLKOUT_CMU_DISP_DIV_STAT,
2531 };
2532
2533 static const struct samsung_clk_reg_dump disp_suspend_regs[] = {
2534 /* PLL has to be enabled for suspend */
2535 { DISP_PLL_CON0, 0x85f40502 },
2536 /* ignore status of external PHY muxes during suspend to avoid hangs */
2537 { MUX_IGNORE_DISP2, 0x00111111 },
2538 { MUX_SEL_DISP0, 0 },
2539 { MUX_SEL_DISP1, 0 },
2540 { MUX_SEL_DISP2, 0 },
2541 { MUX_SEL_DISP3, 0 },
2542 { MUX_SEL_DISP4, 0 },
2543 };
2544
2545 /* list of all parent clock list */
2546 PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
2547 PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
2548 PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
2549 PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
2550 PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
2551 "sclk_decon_tv_eclk_disp", };
2552 PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
2553 "sclk_decon_vclk_disp", };
2554 PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
2555 "sclk_decon_eclk_disp", };
2556 PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
2557 "sclk_decon_tv_vclk_disp", };
2558 PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
2559
2560 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
2561 "phyclk_mipidphy1_bitclkdiv8_phy", };
2562 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
2563 "phyclk_mipidphy1_rxclkesc0_phy", };
2564 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
2565 "phyclk_mipidphy0_bitclkdiv8_phy", };
2566 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
2567 "phyclk_mipidphy0_rxclkesc0_phy", };
2568 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
2569 "phyclk_hdmiphy_tmds_clko_phy", };
2570 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
2571 "phyclk_hdmiphy_pixel_clko_phy", };
2572
2573 PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
2574 "mout_sclk_dsim0_user", };
2575 PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
2576 "mout_sclk_decon_tv_eclk_user", };
2577 PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
2578 "mout_sclk_decon_vclk_user", };
2579 PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
2580 "mout_sclk_decon_eclk_user", };
2581
2582 PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
2583 "mout_sclk_dsim1_user", };
2584 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2585 "mout_phyclk_hdmiphy_pixel_clko_user",
2586 "mout_sclk_decon_tv_vclk_b_disp", };
2587 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2588 "mout_sclk_decon_tv_vclk_user", };
2589
2590 static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
2591 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2592 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates),
2593 };
2594
2595 static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
2596 /*
2597 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2598 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2599 * and sclk_decon_{vclk|tv_vclk}.
2600 */
2601 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2602 1, 2, 0),
2603 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2604 1, 2, 0),
2605 };
2606
2607 static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
2608 /* PHY clocks from MIPI_DPHY1 */
2609 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2610 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
2611 /* PHY clocks from MIPI_DPHY0 */
2612 FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
2613 NULL, 0, 188000000),
2614 FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
2615 NULL, 0, 100000000),
2616 /* PHY clocks from HDMI_PHY */
2617 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
2618 NULL, 0, 300000000),
2619 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
2620 NULL, 0, 166000000),
2621 };
2622
2623 static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
2624 /* MUX_SEL_DISP0 */
2625 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2626 0, 1),
2627
2628 /* MUX_SEL_DISP1 */
2629 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2630 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2631 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2632 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2633 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2634 MUX_SEL_DISP1, 20, 1),
2635 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2636 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2637 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2638 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2639 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2640 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2641 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2642 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2643 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2644 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2645
2646 /* MUX_SEL_DISP2 */
2647 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2648 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2649 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2650 20, 1),
2651 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2652 "mout_phyclk_mipidphy1_rxclkesc0_user",
2653 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2654 16, 1),
2655 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2656 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2657 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2658 12, 1),
2659 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2660 "mout_phyclk_mipidphy0_rxclkesc0_user",
2661 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2662 8, 1),
2663 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2664 "mout_phyclk_hdmiphy_tmds_clko_user",
2665 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2666 4, 1),
2667 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2668 "mout_phyclk_hdmiphy_pixel_clko_user",
2669 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2670 0, 1),
2671
2672 /* MUX_SEL_DISP3 */
2673 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2674 MUX_SEL_DISP3, 12, 1),
2675 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2676 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2677 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2678 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2679 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2680 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2681
2682 /* MUX_SEL_DISP4 */
2683 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2684 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2685 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2686 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2687 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2688 "mout_sclk_decon_tv_vclk_c_disp",
2689 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2690 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2691 "mout_sclk_decon_tv_vclk_b_disp",
2692 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2693 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2694 "mout_sclk_decon_tv_vclk_a_disp",
2695 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2696 };
2697
2698 static const struct samsung_div_clock disp_div_clks[] __initconst = {
2699 /* DIV_DISP */
2700 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2701 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2702 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2703 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2704 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2705 DIV_DISP, 16, 3),
2706 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2707 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2708 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2709 "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2710 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2711 "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2712 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2713 DIV_DISP, 0, 2),
2714 };
2715
2716 static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
2717 /* ENABLE_ACLK_DISP0 */
2718 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2719 ENABLE_ACLK_DISP0, 2, 0, 0),
2720 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2721 ENABLE_ACLK_DISP0, 0, 0, 0),
2722
2723 /* ENABLE_ACLK_DISP1 */
2724 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2725 ENABLE_ACLK_DISP1, 25, 0, 0),
2726 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2727 ENABLE_ACLK_DISP1, 24, 0, 0),
2728 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2729 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2730 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2731 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2732 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2733 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2734 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2735 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2736 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2737 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2738 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2739 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2740 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2741 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2742 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2743 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2744 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2745 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2746 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2747 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2748 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2749 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2750 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2751 "div_pclk_disp", ENABLE_ACLK_DISP1,
2752 12, CLK_IGNORE_UNUSED, 0),
2753 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2754 "div_pclk_disp", ENABLE_ACLK_DISP1,
2755 11, CLK_IGNORE_UNUSED, 0),
2756 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2757 "div_pclk_disp", ENABLE_ACLK_DISP1,
2758 10, CLK_IGNORE_UNUSED, 0),
2759 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2760 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2761 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2762 ENABLE_ACLK_DISP1, 7, 0, 0),
2763 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2764 ENABLE_ACLK_DISP1, 6, 0, 0),
2765 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2766 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2767 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2768 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2769 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2770 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2771 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2772 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2773 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2774 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2775 CLK_IGNORE_UNUSED, 0),
2776 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2777 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2778 0, CLK_IGNORE_UNUSED, 0),
2779
2780 /* ENABLE_PCLK_DISP */
2781 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2782 ENABLE_PCLK_DISP, 23, 0, 0),
2783 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2784 ENABLE_PCLK_DISP, 22, 0, 0),
2785 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2786 ENABLE_PCLK_DISP, 21, 0, 0),
2787 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2788 ENABLE_PCLK_DISP, 20, 0, 0),
2789 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2790 ENABLE_PCLK_DISP, 19, 0, 0),
2791 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2792 ENABLE_PCLK_DISP, 18, 0, 0),
2793 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2794 ENABLE_PCLK_DISP, 17, 0, 0),
2795 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2796 ENABLE_PCLK_DISP, 16, 0, 0),
2797 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2798 ENABLE_PCLK_DISP, 15, 0, 0),
2799 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2800 ENABLE_PCLK_DISP, 14, 0, 0),
2801 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2802 ENABLE_PCLK_DISP, 13, 0, 0),
2803 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2804 ENABLE_PCLK_DISP, 12, 0, 0),
2805 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2806 ENABLE_PCLK_DISP, 11, 0, 0),
2807 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2808 ENABLE_PCLK_DISP, 10, 0, 0),
2809 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2810 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2811 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2812 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2813 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2814 ENABLE_PCLK_DISP, 7, 0, 0),
2815 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2816 ENABLE_PCLK_DISP, 6, 0, 0),
2817 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2818 ENABLE_PCLK_DISP, 5, 0, 0),
2819 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2820 ENABLE_PCLK_DISP, 3, 0, 0),
2821 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2822 ENABLE_PCLK_DISP, 2, 0, 0),
2823 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2824 ENABLE_PCLK_DISP, 1, 0, 0),
2825 GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
2826 ENABLE_PCLK_DISP, 0, 0, 0),
2827
2828 /* ENABLE_SCLK_DISP */
2829 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2830 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2831 ENABLE_SCLK_DISP, 26, 0, 0),
2832 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2833 "mout_phyclk_mipidphy1_rxclkesc0_user",
2834 ENABLE_SCLK_DISP, 25, 0, 0),
2835 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2836 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2837 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2838 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2839 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2840 ENABLE_SCLK_DISP, 22, 0, 0),
2841 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2842 "div_sclk_decon_tv_vclk_disp",
2843 ENABLE_SCLK_DISP, 21, 0, 0),
2844 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2845 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2846 ENABLE_SCLK_DISP, 15, 0, 0),
2847 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2848 "mout_phyclk_mipidphy0_rxclkesc0_user",
2849 ENABLE_SCLK_DISP, 14, 0, 0),
2850 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2851 "mout_phyclk_hdmiphy_tmds_clko_user",
2852 ENABLE_SCLK_DISP, 13, 0, 0),
2853 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2854 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2855 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2856 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2857 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2858 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2859 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2860 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2861 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2862 ENABLE_SCLK_DISP, 7, 0, 0),
2863 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2864 ENABLE_SCLK_DISP, 6, 0, 0),
2865 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2866 ENABLE_SCLK_DISP, 5, 0, 0),
2867 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2868 "div_sclk_decon_tv_eclk_disp",
2869 ENABLE_SCLK_DISP, 4, 0, 0),
2870 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2871 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2872 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2873 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2874 };
2875
2876 static const struct samsung_cmu_info disp_cmu_info __initconst = {
2877 .pll_clks = disp_pll_clks,
2878 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2879 .mux_clks = disp_mux_clks,
2880 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
2881 .div_clks = disp_div_clks,
2882 .nr_div_clks = ARRAY_SIZE(disp_div_clks),
2883 .gate_clks = disp_gate_clks,
2884 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
2885 .fixed_clks = disp_fixed_clks,
2886 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
2887 .fixed_factor_clks = disp_fixed_factor_clks,
2888 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
2889 .nr_clk_ids = DISP_NR_CLK,
2890 .clk_regs = disp_clk_regs,
2891 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
2892 .suspend_regs = disp_suspend_regs,
2893 .nr_suspend_regs = ARRAY_SIZE(disp_suspend_regs),
2894 .clk_name = "aclk_disp_333",
2895 };
2896
2897 /*
2898 * Register offset definitions for CMU_AUD
2899 */
2900 #define MUX_SEL_AUD0 0x0200
2901 #define MUX_SEL_AUD1 0x0204
2902 #define MUX_ENABLE_AUD0 0x0300
2903 #define MUX_ENABLE_AUD1 0x0304
2904 #define MUX_STAT_AUD0 0x0400
2905 #define DIV_AUD0 0x0600
2906 #define DIV_AUD1 0x0604
2907 #define DIV_STAT_AUD0 0x0700
2908 #define DIV_STAT_AUD1 0x0704
2909 #define ENABLE_ACLK_AUD 0x0800
2910 #define ENABLE_PCLK_AUD 0x0900
2911 #define ENABLE_SCLK_AUD0 0x0a00
2912 #define ENABLE_SCLK_AUD1 0x0a04
2913 #define ENABLE_IP_AUD0 0x0b00
2914 #define ENABLE_IP_AUD1 0x0b04
2915
2916 static const unsigned long aud_clk_regs[] __initconst = {
2917 MUX_SEL_AUD0,
2918 MUX_SEL_AUD1,
2919 MUX_ENABLE_AUD0,
2920 MUX_ENABLE_AUD1,
2921 DIV_AUD0,
2922 DIV_AUD1,
2923 ENABLE_ACLK_AUD,
2924 ENABLE_PCLK_AUD,
2925 ENABLE_SCLK_AUD0,
2926 ENABLE_SCLK_AUD1,
2927 ENABLE_IP_AUD0,
2928 ENABLE_IP_AUD1,
2929 };
2930
2931 static const struct samsung_clk_reg_dump aud_suspend_regs[] = {
2932 { MUX_SEL_AUD0, 0 },
2933 { MUX_SEL_AUD1, 0 },
2934 };
2935
2936 /* list of all parent clock list */
2937 PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2938 PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2939
2940 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
2941 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2942 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2943 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2944 };
2945
2946 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
2947 /* MUX_SEL_AUD0 */
2948 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2949 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2950
2951 /* MUX_SEL_AUD1 */
2952 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2953 MUX_SEL_AUD1, 8, 1),
2954 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2955 MUX_SEL_AUD1, 0, 1),
2956 };
2957
2958 static const struct samsung_div_clock aud_div_clks[] __initconst = {
2959 /* DIV_AUD0 */
2960 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2961 12, 4),
2962 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2963 8, 4),
2964 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2965 4, 4),
2966 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2967 0, 4),
2968
2969 /* DIV_AUD1 */
2970 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2971 "mout_aud_pll_user", DIV_AUD1, 16, 5),
2972 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2973 DIV_AUD1, 12, 4),
2974 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2975 DIV_AUD1, 4, 8),
2976 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
2977 DIV_AUD1, 0, 4),
2978 };
2979
2980 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
2981 /* ENABLE_ACLK_AUD */
2982 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2983 ENABLE_ACLK_AUD, 12, 0, 0),
2984 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2985 ENABLE_ACLK_AUD, 7, 0, 0),
2986 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2987 ENABLE_ACLK_AUD, 0, 4, 0),
2988 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2989 ENABLE_ACLK_AUD, 0, 3, 0),
2990 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2991 ENABLE_ACLK_AUD, 0, 2, 0),
2992 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2993 0, 1, 0),
2994 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
2995 0, CLK_IGNORE_UNUSED, 0),
2996
2997 /* ENABLE_PCLK_AUD */
2998 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
2999 13, 0, 0),
3000 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
3001 12, 0, 0),
3002 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
3003 11, 0, 0),
3004 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
3005 ENABLE_PCLK_AUD, 10, 0, 0),
3006 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
3007 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3008 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
3009 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3010 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
3011 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3012 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
3013 ENABLE_PCLK_AUD, 6, 0, 0),
3014 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
3015 ENABLE_PCLK_AUD, 5, 0, 0),
3016 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
3017 ENABLE_PCLK_AUD, 4, 0, 0),
3018 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
3019 ENABLE_PCLK_AUD, 3, 0, 0),
3020 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
3021 2, 0, 0),
3022 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
3023 ENABLE_PCLK_AUD, 0, 0, 0),
3024
3025 /* ENABLE_SCLK_AUD0 */
3026 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
3027 2, CLK_IGNORE_UNUSED, 0),
3028 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
3029 ENABLE_SCLK_AUD0, 1, 0, 0),
3030 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
3031 0, 0, 0),
3032
3033 /* ENABLE_SCLK_AUD1 */
3034 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
3035 ENABLE_SCLK_AUD1, 6, 0, 0),
3036 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
3037 ENABLE_SCLK_AUD1, 5, 0, 0),
3038 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
3039 ENABLE_SCLK_AUD1, 4, 0, 0),
3040 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
3041 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
3042 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
3043 ENABLE_SCLK_AUD1, 2, 0, 0),
3044 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
3045 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3046 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
3047 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3048 };
3049
3050 static const struct samsung_cmu_info aud_cmu_info __initconst = {
3051 .mux_clks = aud_mux_clks,
3052 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
3053 .div_clks = aud_div_clks,
3054 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
3055 .gate_clks = aud_gate_clks,
3056 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
3057 .fixed_clks = aud_fixed_clks,
3058 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
3059 .nr_clk_ids = AUD_NR_CLK,
3060 .clk_regs = aud_clk_regs,
3061 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
3062 .suspend_regs = aud_suspend_regs,
3063 .nr_suspend_regs = ARRAY_SIZE(aud_suspend_regs),
3064 .clk_name = "fout_aud_pll",
3065 };
3066
3067 /*
3068 * Register offset definitions for CMU_BUS{0|1|2}
3069 */
3070 #define DIV_BUS 0x0600
3071 #define DIV_STAT_BUS 0x0700
3072 #define ENABLE_ACLK_BUS 0x0800
3073 #define ENABLE_PCLK_BUS 0x0900
3074 #define ENABLE_IP_BUS0 0x0b00
3075 #define ENABLE_IP_BUS1 0x0b04
3076
3077 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
3078 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3079 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3080
3081 /* list of all parent clock list */
3082 PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3083
3084 #define CMU_BUS_COMMON_CLK_REGS \
3085 DIV_BUS, \
3086 ENABLE_ACLK_BUS, \
3087 ENABLE_PCLK_BUS, \
3088 ENABLE_IP_BUS0, \
3089 ENABLE_IP_BUS1
3090
3091 static const unsigned long bus01_clk_regs[] __initconst = {
3092 CMU_BUS_COMMON_CLK_REGS,
3093 };
3094
3095 static const unsigned long bus2_clk_regs[] __initconst = {
3096 MUX_SEL_BUS2,
3097 MUX_ENABLE_BUS2,
3098 CMU_BUS_COMMON_CLK_REGS,
3099 };
3100
3101 static const struct samsung_div_clock bus0_div_clks[] __initconst = {
3102 /* DIV_BUS0 */
3103 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3104 DIV_BUS, 0, 3),
3105 };
3106
3107 /* CMU_BUS0 clocks */
3108 static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
3109 /* ENABLE_ACLK_BUS0 */
3110 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3111 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3112 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3113 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3114 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3115 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3116
3117 /* ENABLE_PCLK_BUS0 */
3118 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3119 ENABLE_PCLK_BUS, 2, 0, 0),
3120 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3121 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3122 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3123 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3124 };
3125
3126 /* CMU_BUS1 clocks */
3127 static const struct samsung_div_clock bus1_div_clks[] __initconst = {
3128 /* DIV_BUS1 */
3129 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3130 DIV_BUS, 0, 3),
3131 };
3132
3133 static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
3134 /* ENABLE_ACLK_BUS1 */
3135 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3136 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3137 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3138 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3139 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3140 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3141
3142 /* ENABLE_PCLK_BUS1 */
3143 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3144 ENABLE_PCLK_BUS, 2, 0, 0),
3145 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3146 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3147 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3148 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3149 };
3150
3151 /* CMU_BUS2 clocks */
3152 static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
3153 /* MUX_SEL_BUS2 */
3154 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3155 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3156 };
3157
3158 static const struct samsung_div_clock bus2_div_clks[] __initconst = {
3159 /* DIV_BUS2 */
3160 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3161 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3162 };
3163
3164 static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
3165 /* ENABLE_ACLK_BUS2 */
3166 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3167 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3168 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3169 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3170 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3171 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3172 1, CLK_IGNORE_UNUSED, 0),
3173 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3174 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3175 0, CLK_IGNORE_UNUSED, 0),
3176
3177 /* ENABLE_PCLK_BUS2 */
3178 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3179 ENABLE_PCLK_BUS, 2, 0, 0),
3180 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3181 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3182 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3183 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3184 };
3185
3186 #define CMU_BUS_INFO_CLKS(id) \
3187 .div_clks = bus##id##_div_clks, \
3188 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
3189 .gate_clks = bus##id##_gate_clks, \
3190 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3191 .nr_clk_ids = BUSx_NR_CLK
3192
3193 static const struct samsung_cmu_info bus0_cmu_info __initconst = {
3194 CMU_BUS_INFO_CLKS(0),
3195 .clk_regs = bus01_clk_regs,
3196 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3197 };
3198
3199 static const struct samsung_cmu_info bus1_cmu_info __initconst = {
3200 CMU_BUS_INFO_CLKS(1),
3201 .clk_regs = bus01_clk_regs,
3202 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3203 };
3204
3205 static const struct samsung_cmu_info bus2_cmu_info __initconst = {
3206 CMU_BUS_INFO_CLKS(2),
3207 .mux_clks = bus2_mux_clks,
3208 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
3209 .clk_regs = bus2_clk_regs,
3210 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
3211 };
3212
3213 #define exynos5433_cmu_bus_init(id) \
3214 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3215 { \
3216 samsung_cmu_register_one(np, &bus##id##_cmu_info); \
3217 } \
3218 CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
3219 "samsung,exynos5433-cmu-bus"#id, \
3220 exynos5433_cmu_bus##id##_init)
3221
3222 exynos5433_cmu_bus_init(0);
3223 exynos5433_cmu_bus_init(1);
3224 exynos5433_cmu_bus_init(2);
3225
3226 /*
3227 * Register offset definitions for CMU_G3D
3228 */
3229 #define G3D_PLL_LOCK 0x0000
3230 #define G3D_PLL_CON0 0x0100
3231 #define G3D_PLL_CON1 0x0104
3232 #define G3D_PLL_FREQ_DET 0x010c
3233 #define MUX_SEL_G3D 0x0200
3234 #define MUX_ENABLE_G3D 0x0300
3235 #define MUX_STAT_G3D 0x0400
3236 #define DIV_G3D 0x0600
3237 #define DIV_G3D_PLL_FREQ_DET 0x0604
3238 #define DIV_STAT_G3D 0x0700
3239 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3240 #define ENABLE_ACLK_G3D 0x0800
3241 #define ENABLE_PCLK_G3D 0x0900
3242 #define ENABLE_SCLK_G3D 0x0a00
3243 #define ENABLE_IP_G3D0 0x0b00
3244 #define ENABLE_IP_G3D1 0x0b04
3245 #define CLKOUT_CMU_G3D 0x0c00
3246 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3247 #define CLK_STOPCTRL 0x1000
3248
3249 static const unsigned long g3d_clk_regs[] __initconst = {
3250 G3D_PLL_LOCK,
3251 G3D_PLL_CON0,
3252 G3D_PLL_CON1,
3253 G3D_PLL_FREQ_DET,
3254 MUX_SEL_G3D,
3255 MUX_ENABLE_G3D,
3256 DIV_G3D,
3257 DIV_G3D_PLL_FREQ_DET,
3258 ENABLE_ACLK_G3D,
3259 ENABLE_PCLK_G3D,
3260 ENABLE_SCLK_G3D,
3261 ENABLE_IP_G3D0,
3262 ENABLE_IP_G3D1,
3263 CLKOUT_CMU_G3D,
3264 CLKOUT_CMU_G3D_DIV_STAT,
3265 CLK_STOPCTRL,
3266 };
3267
3268 static const struct samsung_clk_reg_dump g3d_suspend_regs[] = {
3269 { MUX_SEL_G3D, 0 },
3270 };
3271
3272 /* list of all parent clock list */
3273 PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3274 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
3275
3276 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
3277 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3278 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates),
3279 };
3280
3281 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
3282 /* MUX_SEL_G3D */
3283 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3284 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3285 MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3286 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3287 };
3288
3289 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
3290 /* DIV_G3D */
3291 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3292 8, 2),
3293 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3294 4, 3),
3295 DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3296 0, 3, CLK_SET_RATE_PARENT, 0),
3297 };
3298
3299 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
3300 /* ENABLE_ACLK_G3D */
3301 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3302 ENABLE_ACLK_G3D, 7, 0, 0),
3303 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3304 ENABLE_ACLK_G3D, 6, 0, 0),
3305 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3306 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3307 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3308 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3309 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3310 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3311 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3312 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3313 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3314 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3315 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3316 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3317
3318 /* ENABLE_PCLK_G3D */
3319 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3320 ENABLE_PCLK_G3D, 3, 0, 0),
3321 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3322 ENABLE_PCLK_G3D, 2, 0, 0),
3323 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3324 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3325 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3326 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3327
3328 /* ENABLE_SCLK_G3D */
3329 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3330 ENABLE_SCLK_G3D, 0, 0, 0),
3331 };
3332
3333 static const struct samsung_cmu_info g3d_cmu_info __initconst = {
3334 .pll_clks = g3d_pll_clks,
3335 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
3336 .mux_clks = g3d_mux_clks,
3337 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
3338 .div_clks = g3d_div_clks,
3339 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
3340 .gate_clks = g3d_gate_clks,
3341 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
3342 .nr_clk_ids = G3D_NR_CLK,
3343 .clk_regs = g3d_clk_regs,
3344 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
3345 .suspend_regs = g3d_suspend_regs,
3346 .nr_suspend_regs = ARRAY_SIZE(g3d_suspend_regs),
3347 .clk_name = "aclk_g3d_400",
3348 };
3349
3350 /*
3351 * Register offset definitions for CMU_GSCL
3352 */
3353 #define MUX_SEL_GSCL 0x0200
3354 #define MUX_ENABLE_GSCL 0x0300
3355 #define MUX_STAT_GSCL 0x0400
3356 #define ENABLE_ACLK_GSCL 0x0800
3357 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3358 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3359 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3360 #define ENABLE_PCLK_GSCL 0x0900
3361 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3362 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3363 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3364 #define ENABLE_IP_GSCL0 0x0b00
3365 #define ENABLE_IP_GSCL1 0x0b04
3366 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3367 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3368 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3369
3370 static const unsigned long gscl_clk_regs[] __initconst = {
3371 MUX_SEL_GSCL,
3372 MUX_ENABLE_GSCL,
3373 ENABLE_ACLK_GSCL,
3374 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3375 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3376 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3377 ENABLE_PCLK_GSCL,
3378 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3379 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3380 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3381 ENABLE_IP_GSCL0,
3382 ENABLE_IP_GSCL1,
3383 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3384 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3385 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3386 };
3387
3388 static const struct samsung_clk_reg_dump gscl_suspend_regs[] = {
3389 { MUX_SEL_GSCL, 0 },
3390 { ENABLE_ACLK_GSCL, 0xfff },
3391 { ENABLE_PCLK_GSCL, 0xff },
3392 };
3393
3394 /* list of all parent clock list */
3395 PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3396 PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3397
3398 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
3399 /* MUX_SEL_GSCL */
3400 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3401 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3402 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3403 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3404 };
3405
3406 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
3407 /* ENABLE_ACLK_GSCL */
3408 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3409 ENABLE_ACLK_GSCL, 11, 0, 0),
3410 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3411 ENABLE_ACLK_GSCL, 10, 0, 0),
3412 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3413 ENABLE_ACLK_GSCL, 9, 0, 0),
3414 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3415 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3416 8, CLK_IGNORE_UNUSED, 0),
3417 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3418 ENABLE_ACLK_GSCL, 7, 0, 0),
3419 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3420 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3421 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3422 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
3423 CLK_IGNORE_UNUSED, 0),
3424 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3425 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
3426 CLK_IGNORE_UNUSED, 0),
3427 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3428 ENABLE_ACLK_GSCL, 3, 0, 0),
3429 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3430 ENABLE_ACLK_GSCL, 2, 0, 0),
3431 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3432 ENABLE_ACLK_GSCL, 1, 0, 0),
3433 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3434 ENABLE_ACLK_GSCL, 0, 0, 0),
3435
3436 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3437 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3438 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3439
3440 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3441 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3442 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3443
3444 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3445 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3446 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3447
3448 /* ENABLE_PCLK_GSCL */
3449 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3450 ENABLE_PCLK_GSCL, 7, 0, 0),
3451 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3452 ENABLE_PCLK_GSCL, 6, 0, 0),
3453 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3454 ENABLE_PCLK_GSCL, 5, 0, 0),
3455 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3456 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3457 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3458 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3459 3, CLK_IGNORE_UNUSED, 0),
3460 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3461 ENABLE_PCLK_GSCL, 2, 0, 0),
3462 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3463 ENABLE_PCLK_GSCL, 1, 0, 0),
3464 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3465 ENABLE_PCLK_GSCL, 0, 0, 0),
3466
3467 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3468 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3469 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3470
3471 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3472 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3473 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3474
3475 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3476 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3477 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3478 };
3479
3480 static const struct samsung_cmu_info gscl_cmu_info __initconst = {
3481 .mux_clks = gscl_mux_clks,
3482 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
3483 .gate_clks = gscl_gate_clks,
3484 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
3485 .nr_clk_ids = GSCL_NR_CLK,
3486 .clk_regs = gscl_clk_regs,
3487 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
3488 .suspend_regs = gscl_suspend_regs,
3489 .nr_suspend_regs = ARRAY_SIZE(gscl_suspend_regs),
3490 .clk_name = "aclk_gscl_111",
3491 };
3492
3493 /*
3494 * Register offset definitions for CMU_APOLLO
3495 */
3496 #define APOLLO_PLL_LOCK 0x0000
3497 #define APOLLO_PLL_CON0 0x0100
3498 #define APOLLO_PLL_CON1 0x0104
3499 #define APOLLO_PLL_FREQ_DET 0x010c
3500 #define MUX_SEL_APOLLO0 0x0200
3501 #define MUX_SEL_APOLLO1 0x0204
3502 #define MUX_SEL_APOLLO2 0x0208
3503 #define MUX_ENABLE_APOLLO0 0x0300
3504 #define MUX_ENABLE_APOLLO1 0x0304
3505 #define MUX_ENABLE_APOLLO2 0x0308
3506 #define MUX_STAT_APOLLO0 0x0400
3507 #define MUX_STAT_APOLLO1 0x0404
3508 #define MUX_STAT_APOLLO2 0x0408
3509 #define DIV_APOLLO0 0x0600
3510 #define DIV_APOLLO1 0x0604
3511 #define DIV_APOLLO_PLL_FREQ_DET 0x0608
3512 #define DIV_STAT_APOLLO0 0x0700
3513 #define DIV_STAT_APOLLO1 0x0704
3514 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3515 #define ENABLE_ACLK_APOLLO 0x0800
3516 #define ENABLE_PCLK_APOLLO 0x0900
3517 #define ENABLE_SCLK_APOLLO 0x0a00
3518 #define ENABLE_IP_APOLLO0 0x0b00
3519 #define ENABLE_IP_APOLLO1 0x0b04
3520 #define CLKOUT_CMU_APOLLO 0x0c00
3521 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3522 #define ARMCLK_STOPCTRL 0x1000
3523 #define APOLLO_PWR_CTRL 0x1020
3524 #define APOLLO_PWR_CTRL2 0x1024
3525 #define APOLLO_INTR_SPREAD_ENABLE 0x1080
3526 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3527 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3528
3529 static const unsigned long apollo_clk_regs[] __initconst = {
3530 APOLLO_PLL_LOCK,
3531 APOLLO_PLL_CON0,
3532 APOLLO_PLL_CON1,
3533 APOLLO_PLL_FREQ_DET,
3534 MUX_SEL_APOLLO0,
3535 MUX_SEL_APOLLO1,
3536 MUX_SEL_APOLLO2,
3537 MUX_ENABLE_APOLLO0,
3538 MUX_ENABLE_APOLLO1,
3539 MUX_ENABLE_APOLLO2,
3540 DIV_APOLLO0,
3541 DIV_APOLLO1,
3542 DIV_APOLLO_PLL_FREQ_DET,
3543 ENABLE_ACLK_APOLLO,
3544 ENABLE_PCLK_APOLLO,
3545 ENABLE_SCLK_APOLLO,
3546 ENABLE_IP_APOLLO0,
3547 ENABLE_IP_APOLLO1,
3548 CLKOUT_CMU_APOLLO,
3549 CLKOUT_CMU_APOLLO_DIV_STAT,
3550 ARMCLK_STOPCTRL,
3551 APOLLO_PWR_CTRL,
3552 APOLLO_PWR_CTRL2,
3553 APOLLO_INTR_SPREAD_ENABLE,
3554 APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3555 APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3556 };
3557
3558 /* list of all parent clock list */
3559 PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
3560 PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
3561 PNAME(mout_apollo_p) = { "mout_apollo_pll",
3562 "mout_bus_pll_apollo_user", };
3563
3564 static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
3565 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3566 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates),
3567 };
3568
3569 static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
3570 /* MUX_SEL_APOLLO0 */
3571 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3572 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
3573 CLK_RECALC_NEW_RATES, 0),
3574
3575 /* MUX_SEL_APOLLO1 */
3576 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3577 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3578
3579 /* MUX_SEL_APOLLO2 */
3580 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3581 0, 1, CLK_SET_RATE_PARENT, 0),
3582 };
3583
3584 static const struct samsung_div_clock apollo_div_clks[] __initconst = {
3585 /* DIV_APOLLO0 */
3586 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3587 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3588 CLK_DIVIDER_READ_ONLY),
3589 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3590 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3591 CLK_DIVIDER_READ_ONLY),
3592 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3593 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3594 CLK_DIVIDER_READ_ONLY),
3595 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3596 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3597 CLK_DIVIDER_READ_ONLY),
3598 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3599 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3600 CLK_DIVIDER_READ_ONLY),
3601 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3602 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
3603 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3604 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
3605
3606 /* DIV_APOLLO1 */
3607 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3608 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3609 CLK_DIVIDER_READ_ONLY),
3610 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3611 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3612 CLK_DIVIDER_READ_ONLY),
3613 };
3614
3615 static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
3616 /* ENABLE_ACLK_APOLLO */
3617 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3618 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3619 6, CLK_IGNORE_UNUSED, 0),
3620 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3621 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3622 5, CLK_IGNORE_UNUSED, 0),
3623 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3624 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3625 4, CLK_IGNORE_UNUSED, 0),
3626 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3627 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3628 3, CLK_IGNORE_UNUSED, 0),
3629 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3630 "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3631 2, CLK_IGNORE_UNUSED, 0),
3632 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3633 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3634 1, CLK_IGNORE_UNUSED, 0),
3635 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3636 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3637 0, CLK_IGNORE_UNUSED, 0),
3638
3639 /* ENABLE_PCLK_APOLLO */
3640 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3641 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3642 2, CLK_IGNORE_UNUSED, 0),
3643 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3644 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3645 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3646 "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3647 0, CLK_IGNORE_UNUSED, 0),
3648
3649 /* ENABLE_SCLK_APOLLO */
3650 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3651 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3652 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3653 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3654 };
3655
3656 #define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3657 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3658 ((pclk) << 12) | ((aclk) << 8))
3659
3660 #define E5433_APOLLO_DIV1(hpm, copy) \
3661 (((hpm) << 4) | ((copy) << 0))
3662
3663 static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {
3664 { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3665 { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3666 { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3667 { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3668 { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3669 { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3670 { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3671 { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3672 { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3673 { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3674 { 0 },
3675 };
3676
3677 static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3678 {
3679 void __iomem *reg_base;
3680 struct samsung_clk_provider *ctx;
3681
3682 reg_base = of_iomap(np, 0);
3683 if (!reg_base) {
3684 panic("%s: failed to map registers\n", __func__);
3685 return;
3686 }
3687
3688 ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK);
3689 if (!ctx) {
3690 panic("%s: unable to allocate ctx\n", __func__);
3691 return;
3692 }
3693
3694 samsung_clk_register_pll(ctx, apollo_pll_clks,
3695 ARRAY_SIZE(apollo_pll_clks), reg_base);
3696 samsung_clk_register_mux(ctx, apollo_mux_clks,
3697 ARRAY_SIZE(apollo_mux_clks));
3698 samsung_clk_register_div(ctx, apollo_div_clks,
3699 ARRAY_SIZE(apollo_div_clks));
3700 samsung_clk_register_gate(ctx, apollo_gate_clks,
3701 ARRAY_SIZE(apollo_gate_clks));
3702
3703 exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
3704 mout_apollo_p[0], mout_apollo_p[1], 0x200,
3705 exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
3706 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3707
3708 samsung_clk_sleep_init(reg_base, apollo_clk_regs,
3709 ARRAY_SIZE(apollo_clk_regs));
3710
3711 samsung_clk_of_add_provider(np, ctx);
3712 }
3713 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3714 exynos5433_cmu_apollo_init);
3715
3716 /*
3717 * Register offset definitions for CMU_ATLAS
3718 */
3719 #define ATLAS_PLL_LOCK 0x0000
3720 #define ATLAS_PLL_CON0 0x0100
3721 #define ATLAS_PLL_CON1 0x0104
3722 #define ATLAS_PLL_FREQ_DET 0x010c
3723 #define MUX_SEL_ATLAS0 0x0200
3724 #define MUX_SEL_ATLAS1 0x0204
3725 #define MUX_SEL_ATLAS2 0x0208
3726 #define MUX_ENABLE_ATLAS0 0x0300
3727 #define MUX_ENABLE_ATLAS1 0x0304
3728 #define MUX_ENABLE_ATLAS2 0x0308
3729 #define MUX_STAT_ATLAS0 0x0400
3730 #define MUX_STAT_ATLAS1 0x0404
3731 #define MUX_STAT_ATLAS2 0x0408
3732 #define DIV_ATLAS0 0x0600
3733 #define DIV_ATLAS1 0x0604
3734 #define DIV_ATLAS_PLL_FREQ_DET 0x0608
3735 #define DIV_STAT_ATLAS0 0x0700
3736 #define DIV_STAT_ATLAS1 0x0704
3737 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3738 #define ENABLE_ACLK_ATLAS 0x0800
3739 #define ENABLE_PCLK_ATLAS 0x0900
3740 #define ENABLE_SCLK_ATLAS 0x0a00
3741 #define ENABLE_IP_ATLAS0 0x0b00
3742 #define ENABLE_IP_ATLAS1 0x0b04
3743 #define CLKOUT_CMU_ATLAS 0x0c00
3744 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3745 #define ARMCLK_STOPCTRL 0x1000
3746 #define ATLAS_PWR_CTRL 0x1020
3747 #define ATLAS_PWR_CTRL2 0x1024
3748 #define ATLAS_INTR_SPREAD_ENABLE 0x1080
3749 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3750 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3751
3752 static const unsigned long atlas_clk_regs[] __initconst = {
3753 ATLAS_PLL_LOCK,
3754 ATLAS_PLL_CON0,
3755 ATLAS_PLL_CON1,
3756 ATLAS_PLL_FREQ_DET,
3757 MUX_SEL_ATLAS0,
3758 MUX_SEL_ATLAS1,
3759 MUX_SEL_ATLAS2,
3760 MUX_ENABLE_ATLAS0,
3761 MUX_ENABLE_ATLAS1,
3762 MUX_ENABLE_ATLAS2,
3763 DIV_ATLAS0,
3764 DIV_ATLAS1,
3765 DIV_ATLAS_PLL_FREQ_DET,
3766 ENABLE_ACLK_ATLAS,
3767 ENABLE_PCLK_ATLAS,
3768 ENABLE_SCLK_ATLAS,
3769 ENABLE_IP_ATLAS0,
3770 ENABLE_IP_ATLAS1,
3771 CLKOUT_CMU_ATLAS,
3772 CLKOUT_CMU_ATLAS_DIV_STAT,
3773 ARMCLK_STOPCTRL,
3774 ATLAS_PWR_CTRL,
3775 ATLAS_PWR_CTRL2,
3776 ATLAS_INTR_SPREAD_ENABLE,
3777 ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3778 ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3779 };
3780
3781 /* list of all parent clock list */
3782 PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
3783 PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
3784 PNAME(mout_atlas_p) = { "mout_atlas_pll",
3785 "mout_bus_pll_atlas_user", };
3786
3787 static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
3788 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3789 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates),
3790 };
3791
3792 static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
3793 /* MUX_SEL_ATLAS0 */
3794 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3795 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
3796 CLK_RECALC_NEW_RATES, 0),
3797
3798 /* MUX_SEL_ATLAS1 */
3799 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3800 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3801
3802 /* MUX_SEL_ATLAS2 */
3803 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3804 0, 1, CLK_SET_RATE_PARENT, 0),
3805 };
3806
3807 static const struct samsung_div_clock atlas_div_clks[] __initconst = {
3808 /* DIV_ATLAS0 */
3809 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3810 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3811 CLK_DIVIDER_READ_ONLY),
3812 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3813 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3814 CLK_DIVIDER_READ_ONLY),
3815 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3816 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3817 CLK_DIVIDER_READ_ONLY),
3818 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3819 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3820 CLK_DIVIDER_READ_ONLY),
3821 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3822 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3823 CLK_DIVIDER_READ_ONLY),
3824 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3825 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3826 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3827 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3828
3829 /* DIV_ATLAS1 */
3830 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3831 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3832 CLK_DIVIDER_READ_ONLY),
3833 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3834 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3835 CLK_DIVIDER_READ_ONLY),
3836 };
3837
3838 static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
3839 /* ENABLE_ACLK_ATLAS */
3840 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3841 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3842 9, CLK_IGNORE_UNUSED, 0),
3843 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3844 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3845 8, CLK_IGNORE_UNUSED, 0),
3846 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3847 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3848 7, CLK_IGNORE_UNUSED, 0),
3849 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3850 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3851 6, CLK_IGNORE_UNUSED, 0),
3852 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3853 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3854 5, CLK_IGNORE_UNUSED, 0),
3855 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3856 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3857 4, CLK_IGNORE_UNUSED, 0),
3858 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3859 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3860 3, CLK_IGNORE_UNUSED, 0),
3861 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3862 "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3863 2, CLK_IGNORE_UNUSED, 0),
3864 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3865 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3866 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3867 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3868
3869 /* ENABLE_PCLK_ATLAS */
3870 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3871 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3872 5, CLK_IGNORE_UNUSED, 0),
3873 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3874 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3875 4, CLK_IGNORE_UNUSED, 0),
3876 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3877 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3878 3, CLK_IGNORE_UNUSED, 0),
3879 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3880 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3881 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3882 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3883 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3884 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3885
3886 /* ENABLE_SCLK_ATLAS */
3887 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3888 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3889 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3890 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3891 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3892 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3893 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3894 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3895 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3896 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3897 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3898 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3899 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3900 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3901 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3902 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3903 };
3904
3905 #define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3906 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3907 ((pclk) << 12) | ((aclk) << 8))
3908
3909 #define E5433_ATLAS_DIV1(hpm, copy) \
3910 (((hpm) << 4) | ((copy) << 0))
3911
3912 static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {
3913 { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3914 { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3915 { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3916 { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3917 { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3918 { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3919 { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3920 { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3921 { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3922 { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3923 { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3924 { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3925 { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3926 { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3927 { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3928 { 0 },
3929 };
3930
3931 static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3932 {
3933 void __iomem *reg_base;
3934 struct samsung_clk_provider *ctx;
3935
3936 reg_base = of_iomap(np, 0);
3937 if (!reg_base) {
3938 panic("%s: failed to map registers\n", __func__);
3939 return;
3940 }
3941
3942 ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK);
3943 if (!ctx) {
3944 panic("%s: unable to allocate ctx\n", __func__);
3945 return;
3946 }
3947
3948 samsung_clk_register_pll(ctx, atlas_pll_clks,
3949 ARRAY_SIZE(atlas_pll_clks), reg_base);
3950 samsung_clk_register_mux(ctx, atlas_mux_clks,
3951 ARRAY_SIZE(atlas_mux_clks));
3952 samsung_clk_register_div(ctx, atlas_div_clks,
3953 ARRAY_SIZE(atlas_div_clks));
3954 samsung_clk_register_gate(ctx, atlas_gate_clks,
3955 ARRAY_SIZE(atlas_gate_clks));
3956
3957 exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
3958 mout_atlas_p[0], mout_atlas_p[1], 0x200,
3959 exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
3960 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3961
3962 samsung_clk_sleep_init(reg_base, atlas_clk_regs,
3963 ARRAY_SIZE(atlas_clk_regs));
3964
3965 samsung_clk_of_add_provider(np, ctx);
3966 }
3967 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3968 exynos5433_cmu_atlas_init);
3969
3970 /*
3971 * Register offset definitions for CMU_MSCL
3972 */
3973 #define MUX_SEL_MSCL0 0x0200
3974 #define MUX_SEL_MSCL1 0x0204
3975 #define MUX_ENABLE_MSCL0 0x0300
3976 #define MUX_ENABLE_MSCL1 0x0304
3977 #define MUX_STAT_MSCL0 0x0400
3978 #define MUX_STAT_MSCL1 0x0404
3979 #define DIV_MSCL 0x0600
3980 #define DIV_STAT_MSCL 0x0700
3981 #define ENABLE_ACLK_MSCL 0x0800
3982 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3983 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3984 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3985 #define ENABLE_PCLK_MSCL 0x0900
3986 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3987 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3988 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
3989 #define ENABLE_SCLK_MSCL 0x0a00
3990 #define ENABLE_IP_MSCL0 0x0b00
3991 #define ENABLE_IP_MSCL1 0x0b04
3992 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3993 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3994 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3995
3996 static const unsigned long mscl_clk_regs[] __initconst = {
3997 MUX_SEL_MSCL0,
3998 MUX_SEL_MSCL1,
3999 MUX_ENABLE_MSCL0,
4000 MUX_ENABLE_MSCL1,
4001 DIV_MSCL,
4002 ENABLE_ACLK_MSCL,
4003 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4004 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4005 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4006 ENABLE_PCLK_MSCL,
4007 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4008 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4009 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4010 ENABLE_SCLK_MSCL,
4011 ENABLE_IP_MSCL0,
4012 ENABLE_IP_MSCL1,
4013 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
4014 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
4015 ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
4016 };
4017
4018 static const struct samsung_clk_reg_dump mscl_suspend_regs[] = {
4019 { MUX_SEL_MSCL0, 0 },
4020 { MUX_SEL_MSCL1, 0 },
4021 };
4022
4023 /* list of all parent clock list */
4024 PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
4025 PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
4026 PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
4027 "mout_aclk_mscl_400_user", };
4028
4029 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
4030 /* MUX_SEL_MSCL0 */
4031 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
4032 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
4033 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
4034 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
4035
4036 /* MUX_SEL_MSCL1 */
4037 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
4038 MUX_SEL_MSCL1, 0, 1),
4039 };
4040
4041 static const struct samsung_div_clock mscl_div_clks[] __initconst = {
4042 /* DIV_MSCL */
4043 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
4044 DIV_MSCL, 0, 3),
4045 };
4046
4047 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
4048 /* ENABLE_ACLK_MSCL */
4049 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
4050 ENABLE_ACLK_MSCL, 9, 0, 0),
4051 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
4052 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
4053 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
4054 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
4055 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
4056 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
4057 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
4058 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
4059 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
4060 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4061 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
4062 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4063 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
4064 ENABLE_ACLK_MSCL, 2, 0, 0),
4065 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
4066 ENABLE_ACLK_MSCL, 1, 0, 0),
4067 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
4068 ENABLE_ACLK_MSCL, 0, 0, 0),
4069
4070 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4071 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
4072 "mout_aclk_mscl_400_user",
4073 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4074 0, CLK_IGNORE_UNUSED, 0),
4075
4076 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4077 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
4078 "mout_aclk_mscl_400_user",
4079 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4080 0, CLK_IGNORE_UNUSED, 0),
4081
4082 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
4083 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
4084 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4085 0, CLK_IGNORE_UNUSED, 0),
4086
4087 /* ENABLE_PCLK_MSCL */
4088 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
4089 ENABLE_PCLK_MSCL, 7, 0, 0),
4090 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
4091 ENABLE_PCLK_MSCL, 6, 0, 0),
4092 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
4093 ENABLE_PCLK_MSCL, 5, 0, 0),
4094 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
4095 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4096 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
4097 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4098 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
4099 ENABLE_PCLK_MSCL, 2, 0, 0),
4100 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
4101 ENABLE_PCLK_MSCL, 1, 0, 0),
4102 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
4103 ENABLE_PCLK_MSCL, 0, 0, 0),
4104
4105 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4106 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
4107 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4108 0, CLK_IGNORE_UNUSED, 0),
4109
4110 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4111 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
4112 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4113 0, CLK_IGNORE_UNUSED, 0),
4114
4115 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
4116 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
4117 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4118 0, CLK_IGNORE_UNUSED, 0),
4119
4120 /* ENABLE_SCLK_MSCL */
4121 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4122 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4123 };
4124
4125 static const struct samsung_cmu_info mscl_cmu_info __initconst = {
4126 .mux_clks = mscl_mux_clks,
4127 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
4128 .div_clks = mscl_div_clks,
4129 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
4130 .gate_clks = mscl_gate_clks,
4131 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
4132 .nr_clk_ids = MSCL_NR_CLK,
4133 .clk_regs = mscl_clk_regs,
4134 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
4135 .suspend_regs = mscl_suspend_regs,
4136 .nr_suspend_regs = ARRAY_SIZE(mscl_suspend_regs),
4137 .clk_name = "aclk_mscl_400",
4138 };
4139
4140 /*
4141 * Register offset definitions for CMU_MFC
4142 */
4143 #define MUX_SEL_MFC 0x0200
4144 #define MUX_ENABLE_MFC 0x0300
4145 #define MUX_STAT_MFC 0x0400
4146 #define DIV_MFC 0x0600
4147 #define DIV_STAT_MFC 0x0700
4148 #define ENABLE_ACLK_MFC 0x0800
4149 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4150 #define ENABLE_PCLK_MFC 0x0900
4151 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4152 #define ENABLE_IP_MFC0 0x0b00
4153 #define ENABLE_IP_MFC1 0x0b04
4154 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4155
4156 static const unsigned long mfc_clk_regs[] __initconst = {
4157 MUX_SEL_MFC,
4158 MUX_ENABLE_MFC,
4159 DIV_MFC,
4160 ENABLE_ACLK_MFC,
4161 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4162 ENABLE_PCLK_MFC,
4163 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4164 ENABLE_IP_MFC0,
4165 ENABLE_IP_MFC1,
4166 ENABLE_IP_MFC_SECURE_SMMU_MFC,
4167 };
4168
4169 static const struct samsung_clk_reg_dump mfc_suspend_regs[] = {
4170 { MUX_SEL_MFC, 0 },
4171 };
4172
4173 PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4174
4175 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
4176 /* MUX_SEL_MFC */
4177 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4178 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4179 };
4180
4181 static const struct samsung_div_clock mfc_div_clks[] __initconst = {
4182 /* DIV_MFC */
4183 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4184 DIV_MFC, 0, 2),
4185 };
4186
4187 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
4188 /* ENABLE_ACLK_MFC */
4189 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4190 ENABLE_ACLK_MFC, 6, 0, 0),
4191 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4192 ENABLE_ACLK_MFC, 5, 0, 0),
4193 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4194 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4195 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4196 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4197 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4198 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4199 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4200 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4201 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4202 ENABLE_ACLK_MFC, 0, 0, 0),
4203
4204 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4205 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4206 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4207 1, CLK_IGNORE_UNUSED, 0),
4208 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4209 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4210 0, CLK_IGNORE_UNUSED, 0),
4211
4212 /* ENABLE_PCLK_MFC */
4213 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4214 ENABLE_PCLK_MFC, 4, 0, 0),
4215 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4216 ENABLE_PCLK_MFC, 3, 0, 0),
4217 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4218 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4219 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4220 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4221 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4222 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4223
4224 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4225 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4226 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4227 1, CLK_IGNORE_UNUSED, 0),
4228 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4229 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4230 0, CLK_IGNORE_UNUSED, 0),
4231 };
4232
4233 static const struct samsung_cmu_info mfc_cmu_info __initconst = {
4234 .mux_clks = mfc_mux_clks,
4235 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
4236 .div_clks = mfc_div_clks,
4237 .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
4238 .gate_clks = mfc_gate_clks,
4239 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
4240 .nr_clk_ids = MFC_NR_CLK,
4241 .clk_regs = mfc_clk_regs,
4242 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
4243 .suspend_regs = mfc_suspend_regs,
4244 .nr_suspend_regs = ARRAY_SIZE(mfc_suspend_regs),
4245 .clk_name = "aclk_mfc_400",
4246 };
4247
4248 /*
4249 * Register offset definitions for CMU_HEVC
4250 */
4251 #define MUX_SEL_HEVC 0x0200
4252 #define MUX_ENABLE_HEVC 0x0300
4253 #define MUX_STAT_HEVC 0x0400
4254 #define DIV_HEVC 0x0600
4255 #define DIV_STAT_HEVC 0x0700
4256 #define ENABLE_ACLK_HEVC 0x0800
4257 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4258 #define ENABLE_PCLK_HEVC 0x0900
4259 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4260 #define ENABLE_IP_HEVC0 0x0b00
4261 #define ENABLE_IP_HEVC1 0x0b04
4262 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4263
4264 static const unsigned long hevc_clk_regs[] __initconst = {
4265 MUX_SEL_HEVC,
4266 MUX_ENABLE_HEVC,
4267 DIV_HEVC,
4268 ENABLE_ACLK_HEVC,
4269 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4270 ENABLE_PCLK_HEVC,
4271 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4272 ENABLE_IP_HEVC0,
4273 ENABLE_IP_HEVC1,
4274 ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4275 };
4276
4277 static const struct samsung_clk_reg_dump hevc_suspend_regs[] = {
4278 { MUX_SEL_HEVC, 0 },
4279 };
4280
4281 PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
4282
4283 static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
4284 /* MUX_SEL_HEVC */
4285 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4286 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4287 };
4288
4289 static const struct samsung_div_clock hevc_div_clks[] __initconst = {
4290 /* DIV_HEVC */
4291 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4292 DIV_HEVC, 0, 2),
4293 };
4294
4295 static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
4296 /* ENABLE_ACLK_HEVC */
4297 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4298 ENABLE_ACLK_HEVC, 6, 0, 0),
4299 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4300 ENABLE_ACLK_HEVC, 5, 0, 0),
4301 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4302 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4303 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4304 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4305 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4306 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4307 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4308 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4309 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4310 ENABLE_ACLK_HEVC, 0, 0, 0),
4311
4312 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4313 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4314 "mout_aclk_hevc_400_user",
4315 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4316 1, CLK_IGNORE_UNUSED, 0),
4317 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4318 "mout_aclk_hevc_400_user",
4319 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4320 0, CLK_IGNORE_UNUSED, 0),
4321
4322 /* ENABLE_PCLK_HEVC */
4323 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4324 ENABLE_PCLK_HEVC, 4, 0, 0),
4325 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4326 ENABLE_PCLK_HEVC, 3, 0, 0),
4327 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4328 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4329 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4330 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4331 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4332 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4333
4334 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4335 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4336 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4337 1, CLK_IGNORE_UNUSED, 0),
4338 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4339 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4340 0, CLK_IGNORE_UNUSED, 0),
4341 };
4342
4343 static const struct samsung_cmu_info hevc_cmu_info __initconst = {
4344 .mux_clks = hevc_mux_clks,
4345 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
4346 .div_clks = hevc_div_clks,
4347 .nr_div_clks = ARRAY_SIZE(hevc_div_clks),
4348 .gate_clks = hevc_gate_clks,
4349 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
4350 .nr_clk_ids = HEVC_NR_CLK,
4351 .clk_regs = hevc_clk_regs,
4352 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
4353 .suspend_regs = hevc_suspend_regs,
4354 .nr_suspend_regs = ARRAY_SIZE(hevc_suspend_regs),
4355 .clk_name = "aclk_hevc_400",
4356 };
4357
4358 /*
4359 * Register offset definitions for CMU_ISP
4360 */
4361 #define MUX_SEL_ISP 0x0200
4362 #define MUX_ENABLE_ISP 0x0300
4363 #define MUX_STAT_ISP 0x0400
4364 #define DIV_ISP 0x0600
4365 #define DIV_STAT_ISP 0x0700
4366 #define ENABLE_ACLK_ISP0 0x0800
4367 #define ENABLE_ACLK_ISP1 0x0804
4368 #define ENABLE_ACLK_ISP2 0x0808
4369 #define ENABLE_PCLK_ISP 0x0900
4370 #define ENABLE_SCLK_ISP 0x0a00
4371 #define ENABLE_IP_ISP0 0x0b00
4372 #define ENABLE_IP_ISP1 0x0b04
4373 #define ENABLE_IP_ISP2 0x0b08
4374 #define ENABLE_IP_ISP3 0x0b0c
4375
4376 static const unsigned long isp_clk_regs[] __initconst = {
4377 MUX_SEL_ISP,
4378 MUX_ENABLE_ISP,
4379 DIV_ISP,
4380 ENABLE_ACLK_ISP0,
4381 ENABLE_ACLK_ISP1,
4382 ENABLE_ACLK_ISP2,
4383 ENABLE_PCLK_ISP,
4384 ENABLE_SCLK_ISP,
4385 ENABLE_IP_ISP0,
4386 ENABLE_IP_ISP1,
4387 ENABLE_IP_ISP2,
4388 ENABLE_IP_ISP3,
4389 };
4390
4391 static const struct samsung_clk_reg_dump isp_suspend_regs[] = {
4392 { MUX_SEL_ISP, 0 },
4393 };
4394
4395 PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
4396 PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
4397
4398 static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
4399 /* MUX_SEL_ISP */
4400 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4401 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4402 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4403 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4404 };
4405
4406 static const struct samsung_div_clock isp_div_clks[] __initconst = {
4407 /* DIV_ISP */
4408 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4409 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4410 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4411 DIV_ISP, 8, 3),
4412 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4413 "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4414 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4415 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4416 };
4417
4418 static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
4419 /* ENABLE_ACLK_ISP0 */
4420 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4421 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4422 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4423 ENABLE_ACLK_ISP0, 5, 0, 0),
4424 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4425 ENABLE_ACLK_ISP0, 4, 0, 0),
4426 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4427 ENABLE_ACLK_ISP0, 3, 0, 0),
4428 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4429 ENABLE_ACLK_ISP0, 2, 0, 0),
4430 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4431 ENABLE_ACLK_ISP0, 1, 0, 0),
4432 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4433 ENABLE_ACLK_ISP0, 0, 0, 0),
4434
4435 /* ENABLE_ACLK_ISP1 */
4436 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4437 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4438 17, CLK_IGNORE_UNUSED, 0),
4439 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4440 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4441 16, CLK_IGNORE_UNUSED, 0),
4442 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4443 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4444 15, CLK_IGNORE_UNUSED, 0),
4445 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4446 "div_pclk_isp", ENABLE_ACLK_ISP1,
4447 14, CLK_IGNORE_UNUSED, 0),
4448 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4449 "div_pclk_isp", ENABLE_ACLK_ISP1,
4450 13, CLK_IGNORE_UNUSED, 0),
4451 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4452 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4453 12, CLK_IGNORE_UNUSED, 0),
4454 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4455 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4456 11, CLK_IGNORE_UNUSED, 0),
4457 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4458 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4459 10, CLK_IGNORE_UNUSED, 0),
4460 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4461 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4462 9, CLK_IGNORE_UNUSED, 0),
4463 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4464 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4465 8, CLK_IGNORE_UNUSED, 0),
4466 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4467 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4468 7, CLK_IGNORE_UNUSED, 0),
4469 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4470 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4471 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4472 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4473 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4474 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4475 4, CLK_IGNORE_UNUSED, 0),
4476 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4477 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4478 3, CLK_IGNORE_UNUSED, 0),
4479 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4480 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4481 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4482 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4483 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4484 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4485
4486 /* ENABLE_ACLK_ISP2 */
4487 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4488 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4489 13, CLK_IGNORE_UNUSED, 0),
4490 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4491 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4492 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4493 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4494 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4495 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4496 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4497 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4498 9, CLK_IGNORE_UNUSED, 0),
4499 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4500 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4501 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4502 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4503 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4504 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4505 6, CLK_IGNORE_UNUSED, 0),
4506 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4507 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4508 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4509 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4510 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4511 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4512 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4513 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4514 2, CLK_IGNORE_UNUSED, 0),
4515 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4516 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4517 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4518 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4519
4520 /* ENABLE_PCLK_ISP */
4521 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4522 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4523 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4524 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4525 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4526 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4527 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4528 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4529 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4530 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4531 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4532 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4533 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4534 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4535 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4536 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4537 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4538 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4539 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4540 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4541 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4542 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4543 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4544 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4545 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4546 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4547 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4548 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4549 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4550 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4551 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4552 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4553 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4554 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4555 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4556 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4557 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4558 "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4559 7, CLK_IGNORE_UNUSED, 0),
4560 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4561 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4562 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4563 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4564 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4565 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4566 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4567 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4568 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4569 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4570 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4571 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4572 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4573 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4574
4575 /* ENABLE_SCLK_ISP */
4576 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4577 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4578 5, CLK_IGNORE_UNUSED, 0),
4579 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4580 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4581 4, CLK_IGNORE_UNUSED, 0),
4582 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4583 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4584 3, CLK_IGNORE_UNUSED, 0),
4585 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4586 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4587 2, CLK_IGNORE_UNUSED, 0),
4588 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4589 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4590 1, CLK_IGNORE_UNUSED, 0),
4591 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4592 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4593 0, CLK_IGNORE_UNUSED, 0),
4594 };
4595
4596 static const struct samsung_cmu_info isp_cmu_info __initconst = {
4597 .mux_clks = isp_mux_clks,
4598 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
4599 .div_clks = isp_div_clks,
4600 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
4601 .gate_clks = isp_gate_clks,
4602 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
4603 .nr_clk_ids = ISP_NR_CLK,
4604 .clk_regs = isp_clk_regs,
4605 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
4606 .suspend_regs = isp_suspend_regs,
4607 .nr_suspend_regs = ARRAY_SIZE(isp_suspend_regs),
4608 .clk_name = "aclk_isp_400",
4609 };
4610
4611 /*
4612 * Register offset definitions for CMU_CAM0
4613 */
4614 #define MUX_SEL_CAM00 0x0200
4615 #define MUX_SEL_CAM01 0x0204
4616 #define MUX_SEL_CAM02 0x0208
4617 #define MUX_SEL_CAM03 0x020c
4618 #define MUX_SEL_CAM04 0x0210
4619 #define MUX_ENABLE_CAM00 0x0300
4620 #define MUX_ENABLE_CAM01 0x0304
4621 #define MUX_ENABLE_CAM02 0x0308
4622 #define MUX_ENABLE_CAM03 0x030c
4623 #define MUX_ENABLE_CAM04 0x0310
4624 #define MUX_STAT_CAM00 0x0400
4625 #define MUX_STAT_CAM01 0x0404
4626 #define MUX_STAT_CAM02 0x0408
4627 #define MUX_STAT_CAM03 0x040c
4628 #define MUX_STAT_CAM04 0x0410
4629 #define MUX_IGNORE_CAM01 0x0504
4630 #define DIV_CAM00 0x0600
4631 #define DIV_CAM01 0x0604
4632 #define DIV_CAM02 0x0608
4633 #define DIV_CAM03 0x060c
4634 #define DIV_STAT_CAM00 0x0700
4635 #define DIV_STAT_CAM01 0x0704
4636 #define DIV_STAT_CAM02 0x0708
4637 #define DIV_STAT_CAM03 0x070c
4638 #define ENABLE_ACLK_CAM00 0X0800
4639 #define ENABLE_ACLK_CAM01 0X0804
4640 #define ENABLE_ACLK_CAM02 0X0808
4641 #define ENABLE_PCLK_CAM0 0X0900
4642 #define ENABLE_SCLK_CAM0 0X0a00
4643 #define ENABLE_IP_CAM00 0X0b00
4644 #define ENABLE_IP_CAM01 0X0b04
4645 #define ENABLE_IP_CAM02 0X0b08
4646 #define ENABLE_IP_CAM03 0X0b0C
4647
4648 static const unsigned long cam0_clk_regs[] __initconst = {
4649 MUX_SEL_CAM00,
4650 MUX_SEL_CAM01,
4651 MUX_SEL_CAM02,
4652 MUX_SEL_CAM03,
4653 MUX_SEL_CAM04,
4654 MUX_ENABLE_CAM00,
4655 MUX_ENABLE_CAM01,
4656 MUX_ENABLE_CAM02,
4657 MUX_ENABLE_CAM03,
4658 MUX_ENABLE_CAM04,
4659 MUX_IGNORE_CAM01,
4660 DIV_CAM00,
4661 DIV_CAM01,
4662 DIV_CAM02,
4663 DIV_CAM03,
4664 ENABLE_ACLK_CAM00,
4665 ENABLE_ACLK_CAM01,
4666 ENABLE_ACLK_CAM02,
4667 ENABLE_PCLK_CAM0,
4668 ENABLE_SCLK_CAM0,
4669 ENABLE_IP_CAM00,
4670 ENABLE_IP_CAM01,
4671 ENABLE_IP_CAM02,
4672 ENABLE_IP_CAM03,
4673 };
4674
4675 static const struct samsung_clk_reg_dump cam0_suspend_regs[] = {
4676 { MUX_SEL_CAM00, 0 },
4677 { MUX_SEL_CAM01, 0 },
4678 { MUX_SEL_CAM02, 0 },
4679 { MUX_SEL_CAM03, 0 },
4680 { MUX_SEL_CAM04, 0 },
4681 };
4682
4683 PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", };
4684 PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", };
4685 PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", };
4686
4687 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
4688 "phyclk_rxbyteclkhs0_s4_phy", };
4689 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
4690 "phyclk_rxbyteclkhs0_s2a_phy", };
4691
4692 PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a",
4693 "mout_aclk_cam0_333_user", };
4694 PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user",
4695 "mout_aclk_cam0_400_user", };
4696 PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a",
4697 "mout_aclk_cam0_333_user", };
4698 PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user",
4699 "mout_aclk_cam0_400_user", };
4700 PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a",
4701 "mout_aclk_cam0_333_user", };
4702 PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user",
4703 "mout_aclk_cam0_400_user", };
4704 PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user",
4705 "mout_aclk_cam0_333_user", };
4706
4707 PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a",
4708 "mout_aclk_cam0_333_user" };
4709 PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user",
4710 "mout_aclk_cam0_400_user", };
4711 PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a",
4712 "mout_aclk_cam0_333_user", };
4713 PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user",
4714 "mout_aclk-cam0_400_user", };
4715 PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a",
4716 "mout_aclk_cam0_333_user", };
4717 PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user",
4718 "mout_aclk_cam0_400_user", };
4719 PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a",
4720 "mout_aclk_cam0_333_user", };
4721 PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user",
4722 "mout_aclk_cam0_400_user", };
4723
4724 PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b",
4725 "div_pclk_lite_d", };
4726 PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a",
4727 "div_pclk_pixelasync_lite_c", };
4728 PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a",
4729 "div_pclk_lite_b", };
4730 PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a",
4731 "mout_aclk_cam0_333_user", };
4732 PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user",
4733 "mout_aclk_cam0_400_user", };
4734 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
4735 "mout_sclk_pixelasync_lite_c_init_a",
4736 "mout_aclk_cam0_400_user", };
4737 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4738 "mout_aclk_cam0_552_user",
4739 "mout_aclk_cam0_400_user", };
4740
4741 static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
4742 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4743 NULL, 0, 100000000),
4744 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4745 NULL, 0, 100000000),
4746 };
4747
4748 static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
4749 /* MUX_SEL_CAM00 */
4750 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4751 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
4752 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
4753 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
4754 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
4755 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4756
4757 /* MUX_SEL_CAM01 */
4758 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4759 "mout_phyclk_rxbyteclkhs0_s4_user",
4760 mout_phyclk_rxbyteclkhs0_s4_user_p,
4761 MUX_SEL_CAM01, 4, 1),
4762 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
4763 "mout_phyclk_rxbyteclkhs0_s2a_user",
4764 mout_phyclk_rxbyteclkhs0_s2a_user_p,
4765 MUX_SEL_CAM01, 0, 1),
4766
4767 /* MUX_SEL_CAM02 */
4768 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
4769 MUX_SEL_CAM02, 24, 1),
4770 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
4771 MUX_SEL_CAM02, 20, 1),
4772 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
4773 MUX_SEL_CAM02, 16, 1),
4774 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
4775 MUX_SEL_CAM02, 12, 1),
4776 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
4777 MUX_SEL_CAM02, 8, 1),
4778 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
4779 MUX_SEL_CAM02, 4, 1),
4780 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
4781 MUX_SEL_CAM02, 0, 1),
4782
4783 /* MUX_SEL_CAM03 */
4784 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
4785 MUX_SEL_CAM03, 28, 1),
4786 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
4787 MUX_SEL_CAM03, 24, 1),
4788 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
4789 MUX_SEL_CAM03, 20, 1),
4790 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
4791 MUX_SEL_CAM03, 16, 1),
4792 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
4793 MUX_SEL_CAM03, 12, 1),
4794 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
4795 MUX_SEL_CAM03, 8, 1),
4796 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
4797 MUX_SEL_CAM03, 4, 1),
4798 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
4799 MUX_SEL_CAM03, 0, 1),
4800
4801 /* MUX_SEL_CAM04 */
4802 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4803 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4804 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4805 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
4806 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4807 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
4808 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4809 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
4810 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4811 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
4812 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4813 "mout_sclk_pixelasync_lite_c_init_b",
4814 mout_sclk_pixelasync_lite_c_init_b_p,
4815 MUX_SEL_CAM04, 4, 1),
4816 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4817 "mout_sclk_pixelasync_lite_c_init_a",
4818 mout_sclk_pixelasync_lite_c_init_a_p,
4819 MUX_SEL_CAM04, 0, 1),
4820 };
4821
4822 static const struct samsung_div_clock cam0_div_clks[] __initconst = {
4823 /* DIV_CAM00 */
4824 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4825 DIV_CAM00, 8, 2),
4826 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4827 DIV_CAM00, 4, 3),
4828 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
4829 "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4830
4831 /* DIV_CAM01 */
4832 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
4833 DIV_CAM01, 20, 2),
4834 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4835 DIV_CAM01, 16, 3),
4836 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
4837 DIV_CAM01, 12, 2),
4838 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4839 DIV_CAM01, 8, 3),
4840 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
4841 DIV_CAM01, 4, 2),
4842 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4843 DIV_CAM01, 0, 3),
4844
4845 /* DIV_CAM02 */
4846 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
4847 DIV_CAM02, 20, 3),
4848 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
4849 DIV_CAM02, 16, 3),
4850 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
4851 DIV_CAM02, 12, 2),
4852 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4853 DIV_CAM02, 8, 3),
4854 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
4855 DIV_CAM02, 4, 2),
4856 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4857 DIV_CAM02, 0, 3),
4858
4859 /* DIV_CAM03 */
4860 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
4861 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
4862 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
4863 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
4864 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
4865 "div_sclk_pixelasync_lite_c_init",
4866 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4867 };
4868
4869 static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
4870 /* ENABLE_ACLK_CAM00 */
4871 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4872 6, 0, 0),
4873 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
4874 5, 0, 0),
4875 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4876 4, 0, 0),
4877 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
4878 3, 0, 0),
4879 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
4880 ENABLE_ACLK_CAM00, 2, 0, 0),
4881 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
4882 ENABLE_ACLK_CAM00, 1, 0, 0),
4883 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
4884 ENABLE_ACLK_CAM00, 0, 0, 0),
4885
4886 /* ENABLE_ACLK_CAM01 */
4887 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4888 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4889 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4890 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4891 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4892 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4893 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4894 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4895 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4896 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4897 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4898 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4899 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4900 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4901 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4902 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4903 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
4904 "div_pclk_lite_d", ENABLE_ACLK_CAM01,
4905 23, CLK_IGNORE_UNUSED, 0),
4906 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
4907 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4908 22, CLK_IGNORE_UNUSED, 0),
4909 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
4910 "div_pclk_lite_b", ENABLE_ACLK_CAM01,
4911 21, CLK_IGNORE_UNUSED, 0),
4912 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
4913 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4914 20, CLK_IGNORE_UNUSED, 0),
4915 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
4916 "div_pclk_lite_a", ENABLE_ACLK_CAM01,
4917 19, CLK_IGNORE_UNUSED, 0),
4918 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
4919 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4920 18, CLK_IGNORE_UNUSED, 0),
4921 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
4922 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4923 17, CLK_IGNORE_UNUSED, 0),
4924 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
4925 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4926 16, CLK_IGNORE_UNUSED, 0),
4927 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
4928 "div_aclk_3aa1", ENABLE_ACLK_CAM01,
4929 15, CLK_IGNORE_UNUSED, 0),
4930 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
4931 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4932 14, CLK_IGNORE_UNUSED, 0),
4933 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
4934 "div_aclk_3aa0", ENABLE_ACLK_CAM01,
4935 13, CLK_IGNORE_UNUSED, 0),
4936 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
4937 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4938 12, CLK_IGNORE_UNUSED, 0),
4939 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
4940 "div_aclk_lite_d", ENABLE_ACLK_CAM01,
4941 11, CLK_IGNORE_UNUSED, 0),
4942 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
4943 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4944 10, CLK_IGNORE_UNUSED, 0),
4945 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
4946 "div_aclk_lite_b", ENABLE_ACLK_CAM01,
4947 9, CLK_IGNORE_UNUSED, 0),
4948 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
4949 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4950 8, CLK_IGNORE_UNUSED, 0),
4951 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
4952 "div_aclk_lite_a", ENABLE_ACLK_CAM01,
4953 7, CLK_IGNORE_UNUSED, 0),
4954 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
4955 "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
4956 6, CLK_IGNORE_UNUSED, 0),
4957 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4958 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4959 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4960 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4961 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
4962 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4963 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4964 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4965 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
4966 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4967 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4968 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4969
4970 /* ENABLE_ACLK_CAM02 */
4971 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4972 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4973 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4974 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4975 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4976 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4977 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4978 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4979 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4980 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4981 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4982 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4983 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4984 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4985 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4986 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4987 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4988 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4989 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
4990 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4991
4992 /* ENABLE_PCLK_CAM0 */
4993 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
4994 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
4995 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
4996 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
4997 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
4998 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
4999 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
5000 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
5001 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
5002 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
5003 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
5004 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
5005 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
5006 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
5007 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
5008 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
5009 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
5010 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
5011 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
5012 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
5013 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
5014 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
5015 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
5016 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
5017 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
5018 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
5019 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
5020 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5021 12, CLK_IGNORE_UNUSED, 0),
5022 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
5023 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5024 11, CLK_IGNORE_UNUSED, 0),
5025 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
5026 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5027 10, CLK_IGNORE_UNUSED, 0),
5028 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
5029 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
5030 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
5031 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
5032 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
5033 "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
5034 7, CLK_IGNORE_UNUSED, 0),
5035 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
5036 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
5037 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
5038 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
5039 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
5040 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
5041 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
5042 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
5043 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
5044 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
5045 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
5046 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
5047 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
5048 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
5049
5050 /* ENABLE_SCLK_CAM0 */
5051 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
5052 "mout_phyclk_rxbyteclkhs0_s4_user",
5053 ENABLE_SCLK_CAM0, 8, 0, 0),
5054 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
5055 "mout_phyclk_rxbyteclkhs0_s2a_user",
5056 ENABLE_SCLK_CAM0, 7, 0, 0),
5057 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
5058 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5059 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
5060 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5061 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
5062 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5063 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
5064 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5065 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
5066 "div_sclk_pixelasync_lite_c",
5067 ENABLE_SCLK_CAM0, 2, 0, 0),
5068 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
5069 "div_sclk_pixelasync_lite_c_init",
5070 ENABLE_SCLK_CAM0, 1, 0, 0),
5071 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
5072 "div_sclk_pixelasync_lite_c",
5073 ENABLE_SCLK_CAM0, 0, 0, 0),
5074 };
5075
5076 static const struct samsung_cmu_info cam0_cmu_info __initconst = {
5077 .mux_clks = cam0_mux_clks,
5078 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
5079 .div_clks = cam0_div_clks,
5080 .nr_div_clks = ARRAY_SIZE(cam0_div_clks),
5081 .gate_clks = cam0_gate_clks,
5082 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
5083 .fixed_clks = cam0_fixed_clks,
5084 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
5085 .nr_clk_ids = CAM0_NR_CLK,
5086 .clk_regs = cam0_clk_regs,
5087 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
5088 .suspend_regs = cam0_suspend_regs,
5089 .nr_suspend_regs = ARRAY_SIZE(cam0_suspend_regs),
5090 .clk_name = "aclk_cam0_400",
5091 };
5092
5093 /*
5094 * Register offset definitions for CMU_CAM1
5095 */
5096 #define MUX_SEL_CAM10 0x0200
5097 #define MUX_SEL_CAM11 0x0204
5098 #define MUX_SEL_CAM12 0x0208
5099 #define MUX_ENABLE_CAM10 0x0300
5100 #define MUX_ENABLE_CAM11 0x0304
5101 #define MUX_ENABLE_CAM12 0x0308
5102 #define MUX_STAT_CAM10 0x0400
5103 #define MUX_STAT_CAM11 0x0404
5104 #define MUX_STAT_CAM12 0x0408
5105 #define MUX_IGNORE_CAM11 0x0504
5106 #define DIV_CAM10 0x0600
5107 #define DIV_CAM11 0x0604
5108 #define DIV_STAT_CAM10 0x0700
5109 #define DIV_STAT_CAM11 0x0704
5110 #define ENABLE_ACLK_CAM10 0X0800
5111 #define ENABLE_ACLK_CAM11 0X0804
5112 #define ENABLE_ACLK_CAM12 0X0808
5113 #define ENABLE_PCLK_CAM1 0X0900
5114 #define ENABLE_SCLK_CAM1 0X0a00
5115 #define ENABLE_IP_CAM10 0X0b00
5116 #define ENABLE_IP_CAM11 0X0b04
5117 #define ENABLE_IP_CAM12 0X0b08
5118
5119 static const unsigned long cam1_clk_regs[] __initconst = {
5120 MUX_SEL_CAM10,
5121 MUX_SEL_CAM11,
5122 MUX_SEL_CAM12,
5123 MUX_ENABLE_CAM10,
5124 MUX_ENABLE_CAM11,
5125 MUX_ENABLE_CAM12,
5126 MUX_IGNORE_CAM11,
5127 DIV_CAM10,
5128 DIV_CAM11,
5129 ENABLE_ACLK_CAM10,
5130 ENABLE_ACLK_CAM11,
5131 ENABLE_ACLK_CAM12,
5132 ENABLE_PCLK_CAM1,
5133 ENABLE_SCLK_CAM1,
5134 ENABLE_IP_CAM10,
5135 ENABLE_IP_CAM11,
5136 ENABLE_IP_CAM12,
5137 };
5138
5139 static const struct samsung_clk_reg_dump cam1_suspend_regs[] = {
5140 { MUX_SEL_CAM10, 0 },
5141 { MUX_SEL_CAM11, 0 },
5142 { MUX_SEL_CAM12, 0 },
5143 };
5144
5145 PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", };
5146 PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", };
5147 PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", };
5148
5149 PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", };
5150 PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", };
5151 PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", };
5152
5153 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
5154 "phyclk_rxbyteclkhs0_s2b_phy", };
5155
5156 PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a",
5157 "mout_aclk_cam1_333_user", };
5158 PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user",
5159 "mout_aclk_cam1_400_user", };
5160
5161 PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a",
5162 "mout_aclk_cam1_333_user", };
5163 PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user",
5164 "mout_aclk_cam1_400_user", };
5165
5166 PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
5167 "mout_aclk_cam1_333_user", };
5168 PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
5169 "mout_aclk_cam1_400_user", };
5170
5171 static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
5172 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5173 0, 100000000),
5174 };
5175
5176 static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
5177 /* MUX_SEL_CAM10 */
5178 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5179 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
5180 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
5181 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
5182 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
5183 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
5184 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
5185 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
5186 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
5187 mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
5188 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
5189 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
5190
5191 /* MUX_SEL_CAM11 */
5192 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
5193 "mout_phyclk_rxbyteclkhs0_s2b_user",
5194 mout_phyclk_rxbyteclkhs0_s2b_user_p,
5195 MUX_SEL_CAM11, 0, 1),
5196
5197 /* MUX_SEL_CAM12 */
5198 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
5199 MUX_SEL_CAM12, 20, 1),
5200 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
5201 MUX_SEL_CAM12, 16, 1),
5202 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
5203 MUX_SEL_CAM12, 12, 1),
5204 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
5205 MUX_SEL_CAM12, 8, 1),
5206 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
5207 MUX_SEL_CAM12, 4, 1),
5208 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
5209 MUX_SEL_CAM12, 0, 1),
5210 };
5211
5212 static const struct samsung_div_clock cam1_div_clks[] __initconst = {
5213 /* DIV_CAM10 */
5214 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
5215 "div_pclk_cam1_83", DIV_CAM10, 16, 2),
5216 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
5217 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
5218 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
5219 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
5220 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
5221 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
5222 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5223 DIV_CAM10, 0, 3),
5224
5225 /* DIV_CAM11 */
5226 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
5227 DIV_CAM11, 16, 3),
5228 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
5229 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
5230 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
5231 DIV_CAM11, 4, 2),
5232 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5233 DIV_CAM11, 0, 3),
5234 };
5235
5236 static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
5237 /* ENABLE_ACLK_CAM10 */
5238 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5239 ENABLE_ACLK_CAM10, 4, 0, 0),
5240 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
5241 ENABLE_ACLK_CAM10, 3, 0, 0),
5242 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
5243 ENABLE_ACLK_CAM10, 1, 0, 0),
5244 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
5245 ENABLE_ACLK_CAM10, 0, 0, 0),
5246
5247 /* ENABLE_ACLK_CAM11 */
5248 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
5249 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5250 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5251 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5252 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
5253 "div_pclk_lite_c", ENABLE_ACLK_CAM11,
5254 27, CLK_IGNORE_UNUSED, 0),
5255 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
5256 "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
5257 26, CLK_IGNORE_UNUSED, 0),
5258 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
5259 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5260 25, CLK_IGNORE_UNUSED, 0),
5261 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
5262 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5263 24, CLK_IGNORE_UNUSED, 0),
5264 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
5265 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5266 23, CLK_IGNORE_UNUSED, 0),
5267 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
5268 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
5269 22, CLK_IGNORE_UNUSED, 0),
5270 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
5271 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5272 21, CLK_IGNORE_UNUSED, 0),
5273 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
5274 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5275 20, CLK_IGNORE_UNUSED, 0),
5276 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
5277 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5278 19, CLK_IGNORE_UNUSED, 0),
5279 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
5280 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5281 18, CLK_IGNORE_UNUSED, 0),
5282 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
5283 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5284 17, CLK_IGNORE_UNUSED, 0),
5285 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
5286 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5287 16, CLK_IGNORE_UNUSED, 0),
5288 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
5289 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5290 15, CLK_IGNORE_UNUSED, 0),
5291 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
5292 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5293 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
5294 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5295 13, CLK_IGNORE_UNUSED, 0),
5296 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
5297 "div_aclk_lite_c", ENABLE_ACLK_CAM11,
5298 12, CLK_IGNORE_UNUSED, 0),
5299 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5300 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5301 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5302 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5303 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
5304 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5305 9, CLK_IGNORE_UNUSED, 0),
5306 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5307 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5308 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5309 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5310 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5311 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5312 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5313 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5314 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5315 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5316 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5317 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5318 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5319 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5320 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5321 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5322 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5323 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5324
5325 /* ENABLE_ACLK_CAM12 */
5326 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
5327 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5328 10, CLK_IGNORE_UNUSED, 0),
5329 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5330 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5331 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
5332 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5333 8, CLK_IGNORE_UNUSED, 0),
5334 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5335 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5336 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5337 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5338 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5339 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5340 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
5341 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5342 4, CLK_IGNORE_UNUSED, 0),
5343 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
5344 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5345 3, CLK_IGNORE_UNUSED, 0),
5346 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
5347 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5348 2, CLK_IGNORE_UNUSED, 0),
5349 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5350 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5351 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
5352 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5353 0, CLK_IGNORE_UNUSED, 0),
5354
5355 /* ENABLE_PCLK_CAM1 */
5356 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5357 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5358 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
5359 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5360 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5361 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5362 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
5363 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5364 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
5365 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5366 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
5367 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5368 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5369 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5370 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
5371 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5372 20, CLK_IGNORE_UNUSED, 0),
5373 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
5374 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5375 19, CLK_IGNORE_UNUSED, 0),
5376 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5377 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5378 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
5379 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5380 17, CLK_IGNORE_UNUSED, 0),
5381 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
5382 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5383 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5384 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5385 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
5386 "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
5387 14, CLK_IGNORE_UNUSED, 0),
5388 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
5389 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5390 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
5391 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5392 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
5393 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5394 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
5395 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5396 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5397 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5398 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
5399 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5400 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
5401 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5402 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
5403 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5404 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
5405 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5406 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
5407 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5408 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83",
5409 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5410 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
5411 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5412 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
5413 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5414 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
5415 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5416
5417 /* ENABLE_SCLK_CAM1 */
5418 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
5419 15, 0, 0),
5420 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
5421 14, 0, 0),
5422 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
5423 13, 0, 0),
5424 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
5425 12, 0, 0),
5426 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
5427 "mout_phyclk_rxbyteclkhs0_s2b_user",
5428 ENABLE_SCLK_CAM1, 11, 0, 0),
5429 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5430 ENABLE_SCLK_CAM1, 10, 0, 0),
5431 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
5432 ENABLE_SCLK_CAM1, 9, 0, 0),
5433 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5434 ENABLE_SCLK_CAM1, 7, 0, 0),
5435 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5436 ENABLE_SCLK_CAM1, 6, 0, 0),
5437 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5438 ENABLE_SCLK_CAM1, 5, 0, 0),
5439 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5440 ENABLE_SCLK_CAM1, 4, 0, 0),
5441 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
5442 ENABLE_SCLK_CAM1, 3, 0, 0),
5443 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5444 ENABLE_SCLK_CAM1, 2, 0, 0),
5445 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
5446 ENABLE_SCLK_CAM1, 1, 0, 0),
5447 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5448 ENABLE_SCLK_CAM1, 0, 0, 0),
5449 };
5450
5451 static const struct samsung_cmu_info cam1_cmu_info __initconst = {
5452 .mux_clks = cam1_mux_clks,
5453 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
5454 .div_clks = cam1_div_clks,
5455 .nr_div_clks = ARRAY_SIZE(cam1_div_clks),
5456 .gate_clks = cam1_gate_clks,
5457 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
5458 .fixed_clks = cam1_fixed_clks,
5459 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
5460 .nr_clk_ids = CAM1_NR_CLK,
5461 .clk_regs = cam1_clk_regs,
5462 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
5463 .suspend_regs = cam1_suspend_regs,
5464 .nr_suspend_regs = ARRAY_SIZE(cam1_suspend_regs),
5465 .clk_name = "aclk_cam1_400",
5466 };
5467
5468 /*
5469 * Register offset definitions for CMU_IMEM
5470 */
5471 #define ENABLE_ACLK_IMEM_SLIMSSS 0x080c
5472 #define ENABLE_PCLK_IMEM_SLIMSSS 0x0908
5473
5474 static const unsigned long imem_clk_regs[] __initconst = {
5475 ENABLE_ACLK_IMEM_SLIMSSS,
5476 ENABLE_PCLK_IMEM_SLIMSSS,
5477 };
5478
5479 static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
5480 /* ENABLE_ACLK_IMEM_SLIMSSS */
5481 GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266",
5482 ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5483
5484 /* ENABLE_PCLK_IMEM_SLIMSSS */
5485 GATE(CLK_PCLK_SLIMSSS, "pclk_slimsss", "aclk_imem_200",
5486 ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5487 };
5488
5489 static const struct samsung_cmu_info imem_cmu_info __initconst = {
5490 .gate_clks = imem_gate_clks,
5491 .nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
5492 .nr_clk_ids = IMEM_NR_CLK,
5493 .clk_regs = imem_clk_regs,
5494 .nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
5495 .clk_name = "aclk_imem_200",
5496 };
5497
5498 struct exynos5433_cmu_data {
5499 struct samsung_clk_reg_dump *clk_save;
5500 unsigned int nr_clk_save;
5501 const struct samsung_clk_reg_dump *clk_suspend;
5502 unsigned int nr_clk_suspend;
5503
5504 struct clk *clk;
5505 struct clk **pclks;
5506 int nr_pclks;
5507
5508 /* must be the last entry */
5509 struct samsung_clk_provider ctx;
5510 };
5511
5512 static int __maybe_unused exynos5433_cmu_suspend(struct device *dev)
5513 {
5514 struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
5515 int i;
5516
5517 samsung_clk_save(data->ctx.reg_base, data->clk_save,
5518 data->nr_clk_save);
5519
5520 for (i = 0; i < data->nr_pclks; i++)
5521 clk_prepare_enable(data->pclks[i]);
5522
5523 /* for suspend some registers have to be set to certain values */
5524 samsung_clk_restore(data->ctx.reg_base, data->clk_suspend,
5525 data->nr_clk_suspend);
5526
5527 for (i = 0; i < data->nr_pclks; i++)
5528 clk_disable_unprepare(data->pclks[i]);
5529
5530 clk_disable_unprepare(data->clk);
5531
5532 return 0;
5533 }
5534
5535 static int __maybe_unused exynos5433_cmu_resume(struct device *dev)
5536 {
5537 struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
5538 int i;
5539
5540 clk_prepare_enable(data->clk);
5541
5542 for (i = 0; i < data->nr_pclks; i++)
5543 clk_prepare_enable(data->pclks[i]);
5544
5545 samsung_clk_restore(data->ctx.reg_base, data->clk_save,
5546 data->nr_clk_save);
5547
5548 for (i = 0; i < data->nr_pclks; i++)
5549 clk_disable_unprepare(data->pclks[i]);
5550
5551 return 0;
5552 }
5553
5554 static int __init exynos5433_cmu_probe(struct platform_device *pdev)
5555 {
5556 const struct samsung_cmu_info *info;
5557 struct exynos5433_cmu_data *data;
5558 struct samsung_clk_provider *ctx;
5559 struct device *dev = &pdev->dev;
5560 struct resource *res;
5561 void __iomem *reg_base;
5562 int i;
5563
5564 info = of_device_get_match_data(dev);
5565
5566 data = devm_kzalloc(dev,
5567 struct_size(data, ctx.clk_data.hws, info->nr_clk_ids),
5568 GFP_KERNEL);
5569 if (!data)
5570 return -ENOMEM;
5571 ctx = &data->ctx;
5572
5573 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5574 reg_base = devm_ioremap_resource(dev, res);
5575 if (IS_ERR(reg_base))
5576 return PTR_ERR(reg_base);
5577
5578 for (i = 0; i < info->nr_clk_ids; ++i)
5579 ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
5580
5581 ctx->clk_data.num = info->nr_clk_ids;
5582 ctx->reg_base = reg_base;
5583 ctx->dev = dev;
5584 spin_lock_init(&ctx->lock);
5585
5586 data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs,
5587 info->nr_clk_regs);
5588 if (!data->clk_save)
5589 return -ENOMEM;
5590 data->nr_clk_save = info->nr_clk_regs;
5591 data->clk_suspend = info->suspend_regs;
5592 data->nr_clk_suspend = info->nr_suspend_regs;
5593 data->nr_pclks = of_clk_get_parent_count(dev->of_node);
5594
5595 if (data->nr_pclks > 0) {
5596 data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
5597 data->nr_pclks, GFP_KERNEL);
5598 if (!data->pclks) {
5599 kfree(data->clk_save);
5600 return -ENOMEM;
5601 }
5602 for (i = 0; i < data->nr_pclks; i++) {
5603 struct clk *clk = of_clk_get(dev->of_node, i);
5604
5605 if (IS_ERR(clk)) {
5606 kfree(data->clk_save);
5607 while (--i >= 0)
5608 clk_put(data->pclks[i]);
5609 return PTR_ERR(clk);
5610 }
5611 data->pclks[i] = clk;
5612 }
5613 }
5614
5615 if (info->clk_name)
5616 data->clk = clk_get(dev, info->clk_name);
5617 clk_prepare_enable(data->clk);
5618
5619 platform_set_drvdata(pdev, data);
5620
5621 /*
5622 * Enable runtime PM here to allow the clock core using runtime PM
5623 * for the registered clocks. Additionally, we increase the runtime
5624 * PM usage count before registering the clocks, to prevent the
5625 * clock core from runtime suspending the device.
5626 */
5627 pm_runtime_get_noresume(dev);
5628 pm_runtime_set_active(dev);
5629 pm_runtime_enable(dev);
5630
5631 if (info->pll_clks)
5632 samsung_clk_register_pll(ctx, info->pll_clks, info->nr_pll_clks,
5633 reg_base);
5634 if (info->mux_clks)
5635 samsung_clk_register_mux(ctx, info->mux_clks,
5636 info->nr_mux_clks);
5637 if (info->div_clks)
5638 samsung_clk_register_div(ctx, info->div_clks,
5639 info->nr_div_clks);
5640 if (info->gate_clks)
5641 samsung_clk_register_gate(ctx, info->gate_clks,
5642 info->nr_gate_clks);
5643 if (info->fixed_clks)
5644 samsung_clk_register_fixed_rate(ctx, info->fixed_clks,
5645 info->nr_fixed_clks);
5646 if (info->fixed_factor_clks)
5647 samsung_clk_register_fixed_factor(ctx, info->fixed_factor_clks,
5648 info->nr_fixed_factor_clks);
5649
5650 samsung_clk_of_add_provider(dev->of_node, ctx);
5651 pm_runtime_put_sync(dev);
5652
5653 return 0;
5654 }
5655
5656 static const struct of_device_id exynos5433_cmu_of_match[] = {
5657 {
5658 .compatible = "samsung,exynos5433-cmu-aud",
5659 .data = &aud_cmu_info,
5660 }, {
5661 .compatible = "samsung,exynos5433-cmu-cam0",
5662 .data = &cam0_cmu_info,
5663 }, {
5664 .compatible = "samsung,exynos5433-cmu-cam1",
5665 .data = &cam1_cmu_info,
5666 }, {
5667 .compatible = "samsung,exynos5433-cmu-disp",
5668 .data = &disp_cmu_info,
5669 }, {
5670 .compatible = "samsung,exynos5433-cmu-g2d",
5671 .data = &g2d_cmu_info,
5672 }, {
5673 .compatible = "samsung,exynos5433-cmu-g3d",
5674 .data = &g3d_cmu_info,
5675 }, {
5676 .compatible = "samsung,exynos5433-cmu-fsys",
5677 .data = &fsys_cmu_info,
5678 }, {
5679 .compatible = "samsung,exynos5433-cmu-gscl",
5680 .data = &gscl_cmu_info,
5681 }, {
5682 .compatible = "samsung,exynos5433-cmu-mfc",
5683 .data = &mfc_cmu_info,
5684 }, {
5685 .compatible = "samsung,exynos5433-cmu-hevc",
5686 .data = &hevc_cmu_info,
5687 }, {
5688 .compatible = "samsung,exynos5433-cmu-isp",
5689 .data = &isp_cmu_info,
5690 }, {
5691 .compatible = "samsung,exynos5433-cmu-mscl",
5692 .data = &mscl_cmu_info,
5693 }, {
5694 .compatible = "samsung,exynos5433-cmu-imem",
5695 .data = &imem_cmu_info,
5696 }, {
5697 },
5698 };
5699
5700 static const struct dev_pm_ops exynos5433_cmu_pm_ops = {
5701 SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume,
5702 NULL)
5703 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5704 pm_runtime_force_resume)
5705 };
5706
5707 static struct platform_driver exynos5433_cmu_driver __refdata = {
5708 .driver = {
5709 .name = "exynos5433-cmu",
5710 .of_match_table = exynos5433_cmu_of_match,
5711 .suppress_bind_attrs = true,
5712 .pm = &exynos5433_cmu_pm_ops,
5713 },
5714 .probe = exynos5433_cmu_probe,
5715 };
5716
5717 static int __init exynos5433_cmu_init(void)
5718 {
5719 return platform_driver_register(&exynos5433_cmu_driver);
5720 }
5721 core_initcall(exynos5433_cmu_init);
Linux with added FPC-III support