1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/nvmem-consumer.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_opp.h>
15 #include <linux/slab.h>
17 #define OCOTP_CFG3_SPEED_GRADE_SHIFT 8
18 #define OCOTP_CFG3_SPEED_GRADE_MASK (0x3 << 8)
19 #define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8)
20 #define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6
21 #define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6)
23 /* cpufreq-dt device registered by imx-cpufreq-dt */
24 static struct platform_device
*cpufreq_dt_pdev
;
25 static struct opp_table
*cpufreq_opp_table
;
27 static int imx_cpufreq_dt_probe(struct platform_device
*pdev
)
29 struct device
*cpu_dev
= get_cpu_device(0);
30 u32 cell_value
, supported_hw
[2];
31 int speed_grade
, mkt_segment
;
34 ret
= nvmem_cell_read_u32(cpu_dev
, "speed_grade", &cell_value
);
38 if (of_machine_is_compatible("fsl,imx8mn") ||
39 of_machine_is_compatible("fsl,imx8mp"))
40 speed_grade
= (cell_value
& IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK
)
41 >> OCOTP_CFG3_SPEED_GRADE_SHIFT
;
43 speed_grade
= (cell_value
& OCOTP_CFG3_SPEED_GRADE_MASK
)
44 >> OCOTP_CFG3_SPEED_GRADE_SHIFT
;
45 mkt_segment
= (cell_value
& OCOTP_CFG3_MKT_SEGMENT_MASK
) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT
;
48 * Early samples without fuses written report "0 0" which may NOT
49 * match any OPP defined in DT. So clamp to minimum OPP defined in
50 * DT to avoid warning for "no OPPs".
52 * Applies to i.MX8M series SoCs.
54 if (mkt_segment
== 0 && speed_grade
== 0) {
55 if (of_machine_is_compatible("fsl,imx8mm") ||
56 of_machine_is_compatible("fsl,imx8mq"))
58 if (of_machine_is_compatible("fsl,imx8mn") ||
59 of_machine_is_compatible("fsl,imx8mp"))
63 supported_hw
[0] = BIT(speed_grade
);
64 supported_hw
[1] = BIT(mkt_segment
);
65 dev_info(&pdev
->dev
, "cpu speed grade %d mkt segment %d supported-hw %#x %#x\n",
66 speed_grade
, mkt_segment
, supported_hw
[0], supported_hw
[1]);
68 cpufreq_opp_table
= dev_pm_opp_set_supported_hw(cpu_dev
, supported_hw
, 2);
69 if (IS_ERR(cpufreq_opp_table
)) {
70 ret
= PTR_ERR(cpufreq_opp_table
);
71 dev_err(&pdev
->dev
, "Failed to set supported opp: %d\n", ret
);
75 cpufreq_dt_pdev
= platform_device_register_data(
76 &pdev
->dev
, "cpufreq-dt", -1, NULL
, 0);
77 if (IS_ERR(cpufreq_dt_pdev
)) {
78 dev_pm_opp_put_supported_hw(cpufreq_opp_table
);
79 ret
= PTR_ERR(cpufreq_dt_pdev
);
80 dev_err(&pdev
->dev
, "Failed to register cpufreq-dt: %d\n", ret
);
87 static int imx_cpufreq_dt_remove(struct platform_device
*pdev
)
89 platform_device_unregister(cpufreq_dt_pdev
);
90 dev_pm_opp_put_supported_hw(cpufreq_opp_table
);
95 static struct platform_driver imx_cpufreq_dt_driver
= {
96 .probe
= imx_cpufreq_dt_probe
,
97 .remove
= imx_cpufreq_dt_remove
,
99 .name
= "imx-cpufreq-dt",
102 module_platform_driver(imx_cpufreq_dt_driver
);
104 MODULE_ALIAS("platform:imx-cpufreq-dt");
105 MODULE_DESCRIPTION("Freescale i.MX cpufreq speed grading driver");
106 MODULE_LICENSE("GPL v2");