drivers/crypto/caam/caamalg_qi2.h

   1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
   2 /*
   3  * Copyright 2015-2016 Freescale Semiconductor Inc.
   4  * Copyright 2017-2018 NXP
   5  */
   6
   7 #ifndef _CAAMALG_QI2_H_
   8 #define _CAAMALG_QI2_H_
   9
  10 #include <soc/fsl/dpaa2-io.h>
  11 #include <soc/fsl/dpaa2-fd.h>
  12 #include <linux/threads.h>
  13 #include <linux/netdevice.h>
  14 #include "dpseci.h"
  15 #include "desc_constr.h"
  16
  17 #define DPAA2_CAAM_STORE_SIZE   16
  18 /* NAPI weight *must* be a multiple of the store size. */
  19 #define DPAA2_CAAM_NAPI_WEIGHT  512
  20
  21 /* The congestion entrance threshold was chosen so that on LS2088
  22  * we support the maximum throughput for the available memory
  23  */
  24 #define DPAA2_SEC_CONG_ENTRY_THRESH     (128 * 1024 * 1024)
  25 #define DPAA2_SEC_CONG_EXIT_THRESH      (DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10)
  26
  27 /**
  28  * dpaa2_caam_priv - driver private data
  29  * @dpseci_id: DPSECI object unique ID
  30  * @major_ver: DPSECI major version
  31  * @minor_ver: DPSECI minor version
  32  * @dpseci_attr: DPSECI attributes
  33  * @sec_attr: SEC engine attributes
  34  * @rx_queue_attr: array of Rx queue attributes
  35  * @tx_queue_attr: array of Tx queue attributes
  36  * @cscn_mem: pointer to memory region containing the congestion SCN
  37  *      it's size is larger than to accommodate alignment
  38  * @cscn_mem_aligned: pointer to congestion SCN; it is computed as
  39  *      PTR_ALIGN(cscn_mem, DPAA2_CSCN_ALIGN)
  40  * @cscn_dma: dma address used by the QMAN to write CSCN messages
  41  * @dev: device associated with the DPSECI object
  42  * @mc_io: pointer to MC portal's I/O object
  43  * @domain: IOMMU domain
  44  * @ppriv: per CPU pointers to privata data
  45  */
  46 struct dpaa2_caam_priv {
  47         int dpsec_id;
  48
  49         u16 major_ver;
  50         u16 minor_ver;
  51
  52         struct dpseci_attr dpseci_attr;
  53         struct dpseci_sec_attr sec_attr;
  54         struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_MAX_QUEUE_NUM];
  55         struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_MAX_QUEUE_NUM];
  56         int num_pairs;
  57
  58         /* congestion */
  59         void *cscn_mem;
  60         void *cscn_mem_aligned;
  61         dma_addr_t cscn_dma;
  62
  63         struct device *dev;
  64         struct fsl_mc_io *mc_io;
  65         struct iommu_domain *domain;
  66
  67         struct dpaa2_caam_priv_per_cpu __percpu *ppriv;
  68         struct dentry *dfs_root;
  69 };
  70
  71 /**
  72  * dpaa2_caam_priv_per_cpu - per CPU private data
  73  * @napi: napi structure
  74  * @net_dev: netdev used by napi
  75  * @req_fqid: (virtual) request (Tx / enqueue) FQID
  76  * @rsp_fqid: (virtual) response (Rx / dequeue) FQID
  77  * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr
  78  * @nctx: notification context of response FQ
  79  * @store: where dequeued frames are stored
  80  * @priv: backpointer to dpaa2_caam_priv
  81  * @dpio: portal used for data path operations
  82  */
  83 struct dpaa2_caam_priv_per_cpu {
  84         struct napi_struct napi;
  85         struct net_device net_dev;
  86         int req_fqid;
  87         int rsp_fqid;
  88         int prio;
  89         struct dpaa2_io_notification_ctx nctx;
  90         struct dpaa2_io_store *store;
  91         struct dpaa2_caam_priv *priv;
  92         struct dpaa2_io *dpio;
  93 };
  94
  95 /* Length of a single buffer in the QI driver memory cache */
  96 #define CAAM_QI_MEMCACHE_SIZE   512
  97
  98 /*
  99  * aead_edesc - s/w-extended aead descriptor
 100  * @src_nents: number of segments in input scatterlist
 101  * @dst_nents: number of segments in output scatterlist
 102  * @iv_dma: dma address of iv for checking continuity and link table
 103  * @qm_sg_bytes: length of dma mapped h/w link table
 104  * @qm_sg_dma: bus physical mapped address of h/w link table
 105  * @assoclen: associated data length, in CAAM endianness
 106  * @assoclen_dma: bus physical mapped address of req->assoclen
 107  * @sgt: the h/w link table, followed by IV
 108  */
 109 struct aead_edesc {
 110         int src_nents;
 111         int dst_nents;
 112         dma_addr_t iv_dma;
 113         int qm_sg_bytes;
 114         dma_addr_t qm_sg_dma;
 115         unsigned int assoclen;
 116         dma_addr_t assoclen_dma;
 117         struct dpaa2_sg_entry sgt[0];
 118 };
 119
 120 /*
 121  * skcipher_edesc - s/w-extended skcipher descriptor
 122  * @src_nents: number of segments in input scatterlist
 123  * @dst_nents: number of segments in output scatterlist
 124  * @iv_dma: dma address of iv for checking continuity and link table
 125  * @qm_sg_bytes: length of dma mapped qm_sg space
 126  * @qm_sg_dma: I/O virtual address of h/w link table
 127  * @sgt: the h/w link table, followed by IV
 128  */
 129 struct skcipher_edesc {
 130         int src_nents;
 131         int dst_nents;
 132         dma_addr_t iv_dma;
 133         int qm_sg_bytes;
 134         dma_addr_t qm_sg_dma;
 135         struct dpaa2_sg_entry sgt[0];
 136 };
 137
 138 /*
 139  * ahash_edesc - s/w-extended ahash descriptor
 140  * @qm_sg_dma: I/O virtual address of h/w link table
 141  * @src_nents: number of segments in input scatterlist
 142  * @qm_sg_bytes: length of dma mapped qm_sg space
 143  * @sgt: pointer to h/w link table
 144  */
 145 struct ahash_edesc {
 146         dma_addr_t qm_sg_dma;
 147         int src_nents;
 148         int qm_sg_bytes;
 149         struct dpaa2_sg_entry sgt[0];
 150 };
 151
 152 /**
 153  * caam_flc - Flow Context (FLC)
 154  * @flc: Flow Context options
 155  * @sh_desc: Shared Descriptor
 156  */
 157 struct caam_flc {
 158         u32 flc[16];
 159         u32 sh_desc[MAX_SDLEN];
 160 } ____cacheline_aligned;
 161
 162 enum optype {
 163         ENCRYPT = 0,
 164         DECRYPT,
 165         NUM_OP
 166 };
 167
 168 /**
 169  * caam_request - the request structure the driver application should fill while
 170  *                submitting a job to driver.
 171  * @fd_flt: Frame list table defining input and output
 172  *          fd_flt[0] - FLE pointing to output buffer
 173  *          fd_flt[1] - FLE pointing to input buffer
 174  * @fd_flt_dma: DMA address for the frame list table
 175  * @flc: Flow Context
 176  * @flc_dma: I/O virtual address of Flow Context
 177  * @cbk: Callback function to invoke when job is completed
 178  * @ctx: arbit context attached with request by the application
 179  * @edesc: extended descriptor; points to one of {skcipher,aead}_edesc
 180  */
 181 struct caam_request {
 182         struct dpaa2_fl_entry fd_flt[2];
 183         dma_addr_t fd_flt_dma;
 184         struct caam_flc *flc;
 185         dma_addr_t flc_dma;
 186         void (*cbk)(void *ctx, u32 err);
 187         void *ctx;
 188         void *edesc;
 189 };
 190
 191 /**
 192  * dpaa2_caam_enqueue() - enqueue a crypto request
 193  * @dev: device associated with the DPSECI object
 194  * @req: pointer to caam_request
 195  */
 196 int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);
 197
 198 #endif  /* _CAAMALG_QI2_H_ */