drivers/crypto/ccree/cc_driver.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
   3
   4 /* \file cc_driver.h
   5  * ARM CryptoCell Linux Crypto Driver
   6  */
   7
   8 #ifndef __CC_DRIVER_H__
   9 #define __CC_DRIVER_H__
  10
  11 #ifdef COMP_IN_WQ
  12 #include <linux/workqueue.h>
  13 #else
  14 #include <linux/interrupt.h>
  15 #endif
  16 #include <linux/dma-mapping.h>
  17 #include <crypto/algapi.h>
  18 #include <crypto/internal/skcipher.h>
  19 #include <crypto/aes.h>
  20 #include <crypto/sha.h>
  21 #include <crypto/aead.h>
  22 #include <crypto/authenc.h>
  23 #include <crypto/hash.h>
  24 #include <crypto/skcipher.h>
  25 #include <linux/version.h>
  26 #include <linux/clk.h>
  27 #include <linux/platform_device.h>
  28
  29 /* Registers definitions from shared/hw/ree_include */
  30 #include "cc_host_regs.h"
  31 #include "cc_crypto_ctx.h"
  32 #include "cc_hw_queue_defs.h"
  33 #include "cc_sram_mgr.h"
  34
  35 extern bool cc_dump_desc;
  36 extern bool cc_dump_bytes;
  37
  38 #define DRV_MODULE_VERSION "5.0"
  39
  40 enum cc_hw_rev {
  41         CC_HW_REV_630 = 630,
  42         CC_HW_REV_710 = 710,
  43         CC_HW_REV_712 = 712,
  44         CC_HW_REV_713 = 713
  45 };
  46
  47 enum cc_std_body {
  48         CC_STD_NIST = 0x1,
  49         CC_STD_OSCCA = 0x2,
  50         CC_STD_ALL = 0x3
  51 };
  52
  53 #define CC_COHERENT_CACHE_PARAMS 0xEEE
  54
  55 #define CC_PINS_FULL    0x0
  56 #define CC_PINS_SLIM    0x9F
  57
  58 /* Maximum DMA mask supported by IP */
  59 #define DMA_BIT_MASK_LEN 48
  60
  61 #define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \
  62                           (1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \
  63                           (1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \
  64                           (1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT))
  65
  66 #define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
  67
  68 #define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
  69
  70 #define CC_SECURITY_DISABLED_MASK BIT(CC_SECURITY_DISABLED_VALUE_BIT_SHIFT)
  71
  72 #define CC_NVM_IS_IDLE_MASK BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT)
  73
  74 #define AXIM_MON_COMP_VALUE GENMASK(CC_AXIM_MON_COMP_VALUE_BIT_SIZE + \
  75                                     CC_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
  76                                     CC_AXIM_MON_COMP_VALUE_BIT_SHIFT)
  77
  78 #define CC_CPP_AES_ABORT_MASK ( \
  79         BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT) | \
  80         BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT) | \
  81         BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT) | \
  82         BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT) | \
  83         BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT) | \
  84         BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT) | \
  85         BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT) | \
  86         BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT))
  87
  88 #define CC_CPP_SM4_ABORT_MASK ( \
  89         BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT) | \
  90         BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT) | \
  91         BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT) | \
  92         BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT) | \
  93         BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT) | \
  94         BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT) | \
  95         BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT) | \
  96         BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT))
  97
  98 /* Register name mangling macro */
  99 #define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET
 100
 101 /* TEE FIPS status interrupt */
 102 #define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT)
 103
 104 #define CC_CRA_PRIO 400
 105
 106 #define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */
 107
 108 #define MAX_REQUEST_QUEUE_SIZE 4096
 109 #define MAX_MLLI_BUFF_SIZE 2080
 110
 111 /* Definitions for HW descriptors DIN/DOUT fields */
 112 #define NS_BIT 1
 113 #define AXI_ID 0
 114 /* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
 115  * field in the HW descriptor. The DMA engine +8 that value.
 116  */
 117
 118 struct cc_cpp_req {
 119         bool is_cpp;
 120         enum cc_cpp_alg alg;
 121         u8 slot;
 122 };
 123
 124 #define CC_MAX_IVGEN_DMA_ADDRESSES      3
 125 struct cc_crypto_req {
 126         void (*user_cb)(struct device *dev, void *req, int err);
 127         void *user_arg;
 128         struct completion seq_compl; /* request completion */
 129         struct cc_cpp_req cpp;
 130 };
 131
 132 /**
 133  * struct cc_drvdata - driver private data context
 134  * @cc_base:    virt address of the CC registers
 135  * @irq:        bitmap indicating source of last interrupt
 136  */
 137 struct cc_drvdata {
 138         void __iomem *cc_base;
 139         int irq;
 140         struct completion hw_queue_avail; /* wait for HW queue availability */
 141         struct platform_device *plat_dev;
 142         cc_sram_addr_t mlli_sram_addr;
 143         void *buff_mgr_handle;
 144         void *cipher_handle;
 145         void *hash_handle;
 146         void *aead_handle;
 147         void *request_mgr_handle;
 148         void *fips_handle;
 149         void *sram_mgr_handle;
 150         void *debugfs;
 151         struct clk *clk;
 152         bool coherent;
 153         char *hw_rev_name;
 154         enum cc_hw_rev hw_rev;
 155         u32 axim_mon_offset;
 156         u32 sig_offset;
 157         u32 ver_offset;
 158         int std_bodies;
 159         bool sec_disabled;
 160         u32 comp_mask;
 161         bool pm_on;
 162 };
 163
 164 struct cc_crypto_alg {
 165         struct list_head entry;
 166         int cipher_mode;
 167         int flow_mode; /* Note: currently, refers to the cipher mode only. */
 168         int auth_mode;
 169         unsigned int data_unit;
 170         struct cc_drvdata *drvdata;
 171         struct skcipher_alg skcipher_alg;
 172         struct aead_alg aead_alg;
 173 };
 174
 175 struct cc_alg_template {
 176         char name[CRYPTO_MAX_ALG_NAME];
 177         char driver_name[CRYPTO_MAX_ALG_NAME];
 178         unsigned int blocksize;
 179         union {
 180                 struct skcipher_alg skcipher;
 181                 struct aead_alg aead;
 182         } template_u;
 183         int cipher_mode;
 184         int flow_mode; /* Note: currently, refers to the cipher mode only. */
 185         int auth_mode;
 186         u32 min_hw_rev;
 187         enum cc_std_body std_body;
 188         bool sec_func;
 189         unsigned int data_unit;
 190         struct cc_drvdata *drvdata;
 191 };
 192
 193 struct async_gen_req_ctx {
 194         dma_addr_t iv_dma_addr;
 195         u8 *iv;
 196         enum drv_crypto_direction op_type;
 197 };
 198
 199 static inline struct device *drvdata_to_dev(struct cc_drvdata *drvdata)
 200 {
 201         return &drvdata->plat_dev->dev;
 202 }
 203
 204 void __dump_byte_array(const char *name, const u8 *buf, size_t len);
 205 static inline void dump_byte_array(const char *name, const u8 *the_array,
 206                                    size_t size)
 207 {
 208         if (cc_dump_bytes)
 209                 __dump_byte_array(name, the_array, size);
 210 }
 211
 212 bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata);
 213 int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe);
 214 void fini_cc_regs(struct cc_drvdata *drvdata);
 215 int cc_clk_on(struct cc_drvdata *drvdata);
 216 void cc_clk_off(struct cc_drvdata *drvdata);
 217 unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata);
 218
 219 static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val)
 220 {
 221         iowrite32(val, (drvdata->cc_base + reg));
 222 }
 223
 224 static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg)
 225 {
 226         return ioread32(drvdata->cc_base + reg);
 227 }
 228
 229 static inline gfp_t cc_gfp_flags(struct crypto_async_request *req)
 230 {
 231         return (req->flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
 232                         GFP_KERNEL : GFP_ATOMIC;
 233 }
 234
 235 static inline void set_queue_last_ind(struct cc_drvdata *drvdata,
 236                                       struct cc_hw_desc *pdesc)
 237 {
 238         if (drvdata->hw_rev >= CC_HW_REV_712)
 239                 set_queue_last_ind_bit(pdesc);
 240 }
 241
 242 #endif /*__CC_DRIVER_H__*/