drivers/crypto/hisilicon/qm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2019 HiSilicon Limited. */
   3 #ifndef HISI_ACC_QM_H
   4 #define HISI_ACC_QM_H
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/iopoll.h>
   8 #include <linux/module.h>
   9 #include <linux/pci.h>
  10
  11 /* qm user domain */
  12 #define QM_ARUSER_M_CFG_1               0x100088
  13 #define AXUSER_SNOOP_ENABLE             BIT(30)
  14 #define AXUSER_CMD_TYPE                 GENMASK(14, 12)
  15 #define AXUSER_CMD_SMMU_NORMAL          1
  16 #define AXUSER_NS                       BIT(6)
  17 #define AXUSER_NO                       BIT(5)
  18 #define AXUSER_FP                       BIT(4)
  19 #define AXUSER_SSV                      BIT(0)
  20 #define AXUSER_BASE                     (AXUSER_SNOOP_ENABLE |          \
  21                                         FIELD_PREP(AXUSER_CMD_TYPE,     \
  22                                         AXUSER_CMD_SMMU_NORMAL) |       \
  23                                         AXUSER_NS | AXUSER_NO | AXUSER_FP)
  24 #define QM_ARUSER_M_CFG_ENABLE          0x100090
  25 #define ARUSER_M_CFG_ENABLE             0xfffffffe
  26 #define QM_AWUSER_M_CFG_1               0x100098
  27 #define QM_AWUSER_M_CFG_ENABLE          0x1000a0
  28 #define AWUSER_M_CFG_ENABLE             0xfffffffe
  29 #define QM_WUSER_M_CFG_ENABLE           0x1000a8
  30 #define WUSER_M_CFG_ENABLE              0xffffffff
  31
  32 /* qm cache */
  33 #define QM_CACHE_CTL                    0x100050
  34 #define SQC_CACHE_ENABLE                BIT(0)
  35 #define CQC_CACHE_ENABLE                BIT(1)
  36 #define SQC_CACHE_WB_ENABLE             BIT(4)
  37 #define SQC_CACHE_WB_THRD               GENMASK(10, 5)
  38 #define CQC_CACHE_WB_ENABLE             BIT(11)
  39 #define CQC_CACHE_WB_THRD               GENMASK(17, 12)
  40 #define QM_AXI_M_CFG                    0x1000ac
  41 #define AXI_M_CFG                       0xffff
  42 #define QM_AXI_M_CFG_ENABLE             0x1000b0
  43 #define AXI_M_CFG_ENABLE                0xffffffff
  44 #define QM_PEH_AXUSER_CFG               0x1000cc
  45 #define QM_PEH_AXUSER_CFG_ENABLE        0x1000d0
  46 #define PEH_AXUSER_CFG                  0x401001
  47 #define PEH_AXUSER_CFG_ENABLE           0xffffffff
  48
  49 #define QM_DFX_MB_CNT_VF                0x104010
  50 #define QM_DFX_DB_CNT_VF                0x104020
  51 #define QM_DFX_SQE_CNT_VF_SQN           0x104030
  52 #define QM_DFX_CQE_CNT_VF_CQN           0x104040
  53 #define QM_DFX_QN_SHIFT                 16
  54 #define CURRENT_FUN_MASK                GENMASK(5, 0)
  55 #define CURRENT_Q_MASK                  GENMASK(31, 16)
  56
  57 #define QM_AXI_RRESP                    BIT(0)
  58 #define QM_AXI_BRESP                    BIT(1)
  59 #define QM_ECC_MBIT                     BIT(2)
  60 #define QM_ECC_1BIT                     BIT(3)
  61 #define QM_ACC_GET_TASK_TIMEOUT         BIT(4)
  62 #define QM_ACC_DO_TASK_TIMEOUT          BIT(5)
  63 #define QM_ACC_WB_NOT_READY_TIMEOUT     BIT(6)
  64 #define QM_SQ_CQ_VF_INVALID             BIT(7)
  65 #define QM_CQ_VF_INVALID                BIT(8)
  66 #define QM_SQ_VF_INVALID                BIT(9)
  67 #define QM_DB_TIMEOUT                   BIT(10)
  68 #define QM_OF_FIFO_OF                   BIT(11)
  69 #define QM_DB_RANDOM_INVALID            BIT(12)
  70
  71 #define QM_BASE_NFE     (QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
  72                          QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
  73                          QM_OF_FIFO_OF)
  74 #define QM_BASE_CE                      QM_ECC_1BIT
  75
  76 #define QM_Q_DEPTH                      1024
  77
  78 #define HISI_ACC_SGL_SGE_NR_MAX         255
  79
  80 enum qp_state {
  81         QP_STOP,
  82 };
  83
  84 enum qm_hw_ver {
  85         QM_HW_UNKNOWN = -1,
  86         QM_HW_V1 = 0x20,
  87         QM_HW_V2 = 0x21,
  88 };
  89
  90 enum qm_fun_type {
  91         QM_HW_PF,
  92         QM_HW_VF,
  93 };
  94
  95 enum qm_debug_file {
  96         CURRENT_Q,
  97         CLEAR_ENABLE,
  98         DEBUG_FILE_NUM,
  99 };
 100
 101 struct debugfs_file {
 102         enum qm_debug_file index;
 103         struct mutex lock;
 104         struct qm_debug *debug;
 105 };
 106
 107 struct qm_debug {
 108         u32 curr_qm_qp_num;
 109         struct dentry *debug_root;
 110         struct dentry *qm_d;
 111         struct debugfs_file files[DEBUG_FILE_NUM];
 112 };
 113
 114 struct qm_dma {
 115         void *va;
 116         dma_addr_t dma;
 117         size_t size;
 118 };
 119
 120 struct hisi_qm_status {
 121         u32 eq_head;
 122         bool eqc_phase;
 123         u32 aeq_head;
 124         bool aeqc_phase;
 125         unsigned long flags;
 126 };
 127
 128 struct hisi_qm {
 129         enum qm_hw_ver ver;
 130         enum qm_fun_type fun_type;
 131         const char *dev_name;
 132         struct pci_dev *pdev;
 133         void __iomem *io_base;
 134         u32 sqe_size;
 135         u32 qp_base;
 136         u32 qp_num;
 137         u32 qp_in_used;
 138         u32 ctrl_qp_num;
 139
 140         struct qm_dma qdma;
 141         struct qm_sqc *sqc;
 142         struct qm_cqc *cqc;
 143         struct qm_eqe *eqe;
 144         struct qm_aeqe *aeqe;
 145         dma_addr_t sqc_dma;
 146         dma_addr_t cqc_dma;
 147         dma_addr_t eqe_dma;
 148         dma_addr_t aeqe_dma;
 149
 150         struct hisi_qm_status status;
 151
 152         rwlock_t qps_lock;
 153         unsigned long *qp_bitmap;
 154         struct hisi_qp **qp_array;
 155
 156         struct mutex mailbox_lock;
 157
 158         const struct hisi_qm_hw_ops *ops;
 159
 160         struct qm_debug debug;
 161
 162         u32 error_mask;
 163         u32 msi_mask;
 164
 165         bool use_dma_api;
 166 };
 167
 168 struct hisi_qp_status {
 169         atomic_t used;
 170         u16 sq_tail;
 171         u16 cq_head;
 172         bool cqc_phase;
 173         unsigned long flags;
 174 };
 175
 176 struct hisi_qp_ops {
 177         int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
 178 };
 179
 180 struct hisi_qp {
 181         u32 qp_id;
 182         u8 alg_type;
 183         u8 req_type;
 184
 185         struct qm_dma qdma;
 186         void *sqe;
 187         struct qm_cqe *cqe;
 188         dma_addr_t sqe_dma;
 189         dma_addr_t cqe_dma;
 190
 191         struct hisi_qp_status qp_status;
 192         struct hisi_qp_ops *hw_ops;
 193         void *qp_ctx;
 194         void (*req_cb)(struct hisi_qp *qp, void *data);
 195         struct work_struct work;
 196         struct workqueue_struct *wq;
 197
 198         struct hisi_qm *qm;
 199 };
 200
 201 int hisi_qm_init(struct hisi_qm *qm);
 202 void hisi_qm_uninit(struct hisi_qm *qm);
 203 int hisi_qm_start(struct hisi_qm *qm);
 204 int hisi_qm_stop(struct hisi_qm *qm);
 205 struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
 206 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
 207 int hisi_qm_stop_qp(struct hisi_qp *qp);
 208 void hisi_qm_release_qp(struct hisi_qp *qp);
 209 int hisi_qp_send(struct hisi_qp *qp, const void *msg);
 210 int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
 211 int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
 212 int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, u32 number);
 213 int hisi_qm_debug_init(struct hisi_qm *qm);
 214 void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
 215                            u32 msi);
 216 pci_ers_result_t hisi_qm_hw_error_handle(struct hisi_qm *qm);
 217 enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
 218 void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
 219
 220 struct hisi_acc_sgl_pool;
 221 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
 222         struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
 223         u32 index, dma_addr_t *hw_sgl_dma);
 224 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
 225                            struct hisi_acc_hw_sgl *hw_sgl);
 226 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
 227                                                    u32 count, u32 sge_nr);
 228 void hisi_acc_free_sgl_pool(struct device *dev,
 229                             struct hisi_acc_sgl_pool *pool);
 230 #endif