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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / crypto / n2_core.c
blobf5c468f2cc82e95595556b3693fab86e02bd902b
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* n2_core.c: Niagara2 Stream Processing Unit (SPU) crypto support.
3 *
4 * Copyright (C) 2010, 2011 David S. Miller <davem@davemloft.net>
5 */
6
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/cpumask.h>
14 #include <linux/slab.h>
15 #include <linux/interrupt.h>
16 #include <linux/crypto.h>
17 #include <crypto/md5.h>
18 #include <crypto/sha.h>
19 #include <crypto/aes.h>
20 #include <crypto/internal/des.h>
21 #include <linux/mutex.h>
22 #include <linux/delay.h>
23 #include <linux/sched.h>
24
25 #include <crypto/internal/hash.h>
26 #include <crypto/internal/skcipher.h>
27 #include <crypto/scatterwalk.h>
28 #include <crypto/algapi.h>
29
30 #include <asm/hypervisor.h>
31 #include <asm/mdesc.h>
32
33 #include "n2_core.h"
34
35 #define DRV_MODULE_NAME "n2_crypto"
36 #define DRV_MODULE_VERSION "0.2"
37 #define DRV_MODULE_RELDATE "July 28, 2011"
38
39 static const char version[] =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("Niagara2 Crypto driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION);
46
47 #define N2_CRA_PRIORITY 200
48
49 static DEFINE_MUTEX(spu_lock);
50
51 struct spu_queue {
52 cpumask_t sharing;
53 unsigned long qhandle;
54
55 spinlock_t lock;
56 u8 q_type;
57 void *q;
58 unsigned long head;
59 unsigned long tail;
60 struct list_head jobs;
61
62 unsigned long devino;
63
64 char irq_name[32];
65 unsigned int irq;
66
67 struct list_head list;
68 };
69
70 struct spu_qreg {
71 struct spu_queue *queue;
72 unsigned long type;
73 };
74
75 static struct spu_queue **cpu_to_cwq;
76 static struct spu_queue **cpu_to_mau;
77
78 static unsigned long spu_next_offset(struct spu_queue *q, unsigned long off)
79 {
80 if (q->q_type == HV_NCS_QTYPE_MAU) {
81 off += MAU_ENTRY_SIZE;
82 if (off == (MAU_ENTRY_SIZE * MAU_NUM_ENTRIES))
83 off = 0;
84 } else {
85 off += CWQ_ENTRY_SIZE;
86 if (off == (CWQ_ENTRY_SIZE * CWQ_NUM_ENTRIES))
87 off = 0;
88 }
89 return off;
90 }
91
92 struct n2_request_common {
93 struct list_head entry;
94 unsigned int offset;
95 };
96 #define OFFSET_NOT_RUNNING (~(unsigned int)0)
97
98 /* An async job request records the final tail value it used in
99 * n2_request_common->offset, test to see if that offset is in
100 * the range old_head, new_head, inclusive.
101 */
102 static inline bool job_finished(struct spu_queue *q, unsigned int offset,
103 unsigned long old_head, unsigned long new_head)
104 {
105 if (old_head <= new_head) {
106 if (offset > old_head && offset <= new_head)
107 return true;
108 } else {
109 if (offset > old_head || offset <= new_head)
110 return true;
111 }
112 return false;
113 }
114
115 /* When the HEAD marker is unequal to the actual HEAD, we get
116 * a virtual device INO interrupt. We should process the
117 * completed CWQ entries and adjust the HEAD marker to clear
118 * the IRQ.
119 */
120 static irqreturn_t cwq_intr(int irq, void *dev_id)
121 {
122 unsigned long off, new_head, hv_ret;
123 struct spu_queue *q = dev_id;
124
125 pr_err("CPU[%d]: Got CWQ interrupt for qhdl[%lx]\n",
126 smp_processor_id(), q->qhandle);
127
128 spin_lock(&q->lock);
129
130 hv_ret = sun4v_ncs_gethead(q->qhandle, &new_head);
131
132 pr_err("CPU[%d]: CWQ gethead[%lx] hv_ret[%lu]\n",
133 smp_processor_id(), new_head, hv_ret);
134
135 for (off = q->head; off != new_head; off = spu_next_offset(q, off)) {
136 /* XXX ... XXX */
137 }
138
139 hv_ret = sun4v_ncs_sethead_marker(q->qhandle, new_head);
140 if (hv_ret == HV_EOK)
141 q->head = new_head;
142
143 spin_unlock(&q->lock);
144
145 return IRQ_HANDLED;
146 }
147
148 static irqreturn_t mau_intr(int irq, void *dev_id)
149 {
150 struct spu_queue *q = dev_id;
151 unsigned long head, hv_ret;
152
153 spin_lock(&q->lock);
154
155 pr_err("CPU[%d]: Got MAU interrupt for qhdl[%lx]\n",
156 smp_processor_id(), q->qhandle);
157
158 hv_ret = sun4v_ncs_gethead(q->qhandle, &head);
159
160 pr_err("CPU[%d]: MAU gethead[%lx] hv_ret[%lu]\n",
161 smp_processor_id(), head, hv_ret);
162
163 sun4v_ncs_sethead_marker(q->qhandle, head);
164
165 spin_unlock(&q->lock);
166
167 return IRQ_HANDLED;
168 }
169
170 static void *spu_queue_next(struct spu_queue *q, void *cur)
171 {
172 return q->q + spu_next_offset(q, cur - q->q);
173 }
174
175 static int spu_queue_num_free(struct spu_queue *q)
176 {
177 unsigned long head = q->head;
178 unsigned long tail = q->tail;
179 unsigned long end = (CWQ_ENTRY_SIZE * CWQ_NUM_ENTRIES);
180 unsigned long diff;
181
182 if (head > tail)
183 diff = head - tail;
184 else
185 diff = (end - tail) + head;
186
187 return (diff / CWQ_ENTRY_SIZE) - 1;
188 }
189
190 static void *spu_queue_alloc(struct spu_queue *q, int num_entries)
191 {
192 int avail = spu_queue_num_free(q);
193
194 if (avail >= num_entries)
195 return q->q + q->tail;
196
197 return NULL;
198 }
199
200 static unsigned long spu_queue_submit(struct spu_queue *q, void *last)
201 {
202 unsigned long hv_ret, new_tail;
203
204 new_tail = spu_next_offset(q, last - q->q);
205
206 hv_ret = sun4v_ncs_settail(q->qhandle, new_tail);
207 if (hv_ret == HV_EOK)
208 q->tail = new_tail;
209 return hv_ret;
210 }
211
212 static u64 control_word_base(unsigned int len, unsigned int hmac_key_len,
213 int enc_type, int auth_type,
214 unsigned int hash_len,
215 bool sfas, bool sob, bool eob, bool encrypt,
216 int opcode)
217 {
218 u64 word = (len - 1) & CONTROL_LEN;
219
220 word |= ((u64) opcode << CONTROL_OPCODE_SHIFT);
221 word |= ((u64) enc_type << CONTROL_ENC_TYPE_SHIFT);
222 word |= ((u64) auth_type << CONTROL_AUTH_TYPE_SHIFT);
223 if (sfas)
224 word |= CONTROL_STORE_FINAL_AUTH_STATE;
225 if (sob)
226 word |= CONTROL_START_OF_BLOCK;
227 if (eob)
228 word |= CONTROL_END_OF_BLOCK;
229 if (encrypt)
230 word |= CONTROL_ENCRYPT;
231 if (hmac_key_len)
232 word |= ((u64) (hmac_key_len - 1)) << CONTROL_HMAC_KEY_LEN_SHIFT;
233 if (hash_len)
234 word |= ((u64) (hash_len - 1)) << CONTROL_HASH_LEN_SHIFT;
235
236 return word;
237 }
238
239 #if 0
240 static inline bool n2_should_run_async(struct spu_queue *qp, int this_len)
241 {
242 if (this_len >= 64 ||
243 qp->head != qp->tail)
244 return true;
245 return false;
246 }
247 #endif
248
249 struct n2_ahash_alg {
250 struct list_head entry;
251 const u8 *hash_zero;
252 const u32 *hash_init;
253 u8 hw_op_hashsz;
254 u8 digest_size;
255 u8 auth_type;
256 u8 hmac_type;
257 struct ahash_alg alg;
258 };
259
260 static inline struct n2_ahash_alg *n2_ahash_alg(struct crypto_tfm *tfm)
261 {
262 struct crypto_alg *alg = tfm->__crt_alg;
263 struct ahash_alg *ahash_alg;
264
265 ahash_alg = container_of(alg, struct ahash_alg, halg.base);
266
267 return container_of(ahash_alg, struct n2_ahash_alg, alg);
268 }
269
270 struct n2_hmac_alg {
271 const char *child_alg;
272 struct n2_ahash_alg derived;
273 };
274
275 static inline struct n2_hmac_alg *n2_hmac_alg(struct crypto_tfm *tfm)
276 {
277 struct crypto_alg *alg = tfm->__crt_alg;
278 struct ahash_alg *ahash_alg;
279
280 ahash_alg = container_of(alg, struct ahash_alg, halg.base);
281
282 return container_of(ahash_alg, struct n2_hmac_alg, derived.alg);
283 }
284
285 struct n2_hash_ctx {
286 struct crypto_ahash *fallback_tfm;
287 };
288
289 #define N2_HASH_KEY_MAX 32 /* HW limit for all HMAC requests */
290
291 struct n2_hmac_ctx {
292 struct n2_hash_ctx base;
293
294 struct crypto_shash *child_shash;
295
296 int hash_key_len;
297 unsigned char hash_key[N2_HASH_KEY_MAX];
298 };
299
300 struct n2_hash_req_ctx {
301 union {
302 struct md5_state md5;
303 struct sha1_state sha1;
304 struct sha256_state sha256;
305 } u;
306
307 struct ahash_request fallback_req;
308 };
309
310 static int n2_hash_async_init(struct ahash_request *req)
311 {
312 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
313 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
314 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
315
316 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
317 rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
318
319 return crypto_ahash_init(&rctx->fallback_req);
320 }
321
322 static int n2_hash_async_update(struct ahash_request *req)
323 {
324 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
325 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
326 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
327
328 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
329 rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
330 rctx->fallback_req.nbytes = req->nbytes;
331 rctx->fallback_req.src = req->src;
332
333 return crypto_ahash_update(&rctx->fallback_req);
334 }
335
336 static int n2_hash_async_final(struct ahash_request *req)
337 {
338 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
339 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
340 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
341
342 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
343 rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
344 rctx->fallback_req.result = req->result;
345
346 return crypto_ahash_final(&rctx->fallback_req);
347 }
348
349 static int n2_hash_async_finup(struct ahash_request *req)
350 {
351 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
352 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
353 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
354
355 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
356 rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
357 rctx->fallback_req.nbytes = req->nbytes;
358 rctx->fallback_req.src = req->src;
359 rctx->fallback_req.result = req->result;
360
361 return crypto_ahash_finup(&rctx->fallback_req);
362 }
363
364 static int n2_hash_async_noimport(struct ahash_request *req, const void *in)
365 {
366 return -ENOSYS;
367 }
368
369 static int n2_hash_async_noexport(struct ahash_request *req, void *out)
370 {
371 return -ENOSYS;
372 }
373
374 static int n2_hash_cra_init(struct crypto_tfm *tfm)
375 {
376 const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
377 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
378 struct n2_hash_ctx *ctx = crypto_ahash_ctx(ahash);
379 struct crypto_ahash *fallback_tfm;
380 int err;
381
382 fallback_tfm = crypto_alloc_ahash(fallback_driver_name, 0,
383 CRYPTO_ALG_NEED_FALLBACK);
384 if (IS_ERR(fallback_tfm)) {
385 pr_warn("Fallback driver '%s' could not be loaded!\n",
386 fallback_driver_name);
387 err = PTR_ERR(fallback_tfm);
388 goto out;
389 }
390
391 crypto_ahash_set_reqsize(ahash, (sizeof(struct n2_hash_req_ctx) +
392 crypto_ahash_reqsize(fallback_tfm)));
393
394 ctx->fallback_tfm = fallback_tfm;
395 return 0;
396
397 out:
398 return err;
399 }
400
401 static void n2_hash_cra_exit(struct crypto_tfm *tfm)
402 {
403 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
404 struct n2_hash_ctx *ctx = crypto_ahash_ctx(ahash);
405
406 crypto_free_ahash(ctx->fallback_tfm);
407 }
408
409 static int n2_hmac_cra_init(struct crypto_tfm *tfm)
410 {
411 const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
412 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
413 struct n2_hmac_ctx *ctx = crypto_ahash_ctx(ahash);
414 struct n2_hmac_alg *n2alg = n2_hmac_alg(tfm);
415 struct crypto_ahash *fallback_tfm;
416 struct crypto_shash *child_shash;
417 int err;
418
419 fallback_tfm = crypto_alloc_ahash(fallback_driver_name, 0,
420 CRYPTO_ALG_NEED_FALLBACK);
421 if (IS_ERR(fallback_tfm)) {
422 pr_warn("Fallback driver '%s' could not be loaded!\n",
423 fallback_driver_name);
424 err = PTR_ERR(fallback_tfm);
425 goto out;
426 }
427
428 child_shash = crypto_alloc_shash(n2alg->child_alg, 0, 0);
429 if (IS_ERR(child_shash)) {
430 pr_warn("Child shash '%s' could not be loaded!\n",
431 n2alg->child_alg);
432 err = PTR_ERR(child_shash);
433 goto out_free_fallback;
434 }
435
436 crypto_ahash_set_reqsize(ahash, (sizeof(struct n2_hash_req_ctx) +
437 crypto_ahash_reqsize(fallback_tfm)));
438
439 ctx->child_shash = child_shash;
440 ctx->base.fallback_tfm = fallback_tfm;
441 return 0;
442
443 out_free_fallback:
444 crypto_free_ahash(fallback_tfm);
445
446 out:
447 return err;
448 }
449
450 static void n2_hmac_cra_exit(struct crypto_tfm *tfm)
451 {
452 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
453 struct n2_hmac_ctx *ctx = crypto_ahash_ctx(ahash);
454
455 crypto_free_ahash(ctx->base.fallback_tfm);
456 crypto_free_shash(ctx->child_shash);
457 }
458
459 static int n2_hmac_async_setkey(struct crypto_ahash *tfm, const u8 *key,
460 unsigned int keylen)
461 {
462 struct n2_hmac_ctx *ctx = crypto_ahash_ctx(tfm);
463 struct crypto_shash *child_shash = ctx->child_shash;
464 struct crypto_ahash *fallback_tfm;
465 SHASH_DESC_ON_STACK(shash, child_shash);
466 int err, bs, ds;
467
468 fallback_tfm = ctx->base.fallback_tfm;
469 err = crypto_ahash_setkey(fallback_tfm, key, keylen);
470 if (err)
471 return err;
472
473 shash->tfm = child_shash;
474
475 bs = crypto_shash_blocksize(child_shash);
476 ds = crypto_shash_digestsize(child_shash);
477 BUG_ON(ds > N2_HASH_KEY_MAX);
478 if (keylen > bs) {
479 err = crypto_shash_digest(shash, key, keylen,
480 ctx->hash_key);
481 if (err)
482 return err;
483 keylen = ds;
484 } else if (keylen <= N2_HASH_KEY_MAX)
485 memcpy(ctx->hash_key, key, keylen);
486
487 ctx->hash_key_len = keylen;
488
489 return err;
490 }
491
492 static unsigned long wait_for_tail(struct spu_queue *qp)
493 {
494 unsigned long head, hv_ret;
495
496 do {
497 hv_ret = sun4v_ncs_gethead(qp->qhandle, &head);
498 if (hv_ret != HV_EOK) {
499 pr_err("Hypervisor error on gethead\n");
500 break;
501 }
502 if (head == qp->tail) {
503 qp->head = head;
504 break;
505 }
506 } while (1);
507 return hv_ret;
508 }
509
510 static unsigned long submit_and_wait_for_tail(struct spu_queue *qp,
511 struct cwq_initial_entry *ent)
512 {
513 unsigned long hv_ret = spu_queue_submit(qp, ent);
514
515 if (hv_ret == HV_EOK)
516 hv_ret = wait_for_tail(qp);
517
518 return hv_ret;
519 }
520
521 static int n2_do_async_digest(struct ahash_request *req,
522 unsigned int auth_type, unsigned int digest_size,
523 unsigned int result_size, void *hash_loc,
524 unsigned long auth_key, unsigned int auth_key_len)
525 {
526 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
527 struct cwq_initial_entry *ent;
528 struct crypto_hash_walk walk;
529 struct spu_queue *qp;
530 unsigned long flags;
531 int err = -ENODEV;
532 int nbytes, cpu;
533
534 /* The total effective length of the operation may not
535 * exceed 2^16.
536 */
537 if (unlikely(req->nbytes > (1 << 16))) {
538 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
539 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
540
541 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
542 rctx->fallback_req.base.flags =
543 req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
544 rctx->fallback_req.nbytes = req->nbytes;
545 rctx->fallback_req.src = req->src;
546 rctx->fallback_req.result = req->result;
547
548 return crypto_ahash_digest(&rctx->fallback_req);
549 }
550
551 nbytes = crypto_hash_walk_first(req, &walk);
552
553 cpu = get_cpu();
554 qp = cpu_to_cwq[cpu];
555 if (!qp)
556 goto out;
557
558 spin_lock_irqsave(&qp->lock, flags);
559
560 /* XXX can do better, improve this later by doing a by-hand scatterlist
561 * XXX walk, etc.
562 */
563 ent = qp->q + qp->tail;
564
565 ent->control = control_word_base(nbytes, auth_key_len, 0,
566 auth_type, digest_size,
567 false, true, false, false,
568 OPCODE_INPLACE_BIT |
569 OPCODE_AUTH_MAC);
570 ent->src_addr = __pa(walk.data);
571 ent->auth_key_addr = auth_key;
572 ent->auth_iv_addr = __pa(hash_loc);
573 ent->final_auth_state_addr = 0UL;
574 ent->enc_key_addr = 0UL;
575 ent->enc_iv_addr = 0UL;
576 ent->dest_addr = __pa(hash_loc);
577
578 nbytes = crypto_hash_walk_done(&walk, 0);
579 while (nbytes > 0) {
580 ent = spu_queue_next(qp, ent);
581
582 ent->control = (nbytes - 1);
583 ent->src_addr = __pa(walk.data);
584 ent->auth_key_addr = 0UL;
585 ent->auth_iv_addr = 0UL;
586 ent->final_auth_state_addr = 0UL;
587 ent->enc_key_addr = 0UL;
588 ent->enc_iv_addr = 0UL;
589 ent->dest_addr = 0UL;
590
591 nbytes = crypto_hash_walk_done(&walk, 0);
592 }
593 ent->control |= CONTROL_END_OF_BLOCK;
594
595 if (submit_and_wait_for_tail(qp, ent) != HV_EOK)
596 err = -EINVAL;
597 else
598 err = 0;
599
600 spin_unlock_irqrestore(&qp->lock, flags);
601
602 if (!err)
603 memcpy(req->result, hash_loc, result_size);
604 out:
605 put_cpu();
606
607 return err;
608 }
609
610 static int n2_hash_async_digest(struct ahash_request *req)
611 {
612 struct n2_ahash_alg *n2alg = n2_ahash_alg(req->base.tfm);
613 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
614 int ds;
615
616 ds = n2alg->digest_size;
617 if (unlikely(req->nbytes == 0)) {
618 memcpy(req->result, n2alg->hash_zero, ds);
619 return 0;
620 }
621 memcpy(&rctx->u, n2alg->hash_init, n2alg->hw_op_hashsz);
622
623 return n2_do_async_digest(req, n2alg->auth_type,
624 n2alg->hw_op_hashsz, ds,
625 &rctx->u, 0UL, 0);
626 }
627
628 static int n2_hmac_async_digest(struct ahash_request *req)
629 {
630 struct n2_hmac_alg *n2alg = n2_hmac_alg(req->base.tfm);
631 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
632 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
633 struct n2_hmac_ctx *ctx = crypto_ahash_ctx(tfm);
634 int ds;
635
636 ds = n2alg->derived.digest_size;
637 if (unlikely(req->nbytes == 0) ||
638 unlikely(ctx->hash_key_len > N2_HASH_KEY_MAX)) {
639 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
640 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
641
642 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
643 rctx->fallback_req.base.flags =
644 req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
645 rctx->fallback_req.nbytes = req->nbytes;
646 rctx->fallback_req.src = req->src;
647 rctx->fallback_req.result = req->result;
648
649 return crypto_ahash_digest(&rctx->fallback_req);
650 }
651 memcpy(&rctx->u, n2alg->derived.hash_init,
652 n2alg->derived.hw_op_hashsz);
653
654 return n2_do_async_digest(req, n2alg->derived.hmac_type,
655 n2alg->derived.hw_op_hashsz, ds,
656 &rctx->u,
657 __pa(&ctx->hash_key),
658 ctx->hash_key_len);
659 }
660
661 struct n2_skcipher_context {
662 int key_len;
663 int enc_type;
664 union {
665 u8 aes[AES_MAX_KEY_SIZE];
666 u8 des[DES_KEY_SIZE];
667 u8 des3[3 * DES_KEY_SIZE];
668 u8 arc4[258]; /* S-box, X, Y */
669 } key;
670 };
671
672 #define N2_CHUNK_ARR_LEN 16
673
674 struct n2_crypto_chunk {
675 struct list_head entry;
676 unsigned long iv_paddr : 44;
677 unsigned long arr_len : 20;
678 unsigned long dest_paddr;
679 unsigned long dest_final;
680 struct {
681 unsigned long src_paddr : 44;
682 unsigned long src_len : 20;
683 } arr[N2_CHUNK_ARR_LEN];
684 };
685
686 struct n2_request_context {
687 struct skcipher_walk walk;
688 struct list_head chunk_list;
689 struct n2_crypto_chunk chunk;
690 u8 temp_iv[16];
691 };
692
693 /* The SPU allows some level of flexibility for partial cipher blocks
694 * being specified in a descriptor.
695 *
696 * It merely requires that every descriptor's length field is at least
697 * as large as the cipher block size. This means that a cipher block
698 * can span at most 2 descriptors. However, this does not allow a
699 * partial block to span into the final descriptor as that would
700 * violate the rule (since every descriptor's length must be at lest
701 * the block size). So, for example, assuming an 8 byte block size:
702 *
703 * 0xe --> 0xa --> 0x8
704 *
705 * is a valid length sequence, whereas:
706 *
707 * 0xe --> 0xb --> 0x7
708 *
709 * is not a valid sequence.
710 */
711
712 struct n2_skcipher_alg {
713 struct list_head entry;
714 u8 enc_type;
715 struct skcipher_alg skcipher;
716 };
717
718 static inline struct n2_skcipher_alg *n2_skcipher_alg(struct crypto_skcipher *tfm)
719 {
720 struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
721
722 return container_of(alg, struct n2_skcipher_alg, skcipher);
723 }
724
725 struct n2_skcipher_request_context {
726 struct skcipher_walk walk;
727 };
728
729 static int n2_aes_setkey(struct crypto_skcipher *skcipher, const u8 *key,
730 unsigned int keylen)
731 {
732 struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher);
733 struct n2_skcipher_context *ctx = crypto_tfm_ctx(tfm);
734 struct n2_skcipher_alg *n2alg = n2_skcipher_alg(skcipher);
735
736 ctx->enc_type = (n2alg->enc_type & ENC_TYPE_CHAINING_MASK);
737
738 switch (keylen) {
739 case AES_KEYSIZE_128:
740 ctx->enc_type |= ENC_TYPE_ALG_AES128;
741 break;
742 case AES_KEYSIZE_192:
743 ctx->enc_type |= ENC_TYPE_ALG_AES192;
744 break;
745 case AES_KEYSIZE_256:
746 ctx->enc_type |= ENC_TYPE_ALG_AES256;
747 break;
748 default:
749 return -EINVAL;
750 }
751
752 ctx->key_len = keylen;
753 memcpy(ctx->key.aes, key, keylen);
754 return 0;
755 }
756
757 static int n2_des_setkey(struct crypto_skcipher *skcipher, const u8 *key,
758 unsigned int keylen)
759 {
760 struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher);
761 struct n2_skcipher_context *ctx = crypto_tfm_ctx(tfm);
762 struct n2_skcipher_alg *n2alg = n2_skcipher_alg(skcipher);
763 int err;
764
765 err = verify_skcipher_des_key(skcipher, key);
766 if (err)
767 return err;
768
769 ctx->enc_type = n2alg->enc_type;
770
771 ctx->key_len = keylen;
772 memcpy(ctx->key.des, key, keylen);
773 return 0;
774 }
775
776 static int n2_3des_setkey(struct crypto_skcipher *skcipher, const u8 *key,
777 unsigned int keylen)
778 {
779 struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher);
780 struct n2_skcipher_context *ctx = crypto_tfm_ctx(tfm);
781 struct n2_skcipher_alg *n2alg = n2_skcipher_alg(skcipher);
782 int err;
783
784 err = verify_skcipher_des3_key(skcipher, key);
785 if (err)
786 return err;
787
788 ctx->enc_type = n2alg->enc_type;
789
790 ctx->key_len = keylen;
791 memcpy(ctx->key.des3, key, keylen);
792 return 0;
793 }
794
795 static int n2_arc4_setkey(struct crypto_skcipher *skcipher, const u8 *key,
796 unsigned int keylen)
797 {
798 struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher);
799 struct n2_skcipher_context *ctx = crypto_tfm_ctx(tfm);
800 struct n2_skcipher_alg *n2alg = n2_skcipher_alg(skcipher);
801 u8 *s = ctx->key.arc4;
802 u8 *x = s + 256;
803 u8 *y = x + 1;
804 int i, j, k;
805
806 ctx->enc_type = n2alg->enc_type;
807
808 j = k = 0;
809 *x = 0;
810 *y = 0;
811 for (i = 0; i < 256; i++)
812 s[i] = i;
813 for (i = 0; i < 256; i++) {
814 u8 a = s[i];
815 j = (j + key[k] + a) & 0xff;
816 s[i] = s[j];
817 s[j] = a;
818 if (++k >= keylen)
819 k = 0;
820 }
821
822 return 0;
823 }
824
825 static inline int skcipher_descriptor_len(int nbytes, unsigned int block_size)
826 {
827 int this_len = nbytes;
828
829 this_len -= (nbytes & (block_size - 1));
830 return this_len > (1 << 16) ? (1 << 16) : this_len;
831 }
832
833 static int __n2_crypt_chunk(struct crypto_skcipher *skcipher,
834 struct n2_crypto_chunk *cp,
835 struct spu_queue *qp, bool encrypt)
836 {
837 struct n2_skcipher_context *ctx = crypto_skcipher_ctx(skcipher);
838 struct cwq_initial_entry *ent;
839 bool in_place;
840 int i;
841
842 ent = spu_queue_alloc(qp, cp->arr_len);
843 if (!ent) {
844 pr_info("queue_alloc() of %d fails\n",
845 cp->arr_len);
846 return -EBUSY;
847 }
848
849 in_place = (cp->dest_paddr == cp->arr[0].src_paddr);
850
851 ent->control = control_word_base(cp->arr[0].src_len,
852 0, ctx->enc_type, 0, 0,
853 false, true, false, encrypt,
854 OPCODE_ENCRYPT |
855 (in_place ? OPCODE_INPLACE_BIT : 0));
856 ent->src_addr = cp->arr[0].src_paddr;
857 ent->auth_key_addr = 0UL;
858 ent->auth_iv_addr = 0UL;
859 ent->final_auth_state_addr = 0UL;
860 ent->enc_key_addr = __pa(&ctx->key);
861 ent->enc_iv_addr = cp->iv_paddr;
862 ent->dest_addr = (in_place ? 0UL : cp->dest_paddr);
863
864 for (i = 1; i < cp->arr_len; i++) {
865 ent = spu_queue_next(qp, ent);
866
867 ent->control = cp->arr[i].src_len - 1;
868 ent->src_addr = cp->arr[i].src_paddr;
869 ent->auth_key_addr = 0UL;
870 ent->auth_iv_addr = 0UL;
871 ent->final_auth_state_addr = 0UL;
872 ent->enc_key_addr = 0UL;
873 ent->enc_iv_addr = 0UL;
874 ent->dest_addr = 0UL;
875 }
876 ent->control |= CONTROL_END_OF_BLOCK;
877
878 return (spu_queue_submit(qp, ent) != HV_EOK) ? -EINVAL : 0;
879 }
880
881 static int n2_compute_chunks(struct skcipher_request *req)
882 {
883 struct n2_request_context *rctx = skcipher_request_ctx(req);
884 struct skcipher_walk *walk = &rctx->walk;
885 struct n2_crypto_chunk *chunk;
886 unsigned long dest_prev;
887 unsigned int tot_len;
888 bool prev_in_place;
889 int err, nbytes;
890
891 err = skcipher_walk_async(walk, req);
892 if (err)
893 return err;
894
895 INIT_LIST_HEAD(&rctx->chunk_list);
896
897 chunk = &rctx->chunk;
898 INIT_LIST_HEAD(&chunk->entry);
899
900 chunk->iv_paddr = 0UL;
901 chunk->arr_len = 0;
902 chunk->dest_paddr = 0UL;
903
904 prev_in_place = false;
905 dest_prev = ~0UL;
906 tot_len = 0;
907
908 while ((nbytes = walk->nbytes) != 0) {
909 unsigned long dest_paddr, src_paddr;
910 bool in_place;
911 int this_len;
912
913 src_paddr = (page_to_phys(walk->src.phys.page) +
914 walk->src.phys.offset);
915 dest_paddr = (page_to_phys(walk->dst.phys.page) +
916 walk->dst.phys.offset);
917 in_place = (src_paddr == dest_paddr);
918 this_len = skcipher_descriptor_len(nbytes, walk->blocksize);
919
920 if (chunk->arr_len != 0) {
921 if (in_place != prev_in_place ||
922 (!prev_in_place &&
923 dest_paddr != dest_prev) ||
924 chunk->arr_len == N2_CHUNK_ARR_LEN ||
925 tot_len + this_len > (1 << 16)) {
926 chunk->dest_final = dest_prev;
927 list_add_tail(&chunk->entry,
928 &rctx->chunk_list);
929 chunk = kzalloc(sizeof(*chunk), GFP_ATOMIC);
930 if (!chunk) {
931 err = -ENOMEM;
932 break;
933 }
934 INIT_LIST_HEAD(&chunk->entry);
935 }
936 }
937 if (chunk->arr_len == 0) {
938 chunk->dest_paddr = dest_paddr;
939 tot_len = 0;
940 }
941 chunk->arr[chunk->arr_len].src_paddr = src_paddr;
942 chunk->arr[chunk->arr_len].src_len = this_len;
943 chunk->arr_len++;
944
945 dest_prev = dest_paddr + this_len;
946 prev_in_place = in_place;
947 tot_len += this_len;
948
949 err = skcipher_walk_done(walk, nbytes - this_len);
950 if (err)
951 break;
952 }
953 if (!err && chunk->arr_len != 0) {
954 chunk->dest_final = dest_prev;
955 list_add_tail(&chunk->entry, &rctx->chunk_list);
956 }
957
958 return err;
959 }
960
961 static void n2_chunk_complete(struct skcipher_request *req, void *final_iv)
962 {
963 struct n2_request_context *rctx = skcipher_request_ctx(req);
964 struct n2_crypto_chunk *c, *tmp;
965
966 if (final_iv)
967 memcpy(rctx->walk.iv, final_iv, rctx->walk.blocksize);
968
969 list_for_each_entry_safe(c, tmp, &rctx->chunk_list, entry) {
970 list_del(&c->entry);
971 if (unlikely(c != &rctx->chunk))
972 kfree(c);
973 }
974
975 }
976
977 static int n2_do_ecb(struct skcipher_request *req, bool encrypt)
978 {
979 struct n2_request_context *rctx = skcipher_request_ctx(req);
980 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
981 int err = n2_compute_chunks(req);
982 struct n2_crypto_chunk *c, *tmp;
983 unsigned long flags, hv_ret;
984 struct spu_queue *qp;
985
986 if (err)
987 return err;
988
989 qp = cpu_to_cwq[get_cpu()];
990 err = -ENODEV;
991 if (!qp)
992 goto out;
993
994 spin_lock_irqsave(&qp->lock, flags);
995
996 list_for_each_entry_safe(c, tmp, &rctx->chunk_list, entry) {
997 err = __n2_crypt_chunk(tfm, c, qp, encrypt);
998 if (err)
999 break;
1000 list_del(&c->entry);
1001 if (unlikely(c != &rctx->chunk))
1002 kfree(c);
1003 }
1004 if (!err) {
1005 hv_ret = wait_for_tail(qp);
1006 if (hv_ret != HV_EOK)
1007 err = -EINVAL;
1008 }
1009
1010 spin_unlock_irqrestore(&qp->lock, flags);
1011
1012 out:
1013 put_cpu();
1014
1015 n2_chunk_complete(req, NULL);
1016 return err;
1017 }
1018
1019 static int n2_encrypt_ecb(struct skcipher_request *req)
1020 {
1021 return n2_do_ecb(req, true);
1022 }
1023
1024 static int n2_decrypt_ecb(struct skcipher_request *req)
1025 {
1026 return n2_do_ecb(req, false);
1027 }
1028
1029 static int n2_do_chaining(struct skcipher_request *req, bool encrypt)
1030 {
1031 struct n2_request_context *rctx = skcipher_request_ctx(req);
1032 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
1033 unsigned long flags, hv_ret, iv_paddr;
1034 int err = n2_compute_chunks(req);
1035 struct n2_crypto_chunk *c, *tmp;
1036 struct spu_queue *qp;
1037 void *final_iv_addr;
1038
1039 final_iv_addr = NULL;
1040
1041 if (err)
1042 return err;
1043
1044 qp = cpu_to_cwq[get_cpu()];
1045 err = -ENODEV;
1046 if (!qp)
1047 goto out;
1048
1049 spin_lock_irqsave(&qp->lock, flags);
1050
1051 if (encrypt) {
1052 iv_paddr = __pa(rctx->walk.iv);
1053 list_for_each_entry_safe(c, tmp, &rctx->chunk_list,
1054 entry) {
1055 c->iv_paddr = iv_paddr;
1056 err = __n2_crypt_chunk(tfm, c, qp, true);
1057 if (err)
1058 break;
1059 iv_paddr = c->dest_final - rctx->walk.blocksize;
1060 list_del(&c->entry);
1061 if (unlikely(c != &rctx->chunk))
1062 kfree(c);
1063 }
1064 final_iv_addr = __va(iv_paddr);
1065 } else {
1066 list_for_each_entry_safe_reverse(c, tmp, &rctx->chunk_list,
1067 entry) {
1068 if (c == &rctx->chunk) {
1069 iv_paddr = __pa(rctx->walk.iv);
1070 } else {
1071 iv_paddr = (tmp->arr[tmp->arr_len-1].src_paddr +
1072 tmp->arr[tmp->arr_len-1].src_len -
1073 rctx->walk.blocksize);
1074 }
1075 if (!final_iv_addr) {
1076 unsigned long pa;
1077
1078 pa = (c->arr[c->arr_len-1].src_paddr +
1079 c->arr[c->arr_len-1].src_len -
1080 rctx->walk.blocksize);
1081 final_iv_addr = rctx->temp_iv;
1082 memcpy(rctx->temp_iv, __va(pa),
1083 rctx->walk.blocksize);
1084 }
1085 c->iv_paddr = iv_paddr;
1086 err = __n2_crypt_chunk(tfm, c, qp, false);
1087 if (err)
1088 break;
1089 list_del(&c->entry);
1090 if (unlikely(c != &rctx->chunk))
1091 kfree(c);
1092 }
1093 }
1094 if (!err) {
1095 hv_ret = wait_for_tail(qp);
1096 if (hv_ret != HV_EOK)
1097 err = -EINVAL;
1098 }
1099
1100 spin_unlock_irqrestore(&qp->lock, flags);
1101
1102 out:
1103 put_cpu();
1104
1105 n2_chunk_complete(req, err ? NULL : final_iv_addr);
1106 return err;
1107 }
1108
1109 static int n2_encrypt_chaining(struct skcipher_request *req)
1110 {
1111 return n2_do_chaining(req, true);
1112 }
1113
1114 static int n2_decrypt_chaining(struct skcipher_request *req)
1115 {
1116 return n2_do_chaining(req, false);
1117 }
1118
1119 struct n2_skcipher_tmpl {
1120 const char *name;
1121 const char *drv_name;
1122 u8 block_size;
1123 u8 enc_type;
1124 struct skcipher_alg skcipher;
1125 };
1126
1127 static const struct n2_skcipher_tmpl skcipher_tmpls[] = {
1128 /* ARC4: only ECB is supported (chaining bits ignored) */
1129 { .name = "ecb(arc4)",
1130 .drv_name = "ecb-arc4",
1131 .block_size = 1,
1132 .enc_type = (ENC_TYPE_ALG_RC4_STREAM |
1133 ENC_TYPE_CHAINING_ECB),
1134 .skcipher = {
1135 .min_keysize = 1,
1136 .max_keysize = 256,
1137 .setkey = n2_arc4_setkey,
1138 .encrypt = n2_encrypt_ecb,
1139 .decrypt = n2_decrypt_ecb,
1140 },
1141 },
1142
1143 /* DES: ECB CBC and CFB are supported */
1144 { .name = "ecb(des)",
1145 .drv_name = "ecb-des",
1146 .block_size = DES_BLOCK_SIZE,
1147 .enc_type = (ENC_TYPE_ALG_DES |
1148 ENC_TYPE_CHAINING_ECB),
1149 .skcipher = {
1150 .min_keysize = DES_KEY_SIZE,
1151 .max_keysize = DES_KEY_SIZE,
1152 .setkey = n2_des_setkey,
1153 .encrypt = n2_encrypt_ecb,
1154 .decrypt = n2_decrypt_ecb,
1155 },
1156 },
1157 { .name = "cbc(des)",
1158 .drv_name = "cbc-des",
1159 .block_size = DES_BLOCK_SIZE,
1160 .enc_type = (ENC_TYPE_ALG_DES |
1161 ENC_TYPE_CHAINING_CBC),
1162 .skcipher = {
1163 .ivsize = DES_BLOCK_SIZE,
1164 .min_keysize = DES_KEY_SIZE,
1165 .max_keysize = DES_KEY_SIZE,
1166 .setkey = n2_des_setkey,
1167 .encrypt = n2_encrypt_chaining,
1168 .decrypt = n2_decrypt_chaining,
1169 },
1170 },
1171 { .name = "cfb(des)",
1172 .drv_name = "cfb-des",
1173 .block_size = DES_BLOCK_SIZE,
1174 .enc_type = (ENC_TYPE_ALG_DES |
1175 ENC_TYPE_CHAINING_CFB),
1176 .skcipher = {
1177 .min_keysize = DES_KEY_SIZE,
1178 .max_keysize = DES_KEY_SIZE,
1179 .setkey = n2_des_setkey,
1180 .encrypt = n2_encrypt_chaining,
1181 .decrypt = n2_decrypt_chaining,
1182 },
1183 },
1184
1185 /* 3DES: ECB CBC and CFB are supported */
1186 { .name = "ecb(des3_ede)",
1187 .drv_name = "ecb-3des",
1188 .block_size = DES_BLOCK_SIZE,
1189 .enc_type = (ENC_TYPE_ALG_3DES |
1190 ENC_TYPE_CHAINING_ECB),
1191 .skcipher = {
1192 .min_keysize = 3 * DES_KEY_SIZE,
1193 .max_keysize = 3 * DES_KEY_SIZE,
1194 .setkey = n2_3des_setkey,
1195 .encrypt = n2_encrypt_ecb,
1196 .decrypt = n2_decrypt_ecb,
1197 },
1198 },
1199 { .name = "cbc(des3_ede)",
1200 .drv_name = "cbc-3des",
1201 .block_size = DES_BLOCK_SIZE,
1202 .enc_type = (ENC_TYPE_ALG_3DES |
1203 ENC_TYPE_CHAINING_CBC),
1204 .skcipher = {
1205 .ivsize = DES_BLOCK_SIZE,
1206 .min_keysize = 3 * DES_KEY_SIZE,
1207 .max_keysize = 3 * DES_KEY_SIZE,
1208 .setkey = n2_3des_setkey,
1209 .encrypt = n2_encrypt_chaining,
1210 .decrypt = n2_decrypt_chaining,
1211 },
1212 },
1213 { .name = "cfb(des3_ede)",
1214 .drv_name = "cfb-3des",
1215 .block_size = DES_BLOCK_SIZE,
1216 .enc_type = (ENC_TYPE_ALG_3DES |
1217 ENC_TYPE_CHAINING_CFB),
1218 .skcipher = {
1219 .min_keysize = 3 * DES_KEY_SIZE,
1220 .max_keysize = 3 * DES_KEY_SIZE,
1221 .setkey = n2_3des_setkey,
1222 .encrypt = n2_encrypt_chaining,
1223 .decrypt = n2_decrypt_chaining,
1224 },
1225 },
1226 /* AES: ECB CBC and CTR are supported */
1227 { .name = "ecb(aes)",
1228 .drv_name = "ecb-aes",
1229 .block_size = AES_BLOCK_SIZE,
1230 .enc_type = (ENC_TYPE_ALG_AES128 |
1231 ENC_TYPE_CHAINING_ECB),
1232 .skcipher = {
1233 .min_keysize = AES_MIN_KEY_SIZE,
1234 .max_keysize = AES_MAX_KEY_SIZE,
1235 .setkey = n2_aes_setkey,
1236 .encrypt = n2_encrypt_ecb,
1237 .decrypt = n2_decrypt_ecb,
1238 },
1239 },
1240 { .name = "cbc(aes)",
1241 .drv_name = "cbc-aes",
1242 .block_size = AES_BLOCK_SIZE,
1243 .enc_type = (ENC_TYPE_ALG_AES128 |
1244 ENC_TYPE_CHAINING_CBC),
1245 .skcipher = {
1246 .ivsize = AES_BLOCK_SIZE,
1247 .min_keysize = AES_MIN_KEY_SIZE,
1248 .max_keysize = AES_MAX_KEY_SIZE,
1249 .setkey = n2_aes_setkey,
1250 .encrypt = n2_encrypt_chaining,
1251 .decrypt = n2_decrypt_chaining,
1252 },
1253 },
1254 { .name = "ctr(aes)",
1255 .drv_name = "ctr-aes",
1256 .block_size = AES_BLOCK_SIZE,
1257 .enc_type = (ENC_TYPE_ALG_AES128 |
1258 ENC_TYPE_CHAINING_COUNTER),
1259 .skcipher = {
1260 .ivsize = AES_BLOCK_SIZE,
1261 .min_keysize = AES_MIN_KEY_SIZE,
1262 .max_keysize = AES_MAX_KEY_SIZE,
1263 .setkey = n2_aes_setkey,
1264 .encrypt = n2_encrypt_chaining,
1265 .decrypt = n2_encrypt_chaining,
1266 },
1267 },
1268
1269 };
1270 #define NUM_CIPHER_TMPLS ARRAY_SIZE(skcipher_tmpls)
1271
1272 static LIST_HEAD(skcipher_algs);
1273
1274 struct n2_hash_tmpl {
1275 const char *name;
1276 const u8 *hash_zero;
1277 const u32 *hash_init;
1278 u8 hw_op_hashsz;
1279 u8 digest_size;
1280 u8 block_size;
1281 u8 auth_type;
1282 u8 hmac_type;
1283 };
1284
1285 static const u32 n2_md5_init[MD5_HASH_WORDS] = {
1286 cpu_to_le32(MD5_H0),
1287 cpu_to_le32(MD5_H1),
1288 cpu_to_le32(MD5_H2),
1289 cpu_to_le32(MD5_H3),
1290 };
1291 static const u32 n2_sha1_init[SHA1_DIGEST_SIZE / 4] = {
1292 SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4,
1293 };
1294 static const u32 n2_sha256_init[SHA256_DIGEST_SIZE / 4] = {
1295 SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3,
1296 SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7,
1297 };
1298 static const u32 n2_sha224_init[SHA256_DIGEST_SIZE / 4] = {
1299 SHA224_H0, SHA224_H1, SHA224_H2, SHA224_H3,
1300 SHA224_H4, SHA224_H5, SHA224_H6, SHA224_H7,
1301 };
1302
1303 static const struct n2_hash_tmpl hash_tmpls[] = {
1304 { .name = "md5",
1305 .hash_zero = md5_zero_message_hash,
1306 .hash_init = n2_md5_init,
1307 .auth_type = AUTH_TYPE_MD5,
1308 .hmac_type = AUTH_TYPE_HMAC_MD5,
1309 .hw_op_hashsz = MD5_DIGEST_SIZE,
1310 .digest_size = MD5_DIGEST_SIZE,
1311 .block_size = MD5_HMAC_BLOCK_SIZE },
1312 { .name = "sha1",
1313 .hash_zero = sha1_zero_message_hash,
1314 .hash_init = n2_sha1_init,
1315 .auth_type = AUTH_TYPE_SHA1,
1316 .hmac_type = AUTH_TYPE_HMAC_SHA1,
1317 .hw_op_hashsz = SHA1_DIGEST_SIZE,
1318 .digest_size = SHA1_DIGEST_SIZE,
1319 .block_size = SHA1_BLOCK_SIZE },
1320 { .name = "sha256",
1321 .hash_zero = sha256_zero_message_hash,
1322 .hash_init = n2_sha256_init,
1323 .auth_type = AUTH_TYPE_SHA256,
1324 .hmac_type = AUTH_TYPE_HMAC_SHA256,
1325 .hw_op_hashsz = SHA256_DIGEST_SIZE,
1326 .digest_size = SHA256_DIGEST_SIZE,
1327 .block_size = SHA256_BLOCK_SIZE },
1328 { .name = "sha224",
1329 .hash_zero = sha224_zero_message_hash,
1330 .hash_init = n2_sha224_init,
1331 .auth_type = AUTH_TYPE_SHA256,
1332 .hmac_type = AUTH_TYPE_RESERVED,
1333 .hw_op_hashsz = SHA256_DIGEST_SIZE,
1334 .digest_size = SHA224_DIGEST_SIZE,
1335 .block_size = SHA224_BLOCK_SIZE },
1336 };
1337 #define NUM_HASH_TMPLS ARRAY_SIZE(hash_tmpls)
1338
1339 static LIST_HEAD(ahash_algs);
1340 static LIST_HEAD(hmac_algs);
1341
1342 static int algs_registered;
1343
1344 static void __n2_unregister_algs(void)
1345 {
1346 struct n2_skcipher_alg *skcipher, *skcipher_tmp;
1347 struct n2_ahash_alg *alg, *alg_tmp;
1348 struct n2_hmac_alg *hmac, *hmac_tmp;
1349
1350 list_for_each_entry_safe(skcipher, skcipher_tmp, &skcipher_algs, entry) {
1351 crypto_unregister_skcipher(&skcipher->skcipher);
1352 list_del(&skcipher->entry);
1353 kfree(skcipher);
1354 }
1355 list_for_each_entry_safe(hmac, hmac_tmp, &hmac_algs, derived.entry) {
1356 crypto_unregister_ahash(&hmac->derived.alg);
1357 list_del(&hmac->derived.entry);
1358 kfree(hmac);
1359 }
1360 list_for_each_entry_safe(alg, alg_tmp, &ahash_algs, entry) {
1361 crypto_unregister_ahash(&alg->alg);
1362 list_del(&alg->entry);
1363 kfree(alg);
1364 }
1365 }
1366
1367 static int n2_skcipher_init_tfm(struct crypto_skcipher *tfm)
1368 {
1369 crypto_skcipher_set_reqsize(tfm, sizeof(struct n2_request_context));
1370 return 0;
1371 }
1372
1373 static int __n2_register_one_skcipher(const struct n2_skcipher_tmpl *tmpl)
1374 {
1375 struct n2_skcipher_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1376 struct skcipher_alg *alg;
1377 int err;
1378
1379 if (!p)
1380 return -ENOMEM;
1381
1382 alg = &p->skcipher;
1383 *alg = tmpl->skcipher;
1384
1385 snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
1386 snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->drv_name);
1387 alg->base.cra_priority = N2_CRA_PRIORITY;
1388 alg->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC;
1389 alg->base.cra_blocksize = tmpl->block_size;
1390 p->enc_type = tmpl->enc_type;
1391 alg->base.cra_ctxsize = sizeof(struct n2_skcipher_context);
1392 alg->base.cra_module = THIS_MODULE;
1393 alg->init = n2_skcipher_init_tfm;
1394
1395 list_add(&p->entry, &skcipher_algs);
1396 err = crypto_register_skcipher(alg);
1397 if (err) {
1398 pr_err("%s alg registration failed\n", alg->base.cra_name);
1399 list_del(&p->entry);
1400 kfree(p);
1401 } else {
1402 pr_info("%s alg registered\n", alg->base.cra_name);
1403 }
1404 return err;
1405 }
1406
1407 static int __n2_register_one_hmac(struct n2_ahash_alg *n2ahash)
1408 {
1409 struct n2_hmac_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1410 struct ahash_alg *ahash;
1411 struct crypto_alg *base;
1412 int err;
1413
1414 if (!p)
1415 return -ENOMEM;
1416
1417 p->child_alg = n2ahash->alg.halg.base.cra_name;
1418 memcpy(&p->derived, n2ahash, sizeof(struct n2_ahash_alg));
1419 INIT_LIST_HEAD(&p->derived.entry);
1420
1421 ahash = &p->derived.alg;
1422 ahash->digest = n2_hmac_async_digest;
1423 ahash->setkey = n2_hmac_async_setkey;
1424
1425 base = &ahash->halg.base;
1426 snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "hmac(%s)", p->child_alg);
1427 snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "hmac-%s-n2", p->child_alg);
1428
1429 base->cra_ctxsize = sizeof(struct n2_hmac_ctx);
1430 base->cra_init = n2_hmac_cra_init;
1431 base->cra_exit = n2_hmac_cra_exit;
1432
1433 list_add(&p->derived.entry, &hmac_algs);
1434 err = crypto_register_ahash(ahash);
1435 if (err) {
1436 pr_err("%s alg registration failed\n", base->cra_name);
1437 list_del(&p->derived.entry);
1438 kfree(p);
1439 } else {
1440 pr_info("%s alg registered\n", base->cra_name);
1441 }
1442 return err;
1443 }
1444
1445 static int __n2_register_one_ahash(const struct n2_hash_tmpl *tmpl)
1446 {
1447 struct n2_ahash_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1448 struct hash_alg_common *halg;
1449 struct crypto_alg *base;
1450 struct ahash_alg *ahash;
1451 int err;
1452
1453 if (!p)
1454 return -ENOMEM;
1455
1456 p->hash_zero = tmpl->hash_zero;
1457 p->hash_init = tmpl->hash_init;
1458 p->auth_type = tmpl->auth_type;
1459 p->hmac_type = tmpl->hmac_type;
1460 p->hw_op_hashsz = tmpl->hw_op_hashsz;
1461 p->digest_size = tmpl->digest_size;
1462
1463 ahash = &p->alg;
1464 ahash->init = n2_hash_async_init;
1465 ahash->update = n2_hash_async_update;
1466 ahash->final = n2_hash_async_final;
1467 ahash->finup = n2_hash_async_finup;
1468 ahash->digest = n2_hash_async_digest;
1469 ahash->export = n2_hash_async_noexport;
1470 ahash->import = n2_hash_async_noimport;
1471
1472 halg = &ahash->halg;
1473 halg->digestsize = tmpl->digest_size;
1474
1475 base = &halg->base;
1476 snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
1477 snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->name);
1478 base->cra_priority = N2_CRA_PRIORITY;
1479 base->cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1480 CRYPTO_ALG_NEED_FALLBACK;
1481 base->cra_blocksize = tmpl->block_size;
1482 base->cra_ctxsize = sizeof(struct n2_hash_ctx);
1483 base->cra_module = THIS_MODULE;
1484 base->cra_init = n2_hash_cra_init;
1485 base->cra_exit = n2_hash_cra_exit;
1486
1487 list_add(&p->entry, &ahash_algs);
1488 err = crypto_register_ahash(ahash);
1489 if (err) {
1490 pr_err("%s alg registration failed\n", base->cra_name);
1491 list_del(&p->entry);
1492 kfree(p);
1493 } else {
1494 pr_info("%s alg registered\n", base->cra_name);
1495 }
1496 if (!err && p->hmac_type != AUTH_TYPE_RESERVED)
1497 err = __n2_register_one_hmac(p);
1498 return err;
1499 }
1500
1501 static int n2_register_algs(void)
1502 {
1503 int i, err = 0;
1504
1505 mutex_lock(&spu_lock);
1506 if (algs_registered++)
1507 goto out;
1508
1509 for (i = 0; i < NUM_HASH_TMPLS; i++) {
1510 err = __n2_register_one_ahash(&hash_tmpls[i]);
1511 if (err) {
1512 __n2_unregister_algs();
1513 goto out;
1514 }
1515 }
1516 for (i = 0; i < NUM_CIPHER_TMPLS; i++) {
1517 err = __n2_register_one_skcipher(&skcipher_tmpls[i]);
1518 if (err) {
1519 __n2_unregister_algs();
1520 goto out;
1521 }
1522 }
1523
1524 out:
1525 mutex_unlock(&spu_lock);
1526 return err;
1527 }
1528
1529 static void n2_unregister_algs(void)
1530 {
1531 mutex_lock(&spu_lock);
1532 if (!--algs_registered)
1533 __n2_unregister_algs();
1534 mutex_unlock(&spu_lock);
1535 }
1536
1537 /* To map CWQ queues to interrupt sources, the hypervisor API provides
1538 * a devino. This isn't very useful to us because all of the
1539 * interrupts listed in the device_node have been translated to
1540 * Linux virtual IRQ cookie numbers.
1541 *
1542 * So we have to back-translate, going through the 'intr' and 'ino'
1543 * property tables of the n2cp MDESC node, matching it with the OF
1544 * 'interrupts' property entries, in order to to figure out which
1545 * devino goes to which already-translated IRQ.
1546 */
1547 static int find_devino_index(struct platform_device *dev, struct spu_mdesc_info *ip,
1548 unsigned long dev_ino)
1549 {
1550 const unsigned int *dev_intrs;
1551 unsigned int intr;
1552 int i;
1553
1554 for (i = 0; i < ip->num_intrs; i++) {
1555 if (ip->ino_table[i].ino == dev_ino)
1556 break;
1557 }
1558 if (i == ip->num_intrs)
1559 return -ENODEV;
1560
1561 intr = ip->ino_table[i].intr;
1562
1563 dev_intrs = of_get_property(dev->dev.of_node, "interrupts", NULL);
1564 if (!dev_intrs)
1565 return -ENODEV;
1566
1567 for (i = 0; i < dev->archdata.num_irqs; i++) {
1568 if (dev_intrs[i] == intr)
1569 return i;
1570 }
1571
1572 return -ENODEV;
1573 }
1574
1575 static int spu_map_ino(struct platform_device *dev, struct spu_mdesc_info *ip,
1576 const char *irq_name, struct spu_queue *p,
1577 irq_handler_t handler)
1578 {
1579 unsigned long herr;
1580 int index;
1581
1582 herr = sun4v_ncs_qhandle_to_devino(p->qhandle, &p->devino);
1583 if (herr)
1584 return -EINVAL;
1585
1586 index = find_devino_index(dev, ip, p->devino);
1587 if (index < 0)
1588 return index;
1589
1590 p->irq = dev->archdata.irqs[index];
1591
1592 sprintf(p->irq_name, "%s-%d", irq_name, index);
1593
1594 return request_irq(p->irq, handler, 0, p->irq_name, p);
1595 }
1596
1597 static struct kmem_cache *queue_cache[2];
1598
1599 static void *new_queue(unsigned long q_type)
1600 {
1601 return kmem_cache_zalloc(queue_cache[q_type - 1], GFP_KERNEL);
1602 }
1603
1604 static void free_queue(void *p, unsigned long q_type)
1605 {
1606 kmem_cache_free(queue_cache[q_type - 1], p);
1607 }
1608
1609 static int queue_cache_init(void)
1610 {
1611 if (!queue_cache[HV_NCS_QTYPE_MAU - 1])
1612 queue_cache[HV_NCS_QTYPE_MAU - 1] =
1613 kmem_cache_create("mau_queue",
1614 (MAU_NUM_ENTRIES *
1615 MAU_ENTRY_SIZE),
1616 MAU_ENTRY_SIZE, 0, NULL);
1617 if (!queue_cache[HV_NCS_QTYPE_MAU - 1])
1618 return -ENOMEM;
1619
1620 if (!queue_cache[HV_NCS_QTYPE_CWQ - 1])
1621 queue_cache[HV_NCS_QTYPE_CWQ - 1] =
1622 kmem_cache_create("cwq_queue",
1623 (CWQ_NUM_ENTRIES *
1624 CWQ_ENTRY_SIZE),
1625 CWQ_ENTRY_SIZE, 0, NULL);
1626 if (!queue_cache[HV_NCS_QTYPE_CWQ - 1]) {
1627 kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_MAU - 1]);
1628 queue_cache[HV_NCS_QTYPE_MAU - 1] = NULL;
1629 return -ENOMEM;
1630 }
1631 return 0;
1632 }
1633
1634 static void queue_cache_destroy(void)
1635 {
1636 kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_MAU - 1]);
1637 kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_CWQ - 1]);
1638 queue_cache[HV_NCS_QTYPE_MAU - 1] = NULL;
1639 queue_cache[HV_NCS_QTYPE_CWQ - 1] = NULL;
1640 }
1641
1642 static long spu_queue_register_workfn(void *arg)
1643 {
1644 struct spu_qreg *qr = arg;
1645 struct spu_queue *p = qr->queue;
1646 unsigned long q_type = qr->type;
1647 unsigned long hv_ret;
1648
1649 hv_ret = sun4v_ncs_qconf(q_type, __pa(p->q),
1650 CWQ_NUM_ENTRIES, &p->qhandle);
1651 if (!hv_ret)
1652 sun4v_ncs_sethead_marker(p->qhandle, 0);
1653
1654 return hv_ret ? -EINVAL : 0;
1655 }
1656
1657 static int spu_queue_register(struct spu_queue *p, unsigned long q_type)
1658 {
1659 int cpu = cpumask_any_and(&p->sharing, cpu_online_mask);
1660 struct spu_qreg qr = { .queue = p, .type = q_type };
1661
1662 return work_on_cpu_safe(cpu, spu_queue_register_workfn, &qr);
1663 }
1664
1665 static int spu_queue_setup(struct spu_queue *p)
1666 {
1667 int err;
1668
1669 p->q = new_queue(p->q_type);
1670 if (!p->q)
1671 return -ENOMEM;
1672
1673 err = spu_queue_register(p, p->q_type);
1674 if (err) {
1675 free_queue(p->q, p->q_type);
1676 p->q = NULL;
1677 }
1678
1679 return err;
1680 }
1681
1682 static void spu_queue_destroy(struct spu_queue *p)
1683 {
1684 unsigned long hv_ret;
1685
1686 if (!p->q)
1687 return;
1688
1689 hv_ret = sun4v_ncs_qconf(p->q_type, p->qhandle, 0, &p->qhandle);
1690
1691 if (!hv_ret)
1692 free_queue(p->q, p->q_type);
1693 }
1694
1695 static void spu_list_destroy(struct list_head *list)
1696 {
1697 struct spu_queue *p, *n;
1698
1699 list_for_each_entry_safe(p, n, list, list) {
1700 int i;
1701
1702 for (i = 0; i < NR_CPUS; i++) {
1703 if (cpu_to_cwq[i] == p)
1704 cpu_to_cwq[i] = NULL;
1705 }
1706
1707 if (p->irq) {
1708 free_irq(p->irq, p);
1709 p->irq = 0;
1710 }
1711 spu_queue_destroy(p);
1712 list_del(&p->list);
1713 kfree(p);
1714 }
1715 }
1716
1717 /* Walk the backward arcs of a CWQ 'exec-unit' node,
1718 * gathering cpu membership information.
1719 */
1720 static int spu_mdesc_walk_arcs(struct mdesc_handle *mdesc,
1721 struct platform_device *dev,
1722 u64 node, struct spu_queue *p,
1723 struct spu_queue **table)
1724 {
1725 u64 arc;
1726
1727 mdesc_for_each_arc(arc, mdesc, node, MDESC_ARC_TYPE_BACK) {
1728 u64 tgt = mdesc_arc_target(mdesc, arc);
1729 const char *name = mdesc_node_name(mdesc, tgt);
1730 const u64 *id;
1731
1732 if (strcmp(name, "cpu"))
1733 continue;
1734 id = mdesc_get_property(mdesc, tgt, "id", NULL);
1735 if (table[*id] != NULL) {
1736 dev_err(&dev->dev, "%pOF: SPU cpu slot already set.\n",
1737 dev->dev.of_node);
1738 return -EINVAL;
1739 }
1740 cpumask_set_cpu(*id, &p->sharing);
1741 table[*id] = p;
1742 }
1743 return 0;
1744 }
1745
1746 /* Process an 'exec-unit' MDESC node of type 'cwq'. */
1747 static int handle_exec_unit(struct spu_mdesc_info *ip, struct list_head *list,
1748 struct platform_device *dev, struct mdesc_handle *mdesc,
1749 u64 node, const char *iname, unsigned long q_type,
1750 irq_handler_t handler, struct spu_queue **table)
1751 {
1752 struct spu_queue *p;
1753 int err;
1754
1755 p = kzalloc(sizeof(struct spu_queue), GFP_KERNEL);
1756 if (!p) {
1757 dev_err(&dev->dev, "%pOF: Could not allocate SPU queue.\n",
1758 dev->dev.of_node);
1759 return -ENOMEM;
1760 }
1761
1762 cpumask_clear(&p->sharing);
1763 spin_lock_init(&p->lock);
1764 p->q_type = q_type;
1765 INIT_LIST_HEAD(&p->jobs);
1766 list_add(&p->list, list);
1767
1768 err = spu_mdesc_walk_arcs(mdesc, dev, node, p, table);
1769 if (err)
1770 return err;
1771
1772 err = spu_queue_setup(p);
1773 if (err)
1774 return err;
1775
1776 return spu_map_ino(dev, ip, iname, p, handler);
1777 }
1778
1779 static int spu_mdesc_scan(struct mdesc_handle *mdesc, struct platform_device *dev,
1780 struct spu_mdesc_info *ip, struct list_head *list,
1781 const char *exec_name, unsigned long q_type,
1782 irq_handler_t handler, struct spu_queue **table)
1783 {
1784 int err = 0;
1785 u64 node;
1786
1787 mdesc_for_each_node_by_name(mdesc, node, "exec-unit") {
1788 const char *type;
1789
1790 type = mdesc_get_property(mdesc, node, "type", NULL);
1791 if (!type || strcmp(type, exec_name))
1792 continue;
1793
1794 err = handle_exec_unit(ip, list, dev, mdesc, node,
1795 exec_name, q_type, handler, table);
1796 if (err) {
1797 spu_list_destroy(list);
1798 break;
1799 }
1800 }
1801
1802 return err;
1803 }
1804
1805 static int get_irq_props(struct mdesc_handle *mdesc, u64 node,
1806 struct spu_mdesc_info *ip)
1807 {
1808 const u64 *ino;
1809 int ino_len;
1810 int i;
1811
1812 ino = mdesc_get_property(mdesc, node, "ino", &ino_len);
1813 if (!ino) {
1814 printk("NO 'ino'\n");
1815 return -ENODEV;
1816 }
1817
1818 ip->num_intrs = ino_len / sizeof(u64);
1819 ip->ino_table = kzalloc((sizeof(struct ino_blob) *
1820 ip->num_intrs),
1821 GFP_KERNEL);
1822 if (!ip->ino_table)
1823 return -ENOMEM;
1824
1825 for (i = 0; i < ip->num_intrs; i++) {
1826 struct ino_blob *b = &ip->ino_table[i];
1827 b->intr = i + 1;
1828 b->ino = ino[i];
1829 }
1830
1831 return 0;
1832 }
1833
1834 static int grab_mdesc_irq_props(struct mdesc_handle *mdesc,
1835 struct platform_device *dev,
1836 struct spu_mdesc_info *ip,
1837 const char *node_name)
1838 {
1839 const unsigned int *reg;
1840 u64 node;
1841
1842 reg = of_get_property(dev->dev.of_node, "reg", NULL);
1843 if (!reg)
1844 return -ENODEV;
1845
1846 mdesc_for_each_node_by_name(mdesc, node, "virtual-device") {
1847 const char *name;
1848 const u64 *chdl;
1849
1850 name = mdesc_get_property(mdesc, node, "name", NULL);
1851 if (!name || strcmp(name, node_name))
1852 continue;
1853 chdl = mdesc_get_property(mdesc, node, "cfg-handle", NULL);
1854 if (!chdl || (*chdl != *reg))
1855 continue;
1856 ip->cfg_handle = *chdl;
1857 return get_irq_props(mdesc, node, ip);
1858 }
1859
1860 return -ENODEV;
1861 }
1862
1863 static unsigned long n2_spu_hvapi_major;
1864 static unsigned long n2_spu_hvapi_minor;
1865
1866 static int n2_spu_hvapi_register(void)
1867 {
1868 int err;
1869
1870 n2_spu_hvapi_major = 2;
1871 n2_spu_hvapi_minor = 0;
1872
1873 err = sun4v_hvapi_register(HV_GRP_NCS,
1874 n2_spu_hvapi_major,
1875 &n2_spu_hvapi_minor);
1876
1877 if (!err)
1878 pr_info("Registered NCS HVAPI version %lu.%lu\n",
1879 n2_spu_hvapi_major,
1880 n2_spu_hvapi_minor);
1881
1882 return err;
1883 }
1884
1885 static void n2_spu_hvapi_unregister(void)
1886 {
1887 sun4v_hvapi_unregister(HV_GRP_NCS);
1888 }
1889
1890 static int global_ref;
1891
1892 static int grab_global_resources(void)
1893 {
1894 int err = 0;
1895
1896 mutex_lock(&spu_lock);
1897
1898 if (global_ref++)
1899 goto out;
1900
1901 err = n2_spu_hvapi_register();
1902 if (err)
1903 goto out;
1904
1905 err = queue_cache_init();
1906 if (err)
1907 goto out_hvapi_release;
1908
1909 err = -ENOMEM;
1910 cpu_to_cwq = kcalloc(NR_CPUS, sizeof(struct spu_queue *),
1911 GFP_KERNEL);
1912 if (!cpu_to_cwq)
1913 goto out_queue_cache_destroy;
1914
1915 cpu_to_mau = kcalloc(NR_CPUS, sizeof(struct spu_queue *),
1916 GFP_KERNEL);
1917 if (!cpu_to_mau)
1918 goto out_free_cwq_table;
1919
1920 err = 0;
1921
1922 out:
1923 if (err)
1924 global_ref--;
1925 mutex_unlock(&spu_lock);
1926 return err;
1927
1928 out_free_cwq_table:
1929 kfree(cpu_to_cwq);
1930 cpu_to_cwq = NULL;
1931
1932 out_queue_cache_destroy:
1933 queue_cache_destroy();
1934
1935 out_hvapi_release:
1936 n2_spu_hvapi_unregister();
1937 goto out;
1938 }
1939
1940 static void release_global_resources(void)
1941 {
1942 mutex_lock(&spu_lock);
1943 if (!--global_ref) {
1944 kfree(cpu_to_cwq);
1945 cpu_to_cwq = NULL;
1946
1947 kfree(cpu_to_mau);
1948 cpu_to_mau = NULL;
1949
1950 queue_cache_destroy();
1951 n2_spu_hvapi_unregister();
1952 }
1953 mutex_unlock(&spu_lock);
1954 }
1955
1956 static struct n2_crypto *alloc_n2cp(void)
1957 {
1958 struct n2_crypto *np = kzalloc(sizeof(struct n2_crypto), GFP_KERNEL);
1959
1960 if (np)
1961 INIT_LIST_HEAD(&np->cwq_list);
1962
1963 return np;
1964 }
1965
1966 static void free_n2cp(struct n2_crypto *np)
1967 {
1968 kfree(np->cwq_info.ino_table);
1969 np->cwq_info.ino_table = NULL;
1970
1971 kfree(np);
1972 }
1973
1974 static void n2_spu_driver_version(void)
1975 {
1976 static int n2_spu_version_printed;
1977
1978 if (n2_spu_version_printed++ == 0)
1979 pr_info("%s", version);
1980 }
1981
1982 static int n2_crypto_probe(struct platform_device *dev)
1983 {
1984 struct mdesc_handle *mdesc;
1985 struct n2_crypto *np;
1986 int err;
1987
1988 n2_spu_driver_version();
1989
1990 pr_info("Found N2CP at %pOF\n", dev->dev.of_node);
1991
1992 np = alloc_n2cp();
1993 if (!np) {
1994 dev_err(&dev->dev, "%pOF: Unable to allocate n2cp.\n",
1995 dev->dev.of_node);
1996 return -ENOMEM;
1997 }
1998
1999 err = grab_global_resources();
2000 if (err) {
2001 dev_err(&dev->dev, "%pOF: Unable to grab global resources.\n",
2002 dev->dev.of_node);
2003 goto out_free_n2cp;
2004 }
2005
2006 mdesc = mdesc_grab();
2007
2008 if (!mdesc) {
2009 dev_err(&dev->dev, "%pOF: Unable to grab MDESC.\n",
2010 dev->dev.of_node);
2011 err = -ENODEV;
2012 goto out_free_global;
2013 }
2014 err = grab_mdesc_irq_props(mdesc, dev, &np->cwq_info, "n2cp");
2015 if (err) {
2016 dev_err(&dev->dev, "%pOF: Unable to grab IRQ props.\n",
2017 dev->dev.of_node);
2018 mdesc_release(mdesc);
2019 goto out_free_global;
2020 }
2021
2022 err = spu_mdesc_scan(mdesc, dev, &np->cwq_info, &np->cwq_list,
2023 "cwq", HV_NCS_QTYPE_CWQ, cwq_intr,
2024 cpu_to_cwq);
2025 mdesc_release(mdesc);
2026
2027 if (err) {
2028 dev_err(&dev->dev, "%pOF: CWQ MDESC scan failed.\n",
2029 dev->dev.of_node);
2030 goto out_free_global;
2031 }
2032
2033 err = n2_register_algs();
2034 if (err) {
2035 dev_err(&dev->dev, "%pOF: Unable to register algorithms.\n",
2036 dev->dev.of_node);
2037 goto out_free_spu_list;
2038 }
2039
2040 dev_set_drvdata(&dev->dev, np);
2041
2042 return 0;
2043
2044 out_free_spu_list:
2045 spu_list_destroy(&np->cwq_list);
2046
2047 out_free_global:
2048 release_global_resources();
2049
2050 out_free_n2cp:
2051 free_n2cp(np);
2052
2053 return err;
2054 }
2055
2056 static int n2_crypto_remove(struct platform_device *dev)
2057 {
2058 struct n2_crypto *np = dev_get_drvdata(&dev->dev);
2059
2060 n2_unregister_algs();
2061
2062 spu_list_destroy(&np->cwq_list);
2063
2064 release_global_resources();
2065
2066 free_n2cp(np);
2067
2068 return 0;
2069 }
2070
2071 static struct n2_mau *alloc_ncp(void)
2072 {
2073 struct n2_mau *mp = kzalloc(sizeof(struct n2_mau), GFP_KERNEL);
2074
2075 if (mp)
2076 INIT_LIST_HEAD(&mp->mau_list);
2077
2078 return mp;
2079 }
2080
2081 static void free_ncp(struct n2_mau *mp)
2082 {
2083 kfree(mp->mau_info.ino_table);
2084 mp->mau_info.ino_table = NULL;
2085
2086 kfree(mp);
2087 }
2088
2089 static int n2_mau_probe(struct platform_device *dev)
2090 {
2091 struct mdesc_handle *mdesc;
2092 struct n2_mau *mp;
2093 int err;
2094
2095 n2_spu_driver_version();
2096
2097 pr_info("Found NCP at %pOF\n", dev->dev.of_node);
2098
2099 mp = alloc_ncp();
2100 if (!mp) {
2101 dev_err(&dev->dev, "%pOF: Unable to allocate ncp.\n",
2102 dev->dev.of_node);
2103 return -ENOMEM;
2104 }
2105
2106 err = grab_global_resources();
2107 if (err) {
2108 dev_err(&dev->dev, "%pOF: Unable to grab global resources.\n",
2109 dev->dev.of_node);
2110 goto out_free_ncp;
2111 }
2112
2113 mdesc = mdesc_grab();
2114
2115 if (!mdesc) {
2116 dev_err(&dev->dev, "%pOF: Unable to grab MDESC.\n",
2117 dev->dev.of_node);
2118 err = -ENODEV;
2119 goto out_free_global;
2120 }
2121
2122 err = grab_mdesc_irq_props(mdesc, dev, &mp->mau_info, "ncp");
2123 if (err) {
2124 dev_err(&dev->dev, "%pOF: Unable to grab IRQ props.\n",
2125 dev->dev.of_node);
2126 mdesc_release(mdesc);
2127 goto out_free_global;
2128 }
2129
2130 err = spu_mdesc_scan(mdesc, dev, &mp->mau_info, &mp->mau_list,
2131 "mau", HV_NCS_QTYPE_MAU, mau_intr,
2132 cpu_to_mau);
2133 mdesc_release(mdesc);
2134
2135 if (err) {
2136 dev_err(&dev->dev, "%pOF: MAU MDESC scan failed.\n",
2137 dev->dev.of_node);
2138 goto out_free_global;
2139 }
2140
2141 dev_set_drvdata(&dev->dev, mp);
2142
2143 return 0;
2144
2145 out_free_global:
2146 release_global_resources();
2147
2148 out_free_ncp:
2149 free_ncp(mp);
2150
2151 return err;
2152 }
2153
2154 static int n2_mau_remove(struct platform_device *dev)
2155 {
2156 struct n2_mau *mp = dev_get_drvdata(&dev->dev);
2157
2158 spu_list_destroy(&mp->mau_list);
2159
2160 release_global_resources();
2161
2162 free_ncp(mp);
2163
2164 return 0;
2165 }
2166
2167 static const struct of_device_id n2_crypto_match[] = {
2168 {
2169 .name = "n2cp",
2170 .compatible = "SUNW,n2-cwq",
2171 },
2172 {
2173 .name = "n2cp",
2174 .compatible = "SUNW,vf-cwq",
2175 },
2176 {
2177 .name = "n2cp",
2178 .compatible = "SUNW,kt-cwq",
2179 },
2180 {},
2181 };
2182
2183 MODULE_DEVICE_TABLE(of, n2_crypto_match);
2184
2185 static struct platform_driver n2_crypto_driver = {
2186 .driver = {
2187 .name = "n2cp",
2188 .of_match_table = n2_crypto_match,
2189 },
2190 .probe = n2_crypto_probe,
2191 .remove = n2_crypto_remove,
2192 };
2193
2194 static const struct of_device_id n2_mau_match[] = {
2195 {
2196 .name = "ncp",
2197 .compatible = "SUNW,n2-mau",
2198 },
2199 {
2200 .name = "ncp",
2201 .compatible = "SUNW,vf-mau",
2202 },
2203 {
2204 .name = "ncp",
2205 .compatible = "SUNW,kt-mau",
2206 },
2207 {},
2208 };
2209
2210 MODULE_DEVICE_TABLE(of, n2_mau_match);
2211
2212 static struct platform_driver n2_mau_driver = {
2213 .driver = {
2214 .name = "ncp",
2215 .of_match_table = n2_mau_match,
2216 },
2217 .probe = n2_mau_probe,
2218 .remove = n2_mau_remove,
2219 };
2220
2221 static struct platform_driver * const drivers[] = {
2222 &n2_crypto_driver,
2223 &n2_mau_driver,
2224 };
2225
2226 static int __init n2_init(void)
2227 {
2228 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2229 }
2230
2231 static void __exit n2_exit(void)
2232 {
2233 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2234 }
2235
2236 module_init(n2_init);
2237 module_exit(n2_exit);
Linux with added FPC-III support