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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / crypto / omap-aes.c
blob824ddf2a66ffdf4d1c64939760e4f4f6f3539999
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Cryptographic API.
4 *
5 * Support for OMAP AES HW acceleration.
6 *
7 * Copyright (c) 2010 Nokia Corporation
8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
9 * Copyright (c) 2011 Texas Instruments Incorporated
10 */
11
12 #define pr_fmt(fmt) "%20s: " fmt, __func__
13 #define prn(num) pr_debug(#num "=%d\n", num)
14 #define prx(num) pr_debug(#num "=%x\n", num)
15
16 #include <linux/err.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/kernel.h>
21 #include <linux/platform_device.h>
22 #include <linux/scatterlist.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmaengine.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/of_address.h>
29 #include <linux/io.h>
30 #include <linux/crypto.h>
31 #include <linux/interrupt.h>
32 #include <crypto/scatterwalk.h>
33 #include <crypto/aes.h>
34 #include <crypto/gcm.h>
35 #include <crypto/engine.h>
36 #include <crypto/internal/skcipher.h>
37 #include <crypto/internal/aead.h>
38
39 #include "omap-crypto.h"
40 #include "omap-aes.h"
41
42 /* keep registered devices data here */
43 static LIST_HEAD(dev_list);
44 static DEFINE_SPINLOCK(list_lock);
45
46 static int aes_fallback_sz = 200;
47
48 #ifdef DEBUG
49 #define omap_aes_read(dd, offset) \
50 ({ \
51 int _read_ret; \
52 _read_ret = __raw_readl(dd->io_base + offset); \
53 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \
54 offset, _read_ret); \
55 _read_ret; \
56 })
57 #else
58 inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
59 {
60 return __raw_readl(dd->io_base + offset);
61 }
62 #endif
63
64 #ifdef DEBUG
65 #define omap_aes_write(dd, offset, value) \
66 do { \
67 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
68 offset, value); \
69 __raw_writel(value, dd->io_base + offset); \
70 } while (0)
71 #else
72 inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
73 u32 value)
74 {
75 __raw_writel(value, dd->io_base + offset);
76 }
77 #endif
78
79 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
80 u32 value, u32 mask)
81 {
82 u32 val;
83
84 val = omap_aes_read(dd, offset);
85 val &= ~mask;
86 val |= value;
87 omap_aes_write(dd, offset, val);
88 }
89
90 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
91 u32 *value, int count)
92 {
93 for (; count--; value++, offset += 4)
94 omap_aes_write(dd, offset, *value);
95 }
96
97 static int omap_aes_hw_init(struct omap_aes_dev *dd)
98 {
99 int err;
100
101 if (!(dd->flags & FLAGS_INIT)) {
102 dd->flags |= FLAGS_INIT;
103 dd->err = 0;
104 }
105
106 err = pm_runtime_get_sync(dd->dev);
107 if (err < 0) {
108 dev_err(dd->dev, "failed to get sync: %d\n", err);
109 return err;
110 }
111
112 return 0;
113 }
114
115 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd)
116 {
117 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT);
118 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT);
119 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT);
120 }
121
122 int omap_aes_write_ctrl(struct omap_aes_dev *dd)
123 {
124 struct omap_aes_reqctx *rctx;
125 unsigned int key32;
126 int i, err;
127 u32 val;
128
129 err = omap_aes_hw_init(dd);
130 if (err)
131 return err;
132
133 key32 = dd->ctx->keylen / sizeof(u32);
134
135 /* RESET the key as previous HASH keys should not get affected*/
136 if (dd->flags & FLAGS_GCM)
137 for (i = 0; i < 0x40; i = i + 4)
138 omap_aes_write(dd, i, 0x0);
139
140 for (i = 0; i < key32; i++) {
141 omap_aes_write(dd, AES_REG_KEY(dd, i),
142 __le32_to_cpu(dd->ctx->key[i]));
143 }
144
145 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv)
146 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (void *)dd->req->iv, 4);
147
148 if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) {
149 rctx = aead_request_ctx(dd->aead_req);
150 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4);
151 }
152
153 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
154 if (dd->flags & FLAGS_CBC)
155 val |= AES_REG_CTRL_CBC;
156
157 if (dd->flags & (FLAGS_CTR | FLAGS_GCM))
158 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
159
160 if (dd->flags & FLAGS_GCM)
161 val |= AES_REG_CTRL_GCM;
162
163 if (dd->flags & FLAGS_ENCRYPT)
164 val |= AES_REG_CTRL_DIRECTION;
165
166 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
167
168 return 0;
169 }
170
171 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
172 {
173 u32 mask, val;
174
175 val = dd->pdata->dma_start;
176
177 if (dd->dma_lch_out != NULL)
178 val |= dd->pdata->dma_enable_out;
179 if (dd->dma_lch_in != NULL)
180 val |= dd->pdata->dma_enable_in;
181
182 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
183 dd->pdata->dma_start;
184
185 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
186
187 }
188
189 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
190 {
191 omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
192 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
193 if (dd->flags & FLAGS_GCM)
194 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len);
195
196 omap_aes_dma_trigger_omap2(dd, length);
197 }
198
199 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
200 {
201 u32 mask;
202
203 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
204 dd->pdata->dma_start;
205
206 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
207 }
208
209 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx)
210 {
211 struct omap_aes_dev *dd;
212
213 spin_lock_bh(&list_lock);
214 dd = list_first_entry(&dev_list, struct omap_aes_dev, list);
215 list_move_tail(&dd->list, &dev_list);
216 rctx->dd = dd;
217 spin_unlock_bh(&list_lock);
218
219 return dd;
220 }
221
222 static void omap_aes_dma_out_callback(void *data)
223 {
224 struct omap_aes_dev *dd = data;
225
226 /* dma_lch_out - completed */
227 tasklet_schedule(&dd->done_task);
228 }
229
230 static int omap_aes_dma_init(struct omap_aes_dev *dd)
231 {
232 int err;
233
234 dd->dma_lch_out = NULL;
235 dd->dma_lch_in = NULL;
236
237 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
238 if (IS_ERR(dd->dma_lch_in)) {
239 dev_err(dd->dev, "Unable to request in DMA channel\n");
240 return PTR_ERR(dd->dma_lch_in);
241 }
242
243 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
244 if (IS_ERR(dd->dma_lch_out)) {
245 dev_err(dd->dev, "Unable to request out DMA channel\n");
246 err = PTR_ERR(dd->dma_lch_out);
247 goto err_dma_out;
248 }
249
250 return 0;
251
252 err_dma_out:
253 dma_release_channel(dd->dma_lch_in);
254
255 return err;
256 }
257
258 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
259 {
260 if (dd->pio_only)
261 return;
262
263 dma_release_channel(dd->dma_lch_out);
264 dma_release_channel(dd->dma_lch_in);
265 }
266
267 static int omap_aes_crypt_dma(struct omap_aes_dev *dd,
268 struct scatterlist *in_sg,
269 struct scatterlist *out_sg,
270 int in_sg_len, int out_sg_len)
271 {
272 struct dma_async_tx_descriptor *tx_in, *tx_out = NULL, *cb_desc;
273 struct dma_slave_config cfg;
274 int ret;
275
276 if (dd->pio_only) {
277 scatterwalk_start(&dd->in_walk, dd->in_sg);
278 if (out_sg_len)
279 scatterwalk_start(&dd->out_walk, dd->out_sg);
280
281 /* Enable DATAIN interrupt and let it take
282 care of the rest */
283 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
284 return 0;
285 }
286
287 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
288
289 memset(&cfg, 0, sizeof(cfg));
290
291 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
292 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
293 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
294 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
295 cfg.src_maxburst = DST_MAXBURST;
296 cfg.dst_maxburst = DST_MAXBURST;
297
298 /* IN */
299 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
300 if (ret) {
301 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
302 ret);
303 return ret;
304 }
305
306 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
307 DMA_MEM_TO_DEV,
308 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
309 if (!tx_in) {
310 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
311 return -EINVAL;
312 }
313
314 /* No callback necessary */
315 tx_in->callback_param = dd;
316 tx_in->callback = NULL;
317
318 /* OUT */
319 if (out_sg_len) {
320 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
321 if (ret) {
322 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
323 ret);
324 return ret;
325 }
326
327 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg,
328 out_sg_len,
329 DMA_DEV_TO_MEM,
330 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
331 if (!tx_out) {
332 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
333 return -EINVAL;
334 }
335
336 cb_desc = tx_out;
337 } else {
338 cb_desc = tx_in;
339 }
340
341 if (dd->flags & FLAGS_GCM)
342 cb_desc->callback = omap_aes_gcm_dma_out_callback;
343 else
344 cb_desc->callback = omap_aes_dma_out_callback;
345 cb_desc->callback_param = dd;
346
347
348 dmaengine_submit(tx_in);
349 if (tx_out)
350 dmaengine_submit(tx_out);
351
352 dma_async_issue_pending(dd->dma_lch_in);
353 if (out_sg_len)
354 dma_async_issue_pending(dd->dma_lch_out);
355
356 /* start DMA */
357 dd->pdata->trigger(dd, dd->total);
358
359 return 0;
360 }
361
362 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
363 {
364 int err;
365
366 pr_debug("total: %d\n", dd->total);
367
368 if (!dd->pio_only) {
369 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
370 DMA_TO_DEVICE);
371 if (!err) {
372 dev_err(dd->dev, "dma_map_sg() error\n");
373 return -EINVAL;
374 }
375
376 if (dd->out_sg_len) {
377 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
378 DMA_FROM_DEVICE);
379 if (!err) {
380 dev_err(dd->dev, "dma_map_sg() error\n");
381 return -EINVAL;
382 }
383 }
384 }
385
386 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len,
387 dd->out_sg_len);
388 if (err && !dd->pio_only) {
389 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
390 if (dd->out_sg_len)
391 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
392 DMA_FROM_DEVICE);
393 }
394
395 return err;
396 }
397
398 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
399 {
400 struct skcipher_request *req = dd->req;
401
402 pr_debug("err: %d\n", err);
403
404 crypto_finalize_skcipher_request(dd->engine, req, err);
405
406 pm_runtime_mark_last_busy(dd->dev);
407 pm_runtime_put_autosuspend(dd->dev);
408 }
409
410 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
411 {
412 pr_debug("total: %d\n", dd->total);
413
414 omap_aes_dma_stop(dd);
415
416
417 return 0;
418 }
419
420 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
421 struct skcipher_request *req)
422 {
423 if (req)
424 return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
425
426 return 0;
427 }
428
429 static int omap_aes_prepare_req(struct crypto_engine *engine,
430 void *areq)
431 {
432 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
433 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
434 crypto_skcipher_reqtfm(req));
435 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
436 struct omap_aes_dev *dd = rctx->dd;
437 int ret;
438 u16 flags;
439
440 if (!dd)
441 return -ENODEV;
442
443 /* assign new request to device */
444 dd->req = req;
445 dd->total = req->cryptlen;
446 dd->total_save = req->cryptlen;
447 dd->in_sg = req->src;
448 dd->out_sg = req->dst;
449 dd->orig_out = req->dst;
450
451 flags = OMAP_CRYPTO_COPY_DATA;
452 if (req->src == req->dst)
453 flags |= OMAP_CRYPTO_FORCE_COPY;
454
455 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE,
456 dd->in_sgl, flags,
457 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
458 if (ret)
459 return ret;
460
461 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE,
462 &dd->out_sgl, 0,
463 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
464 if (ret)
465 return ret;
466
467 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
468 if (dd->in_sg_len < 0)
469 return dd->in_sg_len;
470
471 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
472 if (dd->out_sg_len < 0)
473 return dd->out_sg_len;
474
475 rctx->mode &= FLAGS_MODE_MASK;
476 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
477
478 dd->ctx = ctx;
479 rctx->dd = dd;
480
481 return omap_aes_write_ctrl(dd);
482 }
483
484 static int omap_aes_crypt_req(struct crypto_engine *engine,
485 void *areq)
486 {
487 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
488 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
489 struct omap_aes_dev *dd = rctx->dd;
490
491 if (!dd)
492 return -ENODEV;
493
494 return omap_aes_crypt_dma_start(dd);
495 }
496
497 static void omap_aes_copy_ivout(struct omap_aes_dev *dd, u8 *ivbuf)
498 {
499 int i;
500
501 for (i = 0; i < 4; i++)
502 ((u32 *)ivbuf)[i] = omap_aes_read(dd, AES_REG_IV(dd, i));
503 }
504
505 static void omap_aes_done_task(unsigned long data)
506 {
507 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
508
509 pr_debug("enter done_task\n");
510
511 if (!dd->pio_only) {
512 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
513 DMA_FROM_DEVICE);
514 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
515 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
516 DMA_FROM_DEVICE);
517 omap_aes_crypt_dma_stop(dd);
518 }
519
520 omap_crypto_cleanup(dd->in_sg, NULL, 0, dd->total_save,
521 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
522
523 omap_crypto_cleanup(dd->out_sg, dd->orig_out, 0, dd->total_save,
524 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
525
526 /* Update IV output */
527 if (dd->flags & (FLAGS_CBC | FLAGS_CTR))
528 omap_aes_copy_ivout(dd, dd->req->iv);
529
530 omap_aes_finish_req(dd, 0);
531
532 pr_debug("exit\n");
533 }
534
535 static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode)
536 {
537 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
538 crypto_skcipher_reqtfm(req));
539 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
540 struct omap_aes_dev *dd;
541 int ret;
542
543 if ((req->cryptlen % AES_BLOCK_SIZE) && !(mode & FLAGS_CTR))
544 return -EINVAL;
545
546 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
547 !!(mode & FLAGS_ENCRYPT),
548 !!(mode & FLAGS_CBC));
549
550 if (req->cryptlen < aes_fallback_sz) {
551 SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
552
553 skcipher_request_set_sync_tfm(subreq, ctx->fallback);
554 skcipher_request_set_callback(subreq, req->base.flags, NULL,
555 NULL);
556 skcipher_request_set_crypt(subreq, req->src, req->dst,
557 req->cryptlen, req->iv);
558
559 if (mode & FLAGS_ENCRYPT)
560 ret = crypto_skcipher_encrypt(subreq);
561 else
562 ret = crypto_skcipher_decrypt(subreq);
563
564 skcipher_request_zero(subreq);
565 return ret;
566 }
567 dd = omap_aes_find_dev(rctx);
568 if (!dd)
569 return -ENODEV;
570
571 rctx->mode = mode;
572
573 return omap_aes_handle_queue(dd, req);
574 }
575
576 /* ********************** ALG API ************************************ */
577
578 static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
579 unsigned int keylen)
580 {
581 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
582 int ret;
583
584 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
585 keylen != AES_KEYSIZE_256)
586 return -EINVAL;
587
588 pr_debug("enter, keylen: %d\n", keylen);
589
590 memcpy(ctx->key, key, keylen);
591 ctx->keylen = keylen;
592
593 crypto_sync_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK);
594 crypto_sync_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags &
595 CRYPTO_TFM_REQ_MASK);
596
597 ret = crypto_sync_skcipher_setkey(ctx->fallback, key, keylen);
598 if (!ret)
599 return 0;
600
601 return 0;
602 }
603
604 static int omap_aes_ecb_encrypt(struct skcipher_request *req)
605 {
606 return omap_aes_crypt(req, FLAGS_ENCRYPT);
607 }
608
609 static int omap_aes_ecb_decrypt(struct skcipher_request *req)
610 {
611 return omap_aes_crypt(req, 0);
612 }
613
614 static int omap_aes_cbc_encrypt(struct skcipher_request *req)
615 {
616 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
617 }
618
619 static int omap_aes_cbc_decrypt(struct skcipher_request *req)
620 {
621 return omap_aes_crypt(req, FLAGS_CBC);
622 }
623
624 static int omap_aes_ctr_encrypt(struct skcipher_request *req)
625 {
626 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
627 }
628
629 static int omap_aes_ctr_decrypt(struct skcipher_request *req)
630 {
631 return omap_aes_crypt(req, FLAGS_CTR);
632 }
633
634 static int omap_aes_prepare_req(struct crypto_engine *engine,
635 void *req);
636 static int omap_aes_crypt_req(struct crypto_engine *engine,
637 void *req);
638
639 static int omap_aes_init_tfm(struct crypto_skcipher *tfm)
640 {
641 const char *name = crypto_tfm_alg_name(&tfm->base);
642 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
643 struct crypto_sync_skcipher *blk;
644
645 blk = crypto_alloc_sync_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
646 if (IS_ERR(blk))
647 return PTR_ERR(blk);
648
649 ctx->fallback = blk;
650
651 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx));
652
653 ctx->enginectx.op.prepare_request = omap_aes_prepare_req;
654 ctx->enginectx.op.unprepare_request = NULL;
655 ctx->enginectx.op.do_one_request = omap_aes_crypt_req;
656
657 return 0;
658 }
659
660 static void omap_aes_exit_tfm(struct crypto_skcipher *tfm)
661 {
662 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
663
664 if (ctx->fallback)
665 crypto_free_sync_skcipher(ctx->fallback);
666
667 ctx->fallback = NULL;
668 }
669
670 /* ********************** ALGS ************************************ */
671
672 static struct skcipher_alg algs_ecb_cbc[] = {
673 {
674 .base.cra_name = "ecb(aes)",
675 .base.cra_driver_name = "ecb-aes-omap",
676 .base.cra_priority = 300,
677 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
678 CRYPTO_ALG_ASYNC |
679 CRYPTO_ALG_NEED_FALLBACK,
680 .base.cra_blocksize = AES_BLOCK_SIZE,
681 .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
682 .base.cra_module = THIS_MODULE,
683
684 .min_keysize = AES_MIN_KEY_SIZE,
685 .max_keysize = AES_MAX_KEY_SIZE,
686 .setkey = omap_aes_setkey,
687 .encrypt = omap_aes_ecb_encrypt,
688 .decrypt = omap_aes_ecb_decrypt,
689 .init = omap_aes_init_tfm,
690 .exit = omap_aes_exit_tfm,
691 },
692 {
693 .base.cra_name = "cbc(aes)",
694 .base.cra_driver_name = "cbc-aes-omap",
695 .base.cra_priority = 300,
696 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
697 CRYPTO_ALG_ASYNC |
698 CRYPTO_ALG_NEED_FALLBACK,
699 .base.cra_blocksize = AES_BLOCK_SIZE,
700 .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
701 .base.cra_module = THIS_MODULE,
702
703 .min_keysize = AES_MIN_KEY_SIZE,
704 .max_keysize = AES_MAX_KEY_SIZE,
705 .ivsize = AES_BLOCK_SIZE,
706 .setkey = omap_aes_setkey,
707 .encrypt = omap_aes_cbc_encrypt,
708 .decrypt = omap_aes_cbc_decrypt,
709 .init = omap_aes_init_tfm,
710 .exit = omap_aes_exit_tfm,
711 }
712 };
713
714 static struct skcipher_alg algs_ctr[] = {
715 {
716 .base.cra_name = "ctr(aes)",
717 .base.cra_driver_name = "ctr-aes-omap",
718 .base.cra_priority = 300,
719 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
720 CRYPTO_ALG_ASYNC |
721 CRYPTO_ALG_NEED_FALLBACK,
722 .base.cra_blocksize = 1,
723 .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
724 .base.cra_module = THIS_MODULE,
725
726 .min_keysize = AES_MIN_KEY_SIZE,
727 .max_keysize = AES_MAX_KEY_SIZE,
728 .ivsize = AES_BLOCK_SIZE,
729 .setkey = omap_aes_setkey,
730 .encrypt = omap_aes_ctr_encrypt,
731 .decrypt = omap_aes_ctr_decrypt,
732 .init = omap_aes_init_tfm,
733 .exit = omap_aes_exit_tfm,
734 }
735 };
736
737 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
738 {
739 .algs_list = algs_ecb_cbc,
740 .size = ARRAY_SIZE(algs_ecb_cbc),
741 },
742 };
743
744 static struct aead_alg algs_aead_gcm[] = {
745 {
746 .base = {
747 .cra_name = "gcm(aes)",
748 .cra_driver_name = "gcm-aes-omap",
749 .cra_priority = 300,
750 .cra_flags = CRYPTO_ALG_ASYNC |
751 CRYPTO_ALG_KERN_DRIVER_ONLY,
752 .cra_blocksize = 1,
753 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx),
754 .cra_alignmask = 0xf,
755 .cra_module = THIS_MODULE,
756 },
757 .init = omap_aes_gcm_cra_init,
758 .ivsize = GCM_AES_IV_SIZE,
759 .maxauthsize = AES_BLOCK_SIZE,
760 .setkey = omap_aes_gcm_setkey,
761 .setauthsize = omap_aes_gcm_setauthsize,
762 .encrypt = omap_aes_gcm_encrypt,
763 .decrypt = omap_aes_gcm_decrypt,
764 },
765 {
766 .base = {
767 .cra_name = "rfc4106(gcm(aes))",
768 .cra_driver_name = "rfc4106-gcm-aes-omap",
769 .cra_priority = 300,
770 .cra_flags = CRYPTO_ALG_ASYNC |
771 CRYPTO_ALG_KERN_DRIVER_ONLY,
772 .cra_blocksize = 1,
773 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx),
774 .cra_alignmask = 0xf,
775 .cra_module = THIS_MODULE,
776 },
777 .init = omap_aes_gcm_cra_init,
778 .maxauthsize = AES_BLOCK_SIZE,
779 .ivsize = GCM_RFC4106_IV_SIZE,
780 .setkey = omap_aes_4106gcm_setkey,
781 .setauthsize = omap_aes_4106gcm_setauthsize,
782 .encrypt = omap_aes_4106gcm_encrypt,
783 .decrypt = omap_aes_4106gcm_decrypt,
784 },
785 };
786
787 static struct omap_aes_aead_algs omap_aes_aead_info = {
788 .algs_list = algs_aead_gcm,
789 .size = ARRAY_SIZE(algs_aead_gcm),
790 };
791
792 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
793 .algs_info = omap_aes_algs_info_ecb_cbc,
794 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
795 .trigger = omap_aes_dma_trigger_omap2,
796 .key_ofs = 0x1c,
797 .iv_ofs = 0x20,
798 .ctrl_ofs = 0x30,
799 .data_ofs = 0x34,
800 .rev_ofs = 0x44,
801 .mask_ofs = 0x48,
802 .dma_enable_in = BIT(2),
803 .dma_enable_out = BIT(3),
804 .dma_start = BIT(5),
805 .major_mask = 0xf0,
806 .major_shift = 4,
807 .minor_mask = 0x0f,
808 .minor_shift = 0,
809 };
810
811 #ifdef CONFIG_OF
812 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
813 {
814 .algs_list = algs_ecb_cbc,
815 .size = ARRAY_SIZE(algs_ecb_cbc),
816 },
817 {
818 .algs_list = algs_ctr,
819 .size = ARRAY_SIZE(algs_ctr),
820 },
821 };
822
823 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
824 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
825 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
826 .trigger = omap_aes_dma_trigger_omap2,
827 .key_ofs = 0x1c,
828 .iv_ofs = 0x20,
829 .ctrl_ofs = 0x30,
830 .data_ofs = 0x34,
831 .rev_ofs = 0x44,
832 .mask_ofs = 0x48,
833 .dma_enable_in = BIT(2),
834 .dma_enable_out = BIT(3),
835 .dma_start = BIT(5),
836 .major_mask = 0xf0,
837 .major_shift = 4,
838 .minor_mask = 0x0f,
839 .minor_shift = 0,
840 };
841
842 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
843 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
844 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
845 .aead_algs_info = &omap_aes_aead_info,
846 .trigger = omap_aes_dma_trigger_omap4,
847 .key_ofs = 0x3c,
848 .iv_ofs = 0x40,
849 .ctrl_ofs = 0x50,
850 .data_ofs = 0x60,
851 .rev_ofs = 0x80,
852 .mask_ofs = 0x84,
853 .irq_status_ofs = 0x8c,
854 .irq_enable_ofs = 0x90,
855 .dma_enable_in = BIT(5),
856 .dma_enable_out = BIT(6),
857 .major_mask = 0x0700,
858 .major_shift = 8,
859 .minor_mask = 0x003f,
860 .minor_shift = 0,
861 };
862
863 static irqreturn_t omap_aes_irq(int irq, void *dev_id)
864 {
865 struct omap_aes_dev *dd = dev_id;
866 u32 status, i;
867 u32 *src, *dst;
868
869 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
870 if (status & AES_REG_IRQ_DATA_IN) {
871 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
872
873 BUG_ON(!dd->in_sg);
874
875 BUG_ON(_calc_walked(in) > dd->in_sg->length);
876
877 src = sg_virt(dd->in_sg) + _calc_walked(in);
878
879 for (i = 0; i < AES_BLOCK_WORDS; i++) {
880 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
881
882 scatterwalk_advance(&dd->in_walk, 4);
883 if (dd->in_sg->length == _calc_walked(in)) {
884 dd->in_sg = sg_next(dd->in_sg);
885 if (dd->in_sg) {
886 scatterwalk_start(&dd->in_walk,
887 dd->in_sg);
888 src = sg_virt(dd->in_sg) +
889 _calc_walked(in);
890 }
891 } else {
892 src++;
893 }
894 }
895
896 /* Clear IRQ status */
897 status &= ~AES_REG_IRQ_DATA_IN;
898 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
899
900 /* Enable DATA_OUT interrupt */
901 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
902
903 } else if (status & AES_REG_IRQ_DATA_OUT) {
904 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
905
906 BUG_ON(!dd->out_sg);
907
908 BUG_ON(_calc_walked(out) > dd->out_sg->length);
909
910 dst = sg_virt(dd->out_sg) + _calc_walked(out);
911
912 for (i = 0; i < AES_BLOCK_WORDS; i++) {
913 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
914 scatterwalk_advance(&dd->out_walk, 4);
915 if (dd->out_sg->length == _calc_walked(out)) {
916 dd->out_sg = sg_next(dd->out_sg);
917 if (dd->out_sg) {
918 scatterwalk_start(&dd->out_walk,
919 dd->out_sg);
920 dst = sg_virt(dd->out_sg) +
921 _calc_walked(out);
922 }
923 } else {
924 dst++;
925 }
926 }
927
928 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
929
930 /* Clear IRQ status */
931 status &= ~AES_REG_IRQ_DATA_OUT;
932 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
933
934 if (!dd->total)
935 /* All bytes read! */
936 tasklet_schedule(&dd->done_task);
937 else
938 /* Enable DATA_IN interrupt for next block */
939 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
940 }
941
942 return IRQ_HANDLED;
943 }
944
945 static const struct of_device_id omap_aes_of_match[] = {
946 {
947 .compatible = "ti,omap2-aes",
948 .data = &omap_aes_pdata_omap2,
949 },
950 {
951 .compatible = "ti,omap3-aes",
952 .data = &omap_aes_pdata_omap3,
953 },
954 {
955 .compatible = "ti,omap4-aes",
956 .data = &omap_aes_pdata_omap4,
957 },
958 {},
959 };
960 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
961
962 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
963 struct device *dev, struct resource *res)
964 {
965 struct device_node *node = dev->of_node;
966 int err = 0;
967
968 dd->pdata = of_device_get_match_data(dev);
969 if (!dd->pdata) {
970 dev_err(dev, "no compatible OF match\n");
971 err = -EINVAL;
972 goto err;
973 }
974
975 err = of_address_to_resource(node, 0, res);
976 if (err < 0) {
977 dev_err(dev, "can't translate OF node address\n");
978 err = -EINVAL;
979 goto err;
980 }
981
982 err:
983 return err;
984 }
985 #else
986 static const struct of_device_id omap_aes_of_match[] = {
987 {},
988 };
989
990 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
991 struct device *dev, struct resource *res)
992 {
993 return -EINVAL;
994 }
995 #endif
996
997 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
998 struct platform_device *pdev, struct resource *res)
999 {
1000 struct device *dev = &pdev->dev;
1001 struct resource *r;
1002 int err = 0;
1003
1004 /* Get the base address */
1005 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1006 if (!r) {
1007 dev_err(dev, "no MEM resource info\n");
1008 err = -ENODEV;
1009 goto err;
1010 }
1011 memcpy(res, r, sizeof(*res));
1012
1013 /* Only OMAP2/3 can be non-DT */
1014 dd->pdata = &omap_aes_pdata_omap2;
1015
1016 err:
1017 return err;
1018 }
1019
1020 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
1021 char *buf)
1022 {
1023 return sprintf(buf, "%d\n", aes_fallback_sz);
1024 }
1025
1026 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
1027 const char *buf, size_t size)
1028 {
1029 ssize_t status;
1030 long value;
1031
1032 status = kstrtol(buf, 0, &value);
1033 if (status)
1034 return status;
1035
1036 /* HW accelerator only works with buffers > 9 */
1037 if (value < 9) {
1038 dev_err(dev, "minimum fallback size 9\n");
1039 return -EINVAL;
1040 }
1041
1042 aes_fallback_sz = value;
1043
1044 return size;
1045 }
1046
1047 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
1048 char *buf)
1049 {
1050 struct omap_aes_dev *dd = dev_get_drvdata(dev);
1051
1052 return sprintf(buf, "%d\n", dd->engine->queue.max_qlen);
1053 }
1054
1055 static ssize_t queue_len_store(struct device *dev,
1056 struct device_attribute *attr, const char *buf,
1057 size_t size)
1058 {
1059 struct omap_aes_dev *dd;
1060 ssize_t status;
1061 long value;
1062 unsigned long flags;
1063
1064 status = kstrtol(buf, 0, &value);
1065 if (status)
1066 return status;
1067
1068 if (value < 1)
1069 return -EINVAL;
1070
1071 /*
1072 * Changing the queue size in fly is safe, if size becomes smaller
1073 * than current size, it will just not accept new entries until
1074 * it has shrank enough.
1075 */
1076 spin_lock_bh(&list_lock);
1077 list_for_each_entry(dd, &dev_list, list) {
1078 spin_lock_irqsave(&dd->lock, flags);
1079 dd->engine->queue.max_qlen = value;
1080 dd->aead_queue.base.max_qlen = value;
1081 spin_unlock_irqrestore(&dd->lock, flags);
1082 }
1083 spin_unlock_bh(&list_lock);
1084
1085 return size;
1086 }
1087
1088 static DEVICE_ATTR_RW(queue_len);
1089 static DEVICE_ATTR_RW(fallback);
1090
1091 static struct attribute *omap_aes_attrs[] = {
1092 &dev_attr_queue_len.attr,
1093 &dev_attr_fallback.attr,
1094 NULL,
1095 };
1096
1097 static struct attribute_group omap_aes_attr_group = {
1098 .attrs = omap_aes_attrs,
1099 };
1100
1101 static int omap_aes_probe(struct platform_device *pdev)
1102 {
1103 struct device *dev = &pdev->dev;
1104 struct omap_aes_dev *dd;
1105 struct skcipher_alg *algp;
1106 struct aead_alg *aalg;
1107 struct resource res;
1108 int err = -ENOMEM, i, j, irq = -1;
1109 u32 reg;
1110
1111 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1112 if (dd == NULL) {
1113 dev_err(dev, "unable to alloc data struct.\n");
1114 goto err_data;
1115 }
1116 dd->dev = dev;
1117 platform_set_drvdata(pdev, dd);
1118
1119 aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH);
1120
1121 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1122 omap_aes_get_res_pdev(dd, pdev, &res);
1123 if (err)
1124 goto err_res;
1125
1126 dd->io_base = devm_ioremap_resource(dev, &res);
1127 if (IS_ERR(dd->io_base)) {
1128 err = PTR_ERR(dd->io_base);
1129 goto err_res;
1130 }
1131 dd->phys_base = res.start;
1132
1133 pm_runtime_use_autosuspend(dev);
1134 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1135
1136 pm_runtime_enable(dev);
1137 err = pm_runtime_get_sync(dev);
1138 if (err < 0) {
1139 dev_err(dev, "%s: failed to get_sync(%d)\n",
1140 __func__, err);
1141 goto err_res;
1142 }
1143
1144 omap_aes_dma_stop(dd);
1145
1146 reg = omap_aes_read(dd, AES_REG_REV(dd));
1147
1148 pm_runtime_put_sync(dev);
1149
1150 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1151 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1152 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1153
1154 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1155
1156 err = omap_aes_dma_init(dd);
1157 if (err == -EPROBE_DEFER) {
1158 goto err_irq;
1159 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1160 dd->pio_only = 1;
1161
1162 irq = platform_get_irq(pdev, 0);
1163 if (irq < 0) {
1164 err = irq;
1165 goto err_irq;
1166 }
1167
1168 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1169 dev_name(dev), dd);
1170 if (err) {
1171 dev_err(dev, "Unable to grab omap-aes IRQ\n");
1172 goto err_irq;
1173 }
1174 }
1175
1176 spin_lock_init(&dd->lock);
1177
1178 INIT_LIST_HEAD(&dd->list);
1179 spin_lock(&list_lock);
1180 list_add_tail(&dd->list, &dev_list);
1181 spin_unlock(&list_lock);
1182
1183 /* Initialize crypto engine */
1184 dd->engine = crypto_engine_alloc_init(dev, 1);
1185 if (!dd->engine) {
1186 err = -ENOMEM;
1187 goto err_engine;
1188 }
1189
1190 err = crypto_engine_start(dd->engine);
1191 if (err)
1192 goto err_engine;
1193
1194 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1195 if (!dd->pdata->algs_info[i].registered) {
1196 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1197 algp = &dd->pdata->algs_info[i].algs_list[j];
1198
1199 pr_debug("reg alg: %s\n", algp->base.cra_name);
1200
1201 err = crypto_register_skcipher(algp);
1202 if (err)
1203 goto err_algs;
1204
1205 dd->pdata->algs_info[i].registered++;
1206 }
1207 }
1208 }
1209
1210 if (dd->pdata->aead_algs_info &&
1211 !dd->pdata->aead_algs_info->registered) {
1212 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) {
1213 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1214
1215 pr_debug("reg alg: %s\n", aalg->base.cra_name);
1216
1217 err = crypto_register_aead(aalg);
1218 if (err)
1219 goto err_aead_algs;
1220
1221 dd->pdata->aead_algs_info->registered++;
1222 }
1223 }
1224
1225 err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group);
1226 if (err) {
1227 dev_err(dev, "could not create sysfs device attrs\n");
1228 goto err_aead_algs;
1229 }
1230
1231 return 0;
1232 err_aead_algs:
1233 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
1234 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1235 crypto_unregister_aead(aalg);
1236 }
1237 err_algs:
1238 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1239 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1240 crypto_unregister_skcipher(
1241 &dd->pdata->algs_info[i].algs_list[j]);
1242
1243 err_engine:
1244 if (dd->engine)
1245 crypto_engine_exit(dd->engine);
1246
1247 omap_aes_dma_cleanup(dd);
1248 err_irq:
1249 tasklet_kill(&dd->done_task);
1250 pm_runtime_disable(dev);
1251 err_res:
1252 dd = NULL;
1253 err_data:
1254 dev_err(dev, "initialization failed.\n");
1255 return err;
1256 }
1257
1258 static int omap_aes_remove(struct platform_device *pdev)
1259 {
1260 struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1261 struct aead_alg *aalg;
1262 int i, j;
1263
1264 if (!dd)
1265 return -ENODEV;
1266
1267 spin_lock(&list_lock);
1268 list_del(&dd->list);
1269 spin_unlock(&list_lock);
1270
1271 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1272 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1273 crypto_unregister_skcipher(
1274 &dd->pdata->algs_info[i].algs_list[j]);
1275
1276 for (i = dd->pdata->aead_algs_info->size - 1; i >= 0; i--) {
1277 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1278 crypto_unregister_aead(aalg);
1279 }
1280
1281 crypto_engine_exit(dd->engine);
1282
1283 tasklet_kill(&dd->done_task);
1284 omap_aes_dma_cleanup(dd);
1285 pm_runtime_disable(dd->dev);
1286
1287 sysfs_remove_group(&dd->dev->kobj, &omap_aes_attr_group);
1288
1289 return 0;
1290 }
1291
1292 #ifdef CONFIG_PM_SLEEP
1293 static int omap_aes_suspend(struct device *dev)
1294 {
1295 pm_runtime_put_sync(dev);
1296 return 0;
1297 }
1298
1299 static int omap_aes_resume(struct device *dev)
1300 {
1301 pm_runtime_get_sync(dev);
1302 return 0;
1303 }
1304 #endif
1305
1306 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1307
1308 static struct platform_driver omap_aes_driver = {
1309 .probe = omap_aes_probe,
1310 .remove = omap_aes_remove,
1311 .driver = {
1312 .name = "omap-aes",
1313 .pm = &omap_aes_pm_ops,
1314 .of_match_table = omap_aes_of_match,
1315 },
1316 };
1317
1318 module_platform_driver(omap_aes_driver);
1319
1320 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1321 MODULE_LICENSE("GPL v2");
1322 MODULE_AUTHOR("Dmitry Kasatkin");
1323
Linux with added FPC-III support