drivers/dma/hsu/hsu.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Driver for the High Speed UART DMA
   4  *
   5  * Copyright (C) 2015 Intel Corporation
   6  *
   7  * Partially based on the bits found in drivers/tty/serial/mfd.c.
   8  */
   9
  10 #ifndef __DMA_HSU_H__
  11 #define __DMA_HSU_H__
  12
  13 #include <linux/spinlock.h>
  14 #include <linux/dma/hsu.h>
  15
  16 #include "../virt-dma.h"
  17
  18 #define HSU_CH_SR               0x00                    /* channel status */
  19 #define HSU_CH_CR               0x04                    /* channel control */
  20 #define HSU_CH_DCR              0x08                    /* descriptor control */
  21 #define HSU_CH_BSR              0x10                    /* FIFO buffer size */
  22 #define HSU_CH_MTSR             0x14                    /* minimum transfer size */
  23 #define HSU_CH_DxSAR(x)         (0x20 + 8 * (x))        /* desc start addr */
  24 #define HSU_CH_DxTSR(x)         (0x24 + 8 * (x))        /* desc transfer size */
  25 #define HSU_CH_D0SAR            0x20                    /* desc 0 start addr */
  26 #define HSU_CH_D0TSR            0x24                    /* desc 0 transfer size */
  27 #define HSU_CH_D1SAR            0x28
  28 #define HSU_CH_D1TSR            0x2c
  29 #define HSU_CH_D2SAR            0x30
  30 #define HSU_CH_D2TSR            0x34
  31 #define HSU_CH_D3SAR            0x38
  32 #define HSU_CH_D3TSR            0x3c
  33
  34 #define HSU_DMA_CHAN_NR_DESC    4
  35 #define HSU_DMA_CHAN_LENGTH     0x40
  36
  37 /* Bits in HSU_CH_SR */
  38 #define HSU_CH_SR_DESCTO(x)     BIT(8 + (x))
  39 #define HSU_CH_SR_DESCTO_ANY    (BIT(11) | BIT(10) | BIT(9) | BIT(8))
  40 #define HSU_CH_SR_CHE           BIT(15)
  41 #define HSU_CH_SR_DESCE(x)      BIT(16 + (x))
  42 #define HSU_CH_SR_DESCE_ANY     (BIT(19) | BIT(18) | BIT(17) | BIT(16))
  43 #define HSU_CH_SR_CDESC_ANY     (BIT(31) | BIT(30))
  44
  45 /* Bits in HSU_CH_CR */
  46 #define HSU_CH_CR_CHA           BIT(0)
  47 #define HSU_CH_CR_CHD           BIT(1)
  48
  49 /* Bits in HSU_CH_DCR */
  50 #define HSU_CH_DCR_DESCA(x)     BIT(0 + (x))
  51 #define HSU_CH_DCR_CHSOD(x)     BIT(8 + (x))
  52 #define HSU_CH_DCR_CHSOTO       BIT(14)
  53 #define HSU_CH_DCR_CHSOE        BIT(15)
  54 #define HSU_CH_DCR_CHDI(x)      BIT(16 + (x))
  55 #define HSU_CH_DCR_CHEI         BIT(23)
  56 #define HSU_CH_DCR_CHTOI(x)     BIT(24 + (x))
  57
  58 /* Bits in HSU_CH_DxTSR */
  59 #define HSU_CH_DxTSR_MASK       GENMASK(15, 0)
  60 #define HSU_CH_DxTSR_TSR(x)     ((x) & HSU_CH_DxTSR_MASK)
  61
  62 struct hsu_dma_sg {
  63         dma_addr_t addr;
  64         unsigned int len;
  65 };
  66
  67 struct hsu_dma_desc {
  68         struct virt_dma_desc vdesc;
  69         enum dma_transfer_direction direction;
  70         struct hsu_dma_sg *sg;
  71         unsigned int nents;
  72         size_t length;
  73         unsigned int active;
  74         enum dma_status status;
  75 };
  76
  77 static inline struct hsu_dma_desc *to_hsu_dma_desc(struct virt_dma_desc *vdesc)
  78 {
  79         return container_of(vdesc, struct hsu_dma_desc, vdesc);
  80 }
  81
  82 struct hsu_dma_chan {
  83         struct virt_dma_chan vchan;
  84
  85         void __iomem *reg;
  86
  87         /* hardware configuration */
  88         enum dma_transfer_direction direction;
  89         struct dma_slave_config config;
  90
  91         struct hsu_dma_desc *desc;
  92 };
  93
  94 static inline struct hsu_dma_chan *to_hsu_dma_chan(struct dma_chan *chan)
  95 {
  96         return container_of(chan, struct hsu_dma_chan, vchan.chan);
  97 }
  98
  99 static inline u32 hsu_chan_readl(struct hsu_dma_chan *hsuc, int offset)
 100 {
 101         return readl(hsuc->reg + offset);
 102 }
 103
 104 static inline void hsu_chan_writel(struct hsu_dma_chan *hsuc, int offset,
 105                                    u32 value)
 106 {
 107         writel(value, hsuc->reg + offset);
 108 }
 109
 110 struct hsu_dma {
 111         struct dma_device               dma;
 112
 113         /* channels */
 114         struct hsu_dma_chan             *chan;
 115         unsigned short                  nr_channels;
 116 };
 117
 118 static inline struct hsu_dma *to_hsu_dma(struct dma_device *ddev)
 119 {
 120         return container_of(ddev, struct hsu_dma, dma);
 121 }
 122
 123 #endif /* __DMA_HSU_H__ */