drivers/dma/ti/k3-udma.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  *  Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
   4  */
   5
   6 #ifndef K3_UDMA_H_
   7 #define K3_UDMA_H_
   8
   9 #include <linux/soc/ti/ti_sci_protocol.h>
  10
  11 /* Global registers */
  12 #define UDMA_REV_REG                    0x0
  13 #define UDMA_PERF_CTL_REG               0x4
  14 #define UDMA_EMU_CTL_REG                0x8
  15 #define UDMA_PSIL_TO_REG                0x10
  16 #define UDMA_UTC_CTL_REG                0x1c
  17 #define UDMA_CAP_REG(i)                 (0x20 + ((i) * 4))
  18 #define UDMA_RX_FLOW_ID_FW_OES_REG      0x80
  19 #define UDMA_RX_FLOW_ID_FW_STATUS_REG   0x88
  20
  21 /* TX chan RT regs */
  22 #define UDMA_TCHAN_RT_CTL_REG           0x0
  23 #define UDMA_TCHAN_RT_SWTRIG_REG        0x8
  24 #define UDMA_TCHAN_RT_STDATA_REG        0x80
  25
  26 #define UDMA_TCHAN_RT_PEER_REG(i)       (0x200 + ((i) * 0x4))
  27 #define UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG     \
  28         UDMA_TCHAN_RT_PEER_REG(0)       /* PSI-L: 0x400 */
  29 #define UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG      \
  30         UDMA_TCHAN_RT_PEER_REG(1)       /* PSI-L: 0x401 */
  31 #define UDMA_TCHAN_RT_PEER_BCNT_REG             \
  32         UDMA_TCHAN_RT_PEER_REG(4)       /* PSI-L: 0x404 */
  33 #define UDMA_TCHAN_RT_PEER_RT_EN_REG            \
  34         UDMA_TCHAN_RT_PEER_REG(8)       /* PSI-L: 0x408 */
  35
  36 #define UDMA_TCHAN_RT_PCNT_REG          0x400
  37 #define UDMA_TCHAN_RT_BCNT_REG          0x408
  38 #define UDMA_TCHAN_RT_SBCNT_REG         0x410
  39
  40 /* RX chan RT regs */
  41 #define UDMA_RCHAN_RT_CTL_REG           0x0
  42 #define UDMA_RCHAN_RT_SWTRIG_REG        0x8
  43 #define UDMA_RCHAN_RT_STDATA_REG        0x80
  44
  45 #define UDMA_RCHAN_RT_PEER_REG(i)       (0x200 + ((i) * 0x4))
  46 #define UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG     \
  47         UDMA_RCHAN_RT_PEER_REG(0)       /* PSI-L: 0x400 */
  48 #define UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG      \
  49         UDMA_RCHAN_RT_PEER_REG(1)       /* PSI-L: 0x401 */
  50 #define UDMA_RCHAN_RT_PEER_BCNT_REG             \
  51         UDMA_RCHAN_RT_PEER_REG(4)       /* PSI-L: 0x404 */
  52 #define UDMA_RCHAN_RT_PEER_RT_EN_REG            \
  53         UDMA_RCHAN_RT_PEER_REG(8)       /* PSI-L: 0x408 */
  54
  55 #define UDMA_RCHAN_RT_PCNT_REG          0x400
  56 #define UDMA_RCHAN_RT_BCNT_REG          0x408
  57 #define UDMA_RCHAN_RT_SBCNT_REG         0x410
  58
  59 /* UDMA_TCHAN_RT_CTL_REG/UDMA_RCHAN_RT_CTL_REG */
  60 #define UDMA_CHAN_RT_CTL_EN             BIT(31)
  61 #define UDMA_CHAN_RT_CTL_TDOWN          BIT(30)
  62 #define UDMA_CHAN_RT_CTL_PAUSE          BIT(29)
  63 #define UDMA_CHAN_RT_CTL_FTDOWN         BIT(28)
  64 #define UDMA_CHAN_RT_CTL_ERROR          BIT(0)
  65
  66 /* UDMA_TCHAN_RT_PEER_RT_EN_REG/UDMA_RCHAN_RT_PEER_RT_EN_REG (PSI-L: 0x408) */
  67 #define UDMA_PEER_RT_EN_ENABLE          BIT(31)
  68 #define UDMA_PEER_RT_EN_TEARDOWN        BIT(30)
  69 #define UDMA_PEER_RT_EN_PAUSE           BIT(29)
  70 #define UDMA_PEER_RT_EN_FLUSH           BIT(28)
  71 #define UDMA_PEER_RT_EN_IDLE            BIT(1)
  72
  73 /*
  74  * UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG /
  75  * UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG
  76  */
  77 #define PDMA_STATIC_TR_X_MASK           GENMASK(26, 24)
  78 #define PDMA_STATIC_TR_X_SHIFT          (24)
  79 #define PDMA_STATIC_TR_Y_MASK           GENMASK(11, 0)
  80 #define PDMA_STATIC_TR_Y_SHIFT          (0)
  81
  82 #define PDMA_STATIC_TR_Y(x)     \
  83         (((x) << PDMA_STATIC_TR_Y_SHIFT) & PDMA_STATIC_TR_Y_MASK)
  84 #define PDMA_STATIC_TR_X(x)     \
  85         (((x) << PDMA_STATIC_TR_X_SHIFT) & PDMA_STATIC_TR_X_MASK)
  86
  87 #define PDMA_STATIC_TR_XY_ACC32         BIT(30)
  88 #define PDMA_STATIC_TR_XY_BURST         BIT(31)
  89
  90 /*
  91  * UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG /
  92  * UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG
  93  */
  94 #define PDMA_STATIC_TR_Z(x, mask)       ((x) & (mask))
  95
  96 struct udma_dev;
  97 struct udma_tchan;
  98 struct udma_rchan;
  99 struct udma_rflow;
 100
 101 enum udma_rm_range {
 102         RM_RANGE_TCHAN = 0,
 103         RM_RANGE_RCHAN,
 104         RM_RANGE_RFLOW,
 105         RM_RANGE_LAST,
 106 };
 107
 108 struct udma_tisci_rm {
 109         const struct ti_sci_handle *tisci;
 110         const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
 111         u32  tisci_dev_id;
 112
 113         /* tisci information for PSI-L thread pairing/unpairing */
 114         const struct ti_sci_rm_psil_ops *tisci_psil_ops;
 115         u32  tisci_navss_dev_id;
 116
 117         struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
 118 };
 119
 120 /* Direct access to UDMA low lever resources for the glue layer */
 121 int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread);
 122 int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
 123                             u32 dst_thread);
 124
 125 struct udma_dev *of_xudma_dev_get(struct device_node *np, const char *property);
 126 void xudma_dev_put(struct udma_dev *ud);
 127 u32 xudma_dev_get_psil_base(struct udma_dev *ud);
 128 struct udma_tisci_rm *xudma_dev_get_tisci_rm(struct udma_dev *ud);
 129
 130 int xudma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt);
 131 int xudma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt);
 132
 133 struct udma_tchan *xudma_tchan_get(struct udma_dev *ud, int id);
 134 struct udma_rchan *xudma_rchan_get(struct udma_dev *ud, int id);
 135 struct udma_rflow *xudma_rflow_get(struct udma_dev *ud, int id);
 136
 137 void xudma_tchan_put(struct udma_dev *ud, struct udma_tchan *p);
 138 void xudma_rchan_put(struct udma_dev *ud, struct udma_rchan *p);
 139 void xudma_rflow_put(struct udma_dev *ud, struct udma_rflow *p);
 140
 141 int xudma_tchan_get_id(struct udma_tchan *p);
 142 int xudma_rchan_get_id(struct udma_rchan *p);
 143 int xudma_rflow_get_id(struct udma_rflow *p);
 144
 145 u32 xudma_tchanrt_read(struct udma_tchan *tchan, int reg);
 146 void xudma_tchanrt_write(struct udma_tchan *tchan, int reg, u32 val);
 147 u32 xudma_rchanrt_read(struct udma_rchan *rchan, int reg);
 148 void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val);
 149 bool xudma_rflow_is_gp(struct udma_dev *ud, int id);
 150
 151 #endif /* K3_UDMA_H_ */