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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / edac / skx_base.c
blob83545b4facb7693696d49ecafd8ccbf39cd67d42
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * EDAC driver for Intel(R) Xeon(R) Skylake processors
4 * Copyright (c) 2016, Intel Corporation.
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/processor.h>
9 #include <asm/cpu_device_id.h>
10 #include <asm/intel-family.h>
11 #include <asm/mce.h>
12
13 #include "edac_module.h"
14 #include "skx_common.h"
15
16 #define EDAC_MOD_STR "skx_edac"
17
18 /*
19 * Debug macros
20 */
21 #define skx_printk(level, fmt, arg...) \
22 edac_printk(level, "skx", fmt, ##arg)
23
24 #define skx_mc_printk(mci, level, fmt, arg...) \
25 edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
26
27 static struct list_head *skx_edac_list;
28
29 static u64 skx_tolm, skx_tohm;
30 static int skx_num_sockets;
31 static unsigned int nvdimm_count;
32
33 #define MASK26 0x3FFFFFF /* Mask for 2^26 */
34 #define MASK29 0x1FFFFFFF /* Mask for 2^29 */
35
36 static struct skx_dev *get_skx_dev(struct pci_bus *bus, u8 idx)
37 {
38 struct skx_dev *d;
39
40 list_for_each_entry(d, skx_edac_list, list) {
41 if (d->seg == pci_domain_nr(bus) && d->bus[idx] == bus->number)
42 return d;
43 }
44
45 return NULL;
46 }
47
48 enum munittype {
49 CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD,
50 ERRCHAN0, ERRCHAN1, ERRCHAN2,
51 };
52
53 struct munit {
54 u16 did;
55 u16 devfn[SKX_NUM_IMC];
56 u8 busidx;
57 u8 per_socket;
58 enum munittype mtype;
59 };
60
61 /*
62 * List of PCI device ids that we need together with some device
63 * number and function numbers to tell which memory controller the
64 * device belongs to.
65 */
66 static const struct munit skx_all_munits[] = {
67 { 0x2054, { }, 1, 1, SAD_ALL },
68 { 0x2055, { }, 1, 1, UTIL_ALL },
69 { 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 },
70 { 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 },
71 { 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 },
72 { 0x2043, { PCI_DEVFN(10, 3), PCI_DEVFN(12, 3) }, 2, 2, ERRCHAN0 },
73 { 0x2047, { PCI_DEVFN(10, 7), PCI_DEVFN(12, 7) }, 2, 2, ERRCHAN1 },
74 { 0x204b, { PCI_DEVFN(11, 3), PCI_DEVFN(13, 3) }, 2, 2, ERRCHAN2 },
75 { 0x208e, { }, 1, 0, SAD },
76 { }
77 };
78
79 static int get_all_munits(const struct munit *m)
80 {
81 struct pci_dev *pdev, *prev;
82 struct skx_dev *d;
83 u32 reg;
84 int i = 0, ndev = 0;
85
86 prev = NULL;
87 for (;;) {
88 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, m->did, prev);
89 if (!pdev)
90 break;
91 ndev++;
92 if (m->per_socket == SKX_NUM_IMC) {
93 for (i = 0; i < SKX_NUM_IMC; i++)
94 if (m->devfn[i] == pdev->devfn)
95 break;
96 if (i == SKX_NUM_IMC)
97 goto fail;
98 }
99 d = get_skx_dev(pdev->bus, m->busidx);
100 if (!d)
101 goto fail;
102
103 /* Be sure that the device is enabled */
104 if (unlikely(pci_enable_device(pdev) < 0)) {
105 skx_printk(KERN_ERR, "Couldn't enable device %04x:%04x\n",
106 PCI_VENDOR_ID_INTEL, m->did);
107 goto fail;
108 }
109
110 switch (m->mtype) {
111 case CHAN0:
112 case CHAN1:
113 case CHAN2:
114 pci_dev_get(pdev);
115 d->imc[i].chan[m->mtype].cdev = pdev;
116 break;
117 case ERRCHAN0:
118 case ERRCHAN1:
119 case ERRCHAN2:
120 pci_dev_get(pdev);
121 d->imc[i].chan[m->mtype - ERRCHAN0].edev = pdev;
122 break;
123 case SAD_ALL:
124 pci_dev_get(pdev);
125 d->sad_all = pdev;
126 break;
127 case UTIL_ALL:
128 pci_dev_get(pdev);
129 d->util_all = pdev;
130 break;
131 case SAD:
132 /*
133 * one of these devices per core, including cores
134 * that don't exist on this SKU. Ignore any that
135 * read a route table of zero, make sure all the
136 * non-zero values match.
137 */
138 pci_read_config_dword(pdev, 0xB4, &reg);
139 if (reg != 0) {
140 if (d->mcroute == 0) {
141 d->mcroute = reg;
142 } else if (d->mcroute != reg) {
143 skx_printk(KERN_ERR, "mcroute mismatch\n");
144 goto fail;
145 }
146 }
147 ndev--;
148 break;
149 }
150
151 prev = pdev;
152 }
153
154 return ndev;
155 fail:
156 pci_dev_put(pdev);
157 return -ENODEV;
158 }
159
160 static const struct x86_cpu_id skx_cpuids[] = {
161 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X, 0, 0 },
162 { }
163 };
164 MODULE_DEVICE_TABLE(x86cpu, skx_cpuids);
165
166 #define SKX_GET_MTMTR(dev, reg) \
167 pci_read_config_dword((dev), 0x87c, &(reg))
168
169 static bool skx_check_ecc(struct pci_dev *pdev)
170 {
171 u32 mtmtr;
172
173 SKX_GET_MTMTR(pdev, mtmtr);
174
175 return !!GET_BITFIELD(mtmtr, 2, 2);
176 }
177
178 static int skx_get_dimm_config(struct mem_ctl_info *mci)
179 {
180 struct skx_pvt *pvt = mci->pvt_info;
181 struct skx_imc *imc = pvt->imc;
182 u32 mtr, amap, mcddrtcfg;
183 struct dimm_info *dimm;
184 int i, j;
185 int ndimms;
186
187 for (i = 0; i < SKX_NUM_CHANNELS; i++) {
188 ndimms = 0;
189 pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap);
190 pci_read_config_dword(imc->chan[i].cdev, 0x400, &mcddrtcfg);
191 for (j = 0; j < SKX_NUM_DIMMS; j++) {
192 dimm = edac_get_dimm(mci, i, j, 0);
193 pci_read_config_dword(imc->chan[i].cdev,
194 0x80 + 4 * j, &mtr);
195 if (IS_DIMM_PRESENT(mtr)) {
196 ndimms += skx_get_dimm_info(mtr, amap, dimm, imc, i, j);
197 } else if (IS_NVDIMM_PRESENT(mcddrtcfg, j)) {
198 ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
199 EDAC_MOD_STR);
200 nvdimm_count++;
201 }
202 }
203 if (ndimms && !skx_check_ecc(imc->chan[0].cdev)) {
204 skx_printk(KERN_ERR, "ECC is disabled on imc %d\n", imc->mc);
205 return -ENODEV;
206 }
207 }
208
209 return 0;
210 }
211
212 #define SKX_MAX_SAD 24
213
214 #define SKX_GET_SAD(d, i, reg) \
215 pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &(reg))
216 #define SKX_GET_ILV(d, i, reg) \
217 pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &(reg))
218
219 #define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31)
220 #define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27)
221 #define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26)
222 #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6)
223 #define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4)
224 #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2)
225 #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0)
226
227 #define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0)
228 #define SKX_ILV_TARGET(tgt) ((tgt) & 7)
229
230 static void skx_show_retry_rd_err_log(struct decoded_addr *res,
231 char *msg, int len)
232 {
233 u32 log0, log1, log2, log3, log4;
234 u32 corr0, corr1, corr2, corr3;
235 struct pci_dev *edev;
236 int n;
237
238 edev = res->dev->imc[res->imc].chan[res->channel].edev;
239
240 pci_read_config_dword(edev, 0x154, &log0);
241 pci_read_config_dword(edev, 0x148, &log1);
242 pci_read_config_dword(edev, 0x150, &log2);
243 pci_read_config_dword(edev, 0x15c, &log3);
244 pci_read_config_dword(edev, 0x114, &log4);
245
246 n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x]",
247 log0, log1, log2, log3, log4);
248
249 pci_read_config_dword(edev, 0x104, &corr0);
250 pci_read_config_dword(edev, 0x108, &corr1);
251 pci_read_config_dword(edev, 0x10c, &corr2);
252 pci_read_config_dword(edev, 0x110, &corr3);
253
254 if (len - n > 0)
255 snprintf(msg + n, len - n,
256 " correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]",
257 corr0 & 0xffff, corr0 >> 16,
258 corr1 & 0xffff, corr1 >> 16,
259 corr2 & 0xffff, corr2 >> 16,
260 corr3 & 0xffff, corr3 >> 16);
261 }
262
263 static bool skx_sad_decode(struct decoded_addr *res)
264 {
265 struct skx_dev *d = list_first_entry(skx_edac_list, typeof(*d), list);
266 u64 addr = res->addr;
267 int i, idx, tgt, lchan, shift;
268 u32 sad, ilv;
269 u64 limit, prev_limit;
270 int remote = 0;
271
272 /* Simple sanity check for I/O space or out of range */
273 if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) {
274 edac_dbg(0, "Address 0x%llx out of range\n", addr);
275 return false;
276 }
277
278 restart:
279 prev_limit = 0;
280 for (i = 0; i < SKX_MAX_SAD; i++) {
281 SKX_GET_SAD(d, i, sad);
282 limit = SKX_SAD_LIMIT(sad);
283 if (SKX_SAD_ENABLE(sad)) {
284 if (addr >= prev_limit && addr <= limit)
285 goto sad_found;
286 }
287 prev_limit = limit + 1;
288 }
289 edac_dbg(0, "No SAD entry for 0x%llx\n", addr);
290 return false;
291
292 sad_found:
293 SKX_GET_ILV(d, i, ilv);
294
295 switch (SKX_SAD_INTERLEAVE(sad)) {
296 case 0:
297 idx = GET_BITFIELD(addr, 6, 8);
298 break;
299 case 1:
300 idx = GET_BITFIELD(addr, 8, 10);
301 break;
302 case 2:
303 idx = GET_BITFIELD(addr, 12, 14);
304 break;
305 case 3:
306 idx = GET_BITFIELD(addr, 30, 32);
307 break;
308 }
309
310 tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3);
311
312 /* If point to another node, find it and start over */
313 if (SKX_ILV_REMOTE(tgt)) {
314 if (remote) {
315 edac_dbg(0, "Double remote!\n");
316 return false;
317 }
318 remote = 1;
319 list_for_each_entry(d, skx_edac_list, list) {
320 if (d->imc[0].src_id == SKX_ILV_TARGET(tgt))
321 goto restart;
322 }
323 edac_dbg(0, "Can't find node %d\n", SKX_ILV_TARGET(tgt));
324 return false;
325 }
326
327 if (SKX_SAD_MOD3(sad) == 0) {
328 lchan = SKX_ILV_TARGET(tgt);
329 } else {
330 switch (SKX_SAD_MOD3MODE(sad)) {
331 case 0:
332 shift = 6;
333 break;
334 case 1:
335 shift = 8;
336 break;
337 case 2:
338 shift = 12;
339 break;
340 default:
341 edac_dbg(0, "illegal mod3mode\n");
342 return false;
343 }
344 switch (SKX_SAD_MOD3ASMOD2(sad)) {
345 case 0:
346 lchan = (addr >> shift) % 3;
347 break;
348 case 1:
349 lchan = (addr >> shift) % 2;
350 break;
351 case 2:
352 lchan = (addr >> shift) % 2;
353 lchan = (lchan << 1) | !lchan;
354 break;
355 case 3:
356 lchan = ((addr >> shift) % 2) << 1;
357 break;
358 }
359 lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1);
360 }
361
362 res->dev = d;
363 res->socket = d->imc[0].src_id;
364 res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2);
365 res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19);
366
367 edac_dbg(2, "0x%llx: socket=%d imc=%d channel=%d\n",
368 res->addr, res->socket, res->imc, res->channel);
369 return true;
370 }
371
372 #define SKX_MAX_TAD 8
373
374 #define SKX_GET_TADBASE(d, mc, i, reg) \
375 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &(reg))
376 #define SKX_GET_TADWAYNESS(d, mc, i, reg) \
377 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &(reg))
378 #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \
379 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &(reg))
380
381 #define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26)
382 #define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5)
383 #define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7)
384 #define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26)
385 #define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26)
386 #define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11))
387 #define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1)
388
389 /* which bit used for both socket and channel interleave */
390 static int skx_granularity[] = { 6, 8, 12, 30 };
391
392 static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits)
393 {
394 addr >>= shift;
395 addr /= ways;
396 addr <<= shift;
397
398 return addr | (lowbits & ((1ull << shift) - 1));
399 }
400
401 static bool skx_tad_decode(struct decoded_addr *res)
402 {
403 int i;
404 u32 base, wayness, chnilvoffset;
405 int skt_interleave_bit, chn_interleave_bit;
406 u64 channel_addr;
407
408 for (i = 0; i < SKX_MAX_TAD; i++) {
409 SKX_GET_TADBASE(res->dev, res->imc, i, base);
410 SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness);
411 if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness))
412 goto tad_found;
413 }
414 edac_dbg(0, "No TAD entry for 0x%llx\n", res->addr);
415 return false;
416
417 tad_found:
418 res->sktways = SKX_TAD_SKTWAYS(wayness);
419 res->chanways = SKX_TAD_CHNWAYS(wayness);
420 skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)];
421 chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)];
422
423 SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset);
424 channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset);
425
426 if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) {
427 /* Must handle channel first, then socket */
428 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
429 res->chanways, channel_addr);
430 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
431 res->sktways, channel_addr);
432 } else {
433 /* Handle socket then channel. Preserve low bits from original address */
434 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
435 res->sktways, res->addr);
436 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
437 res->chanways, res->addr);
438 }
439
440 res->chan_addr = channel_addr;
441
442 edac_dbg(2, "0x%llx: chan_addr=0x%llx sktways=%d chanways=%d\n",
443 res->addr, res->chan_addr, res->sktways, res->chanways);
444 return true;
445 }
446
447 #define SKX_MAX_RIR 4
448
449 #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \
450 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
451 0x108 + 4 * (i), &(reg))
452 #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \
453 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
454 0x120 + 16 * (idx) + 4 * (i), &(reg))
455
456 #define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31)
457 #define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29)
458 #define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29))
459 #define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19)
460 #define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26))
461
462 static bool skx_rir_decode(struct decoded_addr *res)
463 {
464 int i, idx, chan_rank;
465 int shift;
466 u32 rirway, rirlv;
467 u64 rank_addr, prev_limit = 0, limit;
468
469 if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg)
470 shift = 6;
471 else
472 shift = 13;
473
474 for (i = 0; i < SKX_MAX_RIR; i++) {
475 SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway);
476 limit = SKX_RIR_LIMIT(rirway);
477 if (SKX_RIR_VALID(rirway)) {
478 if (prev_limit <= res->chan_addr &&
479 res->chan_addr <= limit)
480 goto rir_found;
481 }
482 prev_limit = limit;
483 }
484 edac_dbg(0, "No RIR entry for 0x%llx\n", res->addr);
485 return false;
486
487 rir_found:
488 rank_addr = res->chan_addr >> shift;
489 rank_addr /= SKX_RIR_WAYS(rirway);
490 rank_addr <<= shift;
491 rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0);
492
493 res->rank_address = rank_addr;
494 idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway);
495
496 SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv);
497 res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv);
498 chan_rank = SKX_RIR_CHAN_RANK(rirlv);
499 res->channel_rank = chan_rank;
500 res->dimm = chan_rank / 4;
501 res->rank = chan_rank % 4;
502
503 edac_dbg(2, "0x%llx: dimm=%d rank=%d chan_rank=%d rank_addr=0x%llx\n",
504 res->addr, res->dimm, res->rank,
505 res->channel_rank, res->rank_address);
506 return true;
507 }
508
509 static u8 skx_close_row[] = {
510 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33
511 };
512
513 static u8 skx_close_column[] = {
514 3, 4, 5, 14, 19, 23, 24, 25, 26, 27
515 };
516
517 static u8 skx_open_row[] = {
518 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33
519 };
520
521 static u8 skx_open_column[] = {
522 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
523 };
524
525 static u8 skx_open_fine_column[] = {
526 3, 4, 5, 7, 8, 9, 10, 11, 12, 13
527 };
528
529 static int skx_bits(u64 addr, int nbits, u8 *bits)
530 {
531 int i, res = 0;
532
533 for (i = 0; i < nbits; i++)
534 res |= ((addr >> bits[i]) & 1) << i;
535 return res;
536 }
537
538 static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1)
539 {
540 int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1);
541
542 if (do_xor)
543 ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1);
544
545 return ret;
546 }
547
548 static bool skx_mad_decode(struct decoded_addr *r)
549 {
550 struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm];
551 int bg0 = dimm->fine_grain_bank ? 6 : 13;
552
553 if (dimm->close_pg) {
554 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_close_row);
555 r->column = skx_bits(r->rank_address, dimm->colbits, skx_close_column);
556 r->column |= 0x400; /* C10 is autoprecharge, always set */
557 r->bank_address = skx_bank_bits(r->rank_address, 8, 9, dimm->bank_xor_enable, 22, 28);
558 r->bank_group = skx_bank_bits(r->rank_address, 6, 7, dimm->bank_xor_enable, 20, 21);
559 } else {
560 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_open_row);
561 if (dimm->fine_grain_bank)
562 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_fine_column);
563 else
564 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_column);
565 r->bank_address = skx_bank_bits(r->rank_address, 18, 19, dimm->bank_xor_enable, 22, 23);
566 r->bank_group = skx_bank_bits(r->rank_address, bg0, 17, dimm->bank_xor_enable, 20, 21);
567 }
568 r->row &= (1u << dimm->rowbits) - 1;
569
570 edac_dbg(2, "0x%llx: row=0x%x col=0x%x bank_addr=%d bank_group=%d\n",
571 r->addr, r->row, r->column, r->bank_address,
572 r->bank_group);
573 return true;
574 }
575
576 static bool skx_decode(struct decoded_addr *res)
577 {
578 return skx_sad_decode(res) && skx_tad_decode(res) &&
579 skx_rir_decode(res) && skx_mad_decode(res);
580 }
581
582 static struct notifier_block skx_mce_dec = {
583 .notifier_call = skx_mce_check_error,
584 .priority = MCE_PRIO_EDAC,
585 };
586
587 #ifdef CONFIG_EDAC_DEBUG
588 /*
589 * Debug feature.
590 * Exercise the address decode logic by writing an address to
591 * /sys/kernel/debug/edac/skx_test/addr.
592 */
593 static struct dentry *skx_test;
594
595 static int debugfs_u64_set(void *data, u64 val)
596 {
597 struct mce m;
598
599 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
600
601 memset(&m, 0, sizeof(m));
602 /* ADDRV + MemRd + Unknown channel */
603 m.status = MCI_STATUS_ADDRV + 0x90;
604 /* One corrected error */
605 m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
606 m.addr = val;
607 skx_mce_check_error(NULL, 0, &m);
608
609 return 0;
610 }
611 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
612
613 static void setup_skx_debug(void)
614 {
615 skx_test = edac_debugfs_create_dir("skx_test");
616 if (!skx_test)
617 return;
618
619 if (!edac_debugfs_create_file("addr", 0200, skx_test,
620 NULL, &fops_u64_wo)) {
621 debugfs_remove(skx_test);
622 skx_test = NULL;
623 }
624 }
625
626 static void teardown_skx_debug(void)
627 {
628 debugfs_remove_recursive(skx_test);
629 }
630 #else
631 static inline void setup_skx_debug(void) {}
632 static inline void teardown_skx_debug(void) {}
633 #endif /*CONFIG_EDAC_DEBUG*/
634
635 /*
636 * skx_init:
637 * make sure we are running on the correct cpu model
638 * search for all the devices we need
639 * check which DIMMs are present.
640 */
641 static int __init skx_init(void)
642 {
643 const struct x86_cpu_id *id;
644 const struct munit *m;
645 const char *owner;
646 int rc = 0, i, off[3] = {0xd0, 0xd4, 0xd8};
647 u8 mc = 0, src_id, node_id;
648 struct skx_dev *d;
649
650 edac_dbg(2, "\n");
651
652 owner = edac_get_owner();
653 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
654 return -EBUSY;
655
656 id = x86_match_cpu(skx_cpuids);
657 if (!id)
658 return -ENODEV;
659
660 rc = skx_get_hi_lo(0x2034, off, &skx_tolm, &skx_tohm);
661 if (rc)
662 return rc;
663
664 rc = skx_get_all_bus_mappings(0x2016, 0xcc, SKX, &skx_edac_list);
665 if (rc < 0)
666 goto fail;
667 if (rc == 0) {
668 edac_dbg(2, "No memory controllers found\n");
669 return -ENODEV;
670 }
671 skx_num_sockets = rc;
672
673 for (m = skx_all_munits; m->did; m++) {
674 rc = get_all_munits(m);
675 if (rc < 0)
676 goto fail;
677 if (rc != m->per_socket * skx_num_sockets) {
678 edac_dbg(2, "Expected %d, got %d of 0x%x\n",
679 m->per_socket * skx_num_sockets, rc, m->did);
680 rc = -ENODEV;
681 goto fail;
682 }
683 }
684
685 list_for_each_entry(d, skx_edac_list, list) {
686 rc = skx_get_src_id(d, 0xf0, &src_id);
687 if (rc < 0)
688 goto fail;
689 rc = skx_get_node_id(d, &node_id);
690 if (rc < 0)
691 goto fail;
692 edac_dbg(2, "src_id=%d node_id=%d\n", src_id, node_id);
693 for (i = 0; i < SKX_NUM_IMC; i++) {
694 d->imc[i].mc = mc++;
695 d->imc[i].lmc = i;
696 d->imc[i].src_id = src_id;
697 d->imc[i].node_id = node_id;
698 rc = skx_register_mci(&d->imc[i], d->imc[i].chan[0].cdev,
699 "Skylake Socket", EDAC_MOD_STR,
700 skx_get_dimm_config);
701 if (rc < 0)
702 goto fail;
703 }
704 }
705
706 skx_set_decode(skx_decode, skx_show_retry_rd_err_log);
707
708 if (nvdimm_count && skx_adxl_get() == -ENODEV)
709 skx_printk(KERN_NOTICE, "Only decoding DDR4 address!\n");
710
711 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
712 opstate_init();
713
714 setup_skx_debug();
715
716 mce_register_decode_chain(&skx_mce_dec);
717
718 return 0;
719 fail:
720 skx_remove();
721 return rc;
722 }
723
724 static void __exit skx_exit(void)
725 {
726 edac_dbg(2, "\n");
727 mce_unregister_decode_chain(&skx_mce_dec);
728 teardown_skx_debug();
729 if (nvdimm_count)
730 skx_adxl_put();
731 skx_remove();
732 }
733
734 module_init(skx_init);
735 module_exit(skx_exit);
736
737 module_param(edac_op_state, int, 0444);
738 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
739
740 MODULE_LICENSE("GPL v2");
741 MODULE_AUTHOR("Tony Luck");
742 MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors");
Linux with added FPC-III support