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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_amdkfd_gfx_v9.c
blob8562afe5b761382c5492b230493c56998068bc1c
1 /*
2 * Copyright 2014-2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include <linux/mmu_context.h>
23
24 #include "amdgpu.h"
25 #include "amdgpu_amdkfd.h"
26 #include "gc/gc_9_0_offset.h"
27 #include "gc/gc_9_0_sh_mask.h"
28 #include "vega10_enum.h"
29 #include "sdma0/sdma0_4_0_offset.h"
30 #include "sdma0/sdma0_4_0_sh_mask.h"
31 #include "sdma1/sdma1_4_0_offset.h"
32 #include "sdma1/sdma1_4_0_sh_mask.h"
33 #include "athub/athub_1_0_offset.h"
34 #include "athub/athub_1_0_sh_mask.h"
35 #include "oss/osssys_4_0_offset.h"
36 #include "oss/osssys_4_0_sh_mask.h"
37 #include "soc15_common.h"
38 #include "v9_structs.h"
39 #include "soc15.h"
40 #include "soc15d.h"
41 #include "mmhub_v1_0.h"
42 #include "gfxhub_v1_0.h"
43
44
45 enum hqd_dequeue_request_type {
46 NO_ACTION = 0,
47 DRAIN_PIPE,
48 RESET_WAVES
49 };
50
51
52 /* Because of REG_GET_FIELD() being used, we put this function in the
53 * asic specific file.
54 */
55 int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
56 struct tile_config *config)
57 {
58 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
59
60 config->gb_addr_config = adev->gfx.config.gb_addr_config;
61
62 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
63 config->num_tile_configs =
64 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
65 config->macro_tile_config_ptr =
66 adev->gfx.config.macrotile_mode_array;
67 config->num_macro_tile_configs =
68 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
69
70 return 0;
71 }
72
73 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
74 {
75 return (struct amdgpu_device *)kgd;
76 }
77
78 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
79 uint32_t queue, uint32_t vmid)
80 {
81 struct amdgpu_device *adev = get_amdgpu_device(kgd);
82
83 mutex_lock(&adev->srbm_mutex);
84 soc15_grbm_select(adev, mec, pipe, queue, vmid);
85 }
86
87 static void unlock_srbm(struct kgd_dev *kgd)
88 {
89 struct amdgpu_device *adev = get_amdgpu_device(kgd);
90
91 soc15_grbm_select(adev, 0, 0, 0, 0);
92 mutex_unlock(&adev->srbm_mutex);
93 }
94
95 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
96 uint32_t queue_id)
97 {
98 struct amdgpu_device *adev = get_amdgpu_device(kgd);
99
100 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
101 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
102
103 lock_srbm(kgd, mec, pipe, queue_id, 0);
104 }
105
106 static uint64_t get_queue_mask(struct amdgpu_device *adev,
107 uint32_t pipe_id, uint32_t queue_id)
108 {
109 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
110 queue_id;
111
112 return 1ull << bit;
113 }
114
115 static void release_queue(struct kgd_dev *kgd)
116 {
117 unlock_srbm(kgd);
118 }
119
120 void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
121 uint32_t sh_mem_config,
122 uint32_t sh_mem_ape1_base,
123 uint32_t sh_mem_ape1_limit,
124 uint32_t sh_mem_bases)
125 {
126 struct amdgpu_device *adev = get_amdgpu_device(kgd);
127
128 lock_srbm(kgd, 0, 0, 0, vmid);
129
130 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
131 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
132 /* APE1 no longer exists on GFX9 */
133
134 unlock_srbm(kgd);
135 }
136
137 int kgd_gfx_v9_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
138 unsigned int vmid)
139 {
140 struct amdgpu_device *adev = get_amdgpu_device(kgd);
141
142 /*
143 * We have to assume that there is no outstanding mapping.
144 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
145 * a mapping is in progress or because a mapping finished
146 * and the SW cleared it.
147 * So the protocol is to always wait & clear.
148 */
149 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
150 ATC_VMID0_PASID_MAPPING__VALID_MASK;
151
152 /*
153 * need to do this twice, once for gfx and once for mmhub
154 * for ATC add 16 to VMID for mmhub, for IH different registers.
155 * ATC_VMID0..15 registers are separate from ATC_VMID16..31.
156 */
157
158 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
159 pasid_mapping);
160
161 while (!(RREG32(SOC15_REG_OFFSET(
162 ATHUB, 0,
163 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) &
164 (1U << vmid)))
165 cpu_relax();
166
167 WREG32(SOC15_REG_OFFSET(ATHUB, 0,
168 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS),
169 1U << vmid);
170
171 /* Mapping vmid to pasid also for IH block */
172 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
173 pasid_mapping);
174
175 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid,
176 pasid_mapping);
177
178 while (!(RREG32(SOC15_REG_OFFSET(
179 ATHUB, 0,
180 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) &
181 (1U << (vmid + 16))))
182 cpu_relax();
183
184 WREG32(SOC15_REG_OFFSET(ATHUB, 0,
185 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS),
186 1U << (vmid + 16));
187
188 /* Mapping vmid to pasid also for IH block */
189 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid,
190 pasid_mapping);
191 return 0;
192 }
193
194 /* TODO - RING0 form of field is obsolete, seems to date back to SI
195 * but still works
196 */
197
198 int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
199 {
200 struct amdgpu_device *adev = get_amdgpu_device(kgd);
201 uint32_t mec;
202 uint32_t pipe;
203
204 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
205 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
206
207 lock_srbm(kgd, mec, pipe, 0, 0);
208
209 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
210 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
211 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
212
213 unlock_srbm(kgd);
214
215 return 0;
216 }
217
218 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
219 unsigned int engine_id,
220 unsigned int queue_id)
221 {
222 uint32_t sdma_engine_reg_base[2] = {
223 SOC15_REG_OFFSET(SDMA0, 0,
224 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
225 SOC15_REG_OFFSET(SDMA1, 0,
226 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL
227 };
228 uint32_t retval = sdma_engine_reg_base[engine_id]
229 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
230
231 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
232 queue_id, retval);
233
234 return retval;
235 }
236
237 static inline struct v9_mqd *get_mqd(void *mqd)
238 {
239 return (struct v9_mqd *)mqd;
240 }
241
242 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
243 {
244 return (struct v9_sdma_mqd *)mqd;
245 }
246
247 int kgd_gfx_v9_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
248 uint32_t queue_id, uint32_t __user *wptr,
249 uint32_t wptr_shift, uint32_t wptr_mask,
250 struct mm_struct *mm)
251 {
252 struct amdgpu_device *adev = get_amdgpu_device(kgd);
253 struct v9_mqd *m;
254 uint32_t *mqd_hqd;
255 uint32_t reg, hqd_base, data;
256
257 m = get_mqd(mqd);
258
259 acquire_queue(kgd, pipe_id, queue_id);
260
261 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
262 mqd_hqd = &m->cp_mqd_base_addr_lo;
263 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
264
265 for (reg = hqd_base;
266 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
267 WREG32_RLC(reg, mqd_hqd[reg - hqd_base]);
268
269
270 /* Activate doorbell logic before triggering WPTR poll. */
271 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
272 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
273 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
274
275 if (wptr) {
276 /* Don't read wptr with get_user because the user
277 * context may not be accessible (if this function
278 * runs in a work queue). Instead trigger a one-shot
279 * polling read from memory in the CP. This assumes
280 * that wptr is GPU-accessible in the queue's VMID via
281 * ATC or SVM. WPTR==RPTR before starting the poll so
282 * the CP starts fetching new commands from the right
283 * place.
284 *
285 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit
286 * tricky. Assume that the queue didn't overflow. The
287 * number of valid bits in the 32-bit RPTR depends on
288 * the queue size. The remaining bits are taken from
289 * the saved 64-bit WPTR. If the WPTR wrapped, add the
290 * queue size.
291 */
292 uint32_t queue_size =
293 2 << REG_GET_FIELD(m->cp_hqd_pq_control,
294 CP_HQD_PQ_CONTROL, QUEUE_SIZE);
295 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
296
297 if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr)
298 guessed_wptr += queue_size;
299 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
300 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
301
302 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
303 lower_32_bits(guessed_wptr));
304 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
305 upper_32_bits(guessed_wptr));
306 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
307 lower_32_bits((uintptr_t)wptr));
308 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
309 upper_32_bits((uintptr_t)wptr));
310 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
311 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
312 }
313
314 /* Start the EOP fetcher */
315 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
316 REG_SET_FIELD(m->cp_hqd_eop_rptr,
317 CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
318
319 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
320 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
321
322 release_queue(kgd);
323
324 return 0;
325 }
326
327 int kgd_gfx_v9_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
328 uint32_t pipe_id, uint32_t queue_id,
329 uint32_t doorbell_off)
330 {
331 struct amdgpu_device *adev = get_amdgpu_device(kgd);
332 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
333 struct v9_mqd *m;
334 uint32_t mec, pipe;
335 int r;
336
337 m = get_mqd(mqd);
338
339 acquire_queue(kgd, pipe_id, queue_id);
340
341 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
342 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
343
344 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
345 mec, pipe, queue_id);
346
347 spin_lock(&adev->gfx.kiq.ring_lock);
348 r = amdgpu_ring_alloc(kiq_ring, 7);
349 if (r) {
350 pr_err("Failed to alloc KIQ (%d).\n", r);
351 goto out_unlock;
352 }
353
354 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
355 amdgpu_ring_write(kiq_ring,
356 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
357 PACKET3_MAP_QUEUES_VMID(m->cp_hqd_vmid) | /* VMID */
358 PACKET3_MAP_QUEUES_QUEUE(queue_id) |
359 PACKET3_MAP_QUEUES_PIPE(pipe) |
360 PACKET3_MAP_QUEUES_ME((mec - 1)) |
361 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
362 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
363 PACKET3_MAP_QUEUES_ENGINE_SEL(1) | /* engine_sel: hiq */
364 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
365 amdgpu_ring_write(kiq_ring,
366 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(doorbell_off));
367 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo);
368 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi);
369 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo);
370 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
371 amdgpu_ring_commit(kiq_ring);
372
373 out_unlock:
374 spin_unlock(&adev->gfx.kiq.ring_lock);
375 release_queue(kgd);
376
377 return r;
378 }
379
380 int kgd_gfx_v9_hqd_dump(struct kgd_dev *kgd,
381 uint32_t pipe_id, uint32_t queue_id,
382 uint32_t (**dump)[2], uint32_t *n_regs)
383 {
384 struct amdgpu_device *adev = get_amdgpu_device(kgd);
385 uint32_t i = 0, reg;
386 #define HQD_N_REGS 56
387 #define DUMP_REG(addr) do { \
388 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
389 break; \
390 (*dump)[i][0] = (addr) << 2; \
391 (*dump)[i++][1] = RREG32(addr); \
392 } while (0)
393
394 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
395 if (*dump == NULL)
396 return -ENOMEM;
397
398 acquire_queue(kgd, pipe_id, queue_id);
399
400 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
401 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
402 DUMP_REG(reg);
403
404 release_queue(kgd);
405
406 WARN_ON_ONCE(i != HQD_N_REGS);
407 *n_regs = i;
408
409 return 0;
410 }
411
412 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
413 uint32_t __user *wptr, struct mm_struct *mm)
414 {
415 struct amdgpu_device *adev = get_amdgpu_device(kgd);
416 struct v9_sdma_mqd *m;
417 uint32_t sdma_rlc_reg_offset;
418 unsigned long end_jiffies;
419 uint32_t data;
420 uint64_t data64;
421 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
422
423 m = get_sdma_mqd(mqd);
424 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
425 m->sdma_queue_id);
426
427 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
428 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
429
430 end_jiffies = msecs_to_jiffies(2000) + jiffies;
431 while (true) {
432 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
433 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
434 break;
435 if (time_after(jiffies, end_jiffies)) {
436 pr_err("SDMA RLC not idle in %s\n", __func__);
437 return -ETIME;
438 }
439 usleep_range(500, 1000);
440 }
441
442 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
443 m->sdmax_rlcx_doorbell_offset);
444
445 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
446 ENABLE, 1);
447 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
448 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
449 m->sdmax_rlcx_rb_rptr);
450 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
451 m->sdmax_rlcx_rb_rptr_hi);
452
453 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
454 if (read_user_wptr(mm, wptr64, data64)) {
455 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
456 lower_32_bits(data64));
457 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
458 upper_32_bits(data64));
459 } else {
460 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
461 m->sdmax_rlcx_rb_rptr);
462 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
463 m->sdmax_rlcx_rb_rptr_hi);
464 }
465 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
466
467 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
468 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
469 m->sdmax_rlcx_rb_base_hi);
470 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
471 m->sdmax_rlcx_rb_rptr_addr_lo);
472 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
473 m->sdmax_rlcx_rb_rptr_addr_hi);
474
475 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
476 RB_ENABLE, 1);
477 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
478
479 return 0;
480 }
481
482 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
483 uint32_t engine_id, uint32_t queue_id,
484 uint32_t (**dump)[2], uint32_t *n_regs)
485 {
486 struct amdgpu_device *adev = get_amdgpu_device(kgd);
487 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
488 engine_id, queue_id);
489 uint32_t i = 0, reg;
490 #undef HQD_N_REGS
491 #define HQD_N_REGS (19+6+7+10)
492
493 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
494 if (*dump == NULL)
495 return -ENOMEM;
496
497 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
498 DUMP_REG(sdma_rlc_reg_offset + reg);
499 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
500 DUMP_REG(sdma_rlc_reg_offset + reg);
501 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
502 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
503 DUMP_REG(sdma_rlc_reg_offset + reg);
504 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
505 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
506 DUMP_REG(sdma_rlc_reg_offset + reg);
507
508 WARN_ON_ONCE(i != HQD_N_REGS);
509 *n_regs = i;
510
511 return 0;
512 }
513
514 bool kgd_gfx_v9_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
515 uint32_t pipe_id, uint32_t queue_id)
516 {
517 struct amdgpu_device *adev = get_amdgpu_device(kgd);
518 uint32_t act;
519 bool retval = false;
520 uint32_t low, high;
521
522 acquire_queue(kgd, pipe_id, queue_id);
523 act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
524 if (act) {
525 low = lower_32_bits(queue_address >> 8);
526 high = upper_32_bits(queue_address >> 8);
527
528 if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
529 high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
530 retval = true;
531 }
532 release_queue(kgd);
533 return retval;
534 }
535
536 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
537 {
538 struct amdgpu_device *adev = get_amdgpu_device(kgd);
539 struct v9_sdma_mqd *m;
540 uint32_t sdma_rlc_reg_offset;
541 uint32_t sdma_rlc_rb_cntl;
542
543 m = get_sdma_mqd(mqd);
544 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
545 m->sdma_queue_id);
546
547 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
548
549 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
550 return true;
551
552 return false;
553 }
554
555 int kgd_gfx_v9_hqd_destroy(struct kgd_dev *kgd, void *mqd,
556 enum kfd_preempt_type reset_type,
557 unsigned int utimeout, uint32_t pipe_id,
558 uint32_t queue_id)
559 {
560 struct amdgpu_device *adev = get_amdgpu_device(kgd);
561 enum hqd_dequeue_request_type type;
562 unsigned long end_jiffies;
563 uint32_t temp;
564 struct v9_mqd *m = get_mqd(mqd);
565
566 if (adev->in_gpu_reset)
567 return -EIO;
568
569 acquire_queue(kgd, pipe_id, queue_id);
570
571 if (m->cp_hqd_vmid == 0)
572 WREG32_FIELD15_RLC(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);
573
574 switch (reset_type) {
575 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
576 type = DRAIN_PIPE;
577 break;
578 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
579 type = RESET_WAVES;
580 break;
581 default:
582 type = DRAIN_PIPE;
583 break;
584 }
585
586 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
587
588 end_jiffies = (utimeout * HZ / 1000) + jiffies;
589 while (true) {
590 temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
591 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
592 break;
593 if (time_after(jiffies, end_jiffies)) {
594 pr_err("cp queue preemption time out.\n");
595 release_queue(kgd);
596 return -ETIME;
597 }
598 usleep_range(500, 1000);
599 }
600
601 release_queue(kgd);
602 return 0;
603 }
604
605 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
606 unsigned int utimeout)
607 {
608 struct amdgpu_device *adev = get_amdgpu_device(kgd);
609 struct v9_sdma_mqd *m;
610 uint32_t sdma_rlc_reg_offset;
611 uint32_t temp;
612 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
613
614 m = get_sdma_mqd(mqd);
615 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
616 m->sdma_queue_id);
617
618 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
619 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
620 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
621
622 while (true) {
623 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
624 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
625 break;
626 if (time_after(jiffies, end_jiffies)) {
627 pr_err("SDMA RLC not idle in %s\n", __func__);
628 return -ETIME;
629 }
630 usleep_range(500, 1000);
631 }
632
633 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
634 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
635 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
636 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
637
638 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
639 m->sdmax_rlcx_rb_rptr_hi =
640 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
641
642 return 0;
643 }
644
645 bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
646 uint8_t vmid, uint16_t *p_pasid)
647 {
648 uint32_t value;
649 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
650
651 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
652 + vmid);
653 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
654
655 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
656 }
657
658 int kgd_gfx_v9_address_watch_disable(struct kgd_dev *kgd)
659 {
660 return 0;
661 }
662
663 int kgd_gfx_v9_address_watch_execute(struct kgd_dev *kgd,
664 unsigned int watch_point_id,
665 uint32_t cntl_val,
666 uint32_t addr_hi,
667 uint32_t addr_lo)
668 {
669 return 0;
670 }
671
672 int kgd_gfx_v9_wave_control_execute(struct kgd_dev *kgd,
673 uint32_t gfx_index_val,
674 uint32_t sq_cmd)
675 {
676 struct amdgpu_device *adev = get_amdgpu_device(kgd);
677 uint32_t data = 0;
678
679 mutex_lock(&adev->grbm_idx_mutex);
680
681 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
682 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
683
684 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
685 INSTANCE_BROADCAST_WRITES, 1);
686 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
687 SH_BROADCAST_WRITES, 1);
688 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
689 SE_BROADCAST_WRITES, 1);
690
691 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data);
692 mutex_unlock(&adev->grbm_idx_mutex);
693
694 return 0;
695 }
696
697 uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd,
698 unsigned int watch_point_id,
699 unsigned int reg_offset)
700 {
701 return 0;
702 }
703
704 static void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd,
705 uint32_t vmid, uint64_t page_table_base)
706 {
707 struct amdgpu_device *adev = get_amdgpu_device(kgd);
708
709 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
710 pr_err("trying to set page table base for wrong VMID %u\n",
711 vmid);
712 return;
713 }
714
715 mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
716
717 gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
718 }
719
720 const struct kfd2kgd_calls gfx_v9_kfd2kgd = {
721 .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
722 .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
723 .init_interrupts = kgd_gfx_v9_init_interrupts,
724 .hqd_load = kgd_gfx_v9_hqd_load,
725 .hiq_mqd_load = kgd_gfx_v9_hiq_mqd_load,
726 .hqd_sdma_load = kgd_hqd_sdma_load,
727 .hqd_dump = kgd_gfx_v9_hqd_dump,
728 .hqd_sdma_dump = kgd_hqd_sdma_dump,
729 .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied,
730 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
731 .hqd_destroy = kgd_gfx_v9_hqd_destroy,
732 .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
733 .address_watch_disable = kgd_gfx_v9_address_watch_disable,
734 .address_watch_execute = kgd_gfx_v9_address_watch_execute,
735 .wave_control_execute = kgd_gfx_v9_wave_control_execute,
736 .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
737 .get_atc_vmid_pasid_mapping_info =
738 kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
739 .get_tile_config = kgd_gfx_v9_get_tile_config,
740 .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
741 .get_hive_id = amdgpu_amdkfd_get_hive_id,
742 };
Linux with added FPC-III support