drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_fb_helper.h>
  29 #include <drm/drm_probe_helper.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu.h"
  32 #include "atom.h"
  33 #include "atombios_encoders.h"
  34 #include "atombios_dp.h"
  35 #include "amdgpu_connectors.h"
  36 #include "amdgpu_i2c.h"
  37 #include "amdgpu_display.h"
  38
  39 #include <linux/pm_runtime.h>
  40
  41 void amdgpu_connector_hotplug(struct drm_connector *connector)
  42 {
  43         struct drm_device *dev = connector->dev;
  44         struct amdgpu_device *adev = dev->dev_private;
  45         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  46
  47         /* bail if the connector does not have hpd pin, e.g.,
  48          * VGA, TV, etc.
  49          */
  50         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
  51                 return;
  52
  53         amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  54
  55         /* if the connector is already off, don't turn it back on */
  56         if (connector->dpms != DRM_MODE_DPMS_ON)
  57                 return;
  58
  59         /* just deal with DP (not eDP) here. */
  60         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
  61                 struct amdgpu_connector_atom_dig *dig_connector =
  62                         amdgpu_connector->con_priv;
  63
  64                 /* if existing sink type was not DP no need to retrain */
  65                 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
  66                         return;
  67
  68                 /* first get sink type as it may be reset after (un)plug */
  69                 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
  70                 /* don't do anything if sink is not display port, i.e.,
  71                  * passive dp->(dvi|hdmi) adaptor
  72                  */
  73                 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
  74                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
  75                     amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
  76                         /* Don't start link training before we have the DPCD */
  77                         if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
  78                                 return;
  79
  80                         /* Turn the connector off and back on immediately, which
  81                          * will trigger link training
  82                          */
  83                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  84                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  85                 }
  86         }
  87 }
  88
  89 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
  90 {
  91         struct drm_crtc *crtc = encoder->crtc;
  92
  93         if (crtc && crtc->enabled) {
  94                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
  95                                          crtc->x, crtc->y, crtc->primary->fb);
  96         }
  97 }
  98
  99 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
 100 {
 101         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 102         struct amdgpu_connector_atom_dig *dig_connector;
 103         int bpc = 8;
 104         unsigned mode_clock, max_tmds_clock;
 105
 106         switch (connector->connector_type) {
 107         case DRM_MODE_CONNECTOR_DVII:
 108         case DRM_MODE_CONNECTOR_HDMIB:
 109                 if (amdgpu_connector->use_digital) {
 110                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 111                                 if (connector->display_info.bpc)
 112                                         bpc = connector->display_info.bpc;
 113                         }
 114                 }
 115                 break;
 116         case DRM_MODE_CONNECTOR_DVID:
 117         case DRM_MODE_CONNECTOR_HDMIA:
 118                 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 119                         if (connector->display_info.bpc)
 120                                 bpc = connector->display_info.bpc;
 121                 }
 122                 break;
 123         case DRM_MODE_CONNECTOR_DisplayPort:
 124                 dig_connector = amdgpu_connector->con_priv;
 125                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 126                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
 127                     drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 128                         if (connector->display_info.bpc)
 129                                 bpc = connector->display_info.bpc;
 130                 }
 131                 break;
 132         case DRM_MODE_CONNECTOR_eDP:
 133         case DRM_MODE_CONNECTOR_LVDS:
 134                 if (connector->display_info.bpc)
 135                         bpc = connector->display_info.bpc;
 136                 else {
 137                         const struct drm_connector_helper_funcs *connector_funcs =
 138                                 connector->helper_private;
 139                         struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
 140                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 141                         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 142
 143                         if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
 144                                 bpc = 6;
 145                         else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
 146                                 bpc = 8;
 147                 }
 148                 break;
 149         }
 150
 151         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 152                 /*
 153                  * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
 154                  * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
 155                  * 12 bpc is always supported on hdmi deep color sinks, as this is
 156                  * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
 157                  */
 158                 if (bpc > 12) {
 159                         DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
 160                                   connector->name, bpc);
 161                         bpc = 12;
 162                 }
 163
 164                 /* Any defined maximum tmds clock limit we must not exceed? */
 165                 if (connector->display_info.max_tmds_clock > 0) {
 166                         /* mode_clock is clock in kHz for mode to be modeset on this connector */
 167                         mode_clock = amdgpu_connector->pixelclock_for_modeset;
 168
 169                         /* Maximum allowable input clock in kHz */
 170                         max_tmds_clock = connector->display_info.max_tmds_clock;
 171
 172                         DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
 173                                   connector->name, mode_clock, max_tmds_clock);
 174
 175                         /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
 176                         if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
 177                                 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
 178                                     (mode_clock * 5/4 <= max_tmds_clock))
 179                                         bpc = 10;
 180                                 else
 181                                         bpc = 8;
 182
 183                                 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
 184                                           connector->name, bpc);
 185                         }
 186
 187                         if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
 188                                 bpc = 8;
 189                                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
 190                                           connector->name, bpc);
 191                         }
 192                 } else if (bpc > 8) {
 193                         /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
 194                         DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
 195                                   connector->name);
 196                         bpc = 8;
 197                 }
 198         }
 199
 200         if ((amdgpu_deep_color == 0) && (bpc > 8)) {
 201                 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
 202                           connector->name);
 203                 bpc = 8;
 204         }
 205
 206         DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
 207                   connector->name, connector->display_info.bpc, bpc);
 208
 209         return bpc;
 210 }
 211
 212 static void
 213 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
 214                                       enum drm_connector_status status)
 215 {
 216         struct drm_encoder *best_encoder;
 217         struct drm_encoder *encoder;
 218         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 219         bool connected;
 220
 221         best_encoder = connector_funcs->best_encoder(connector);
 222
 223         drm_connector_for_each_possible_encoder(connector, encoder) {
 224                 if ((encoder == best_encoder) && (status == connector_status_connected))
 225                         connected = true;
 226                 else
 227                         connected = false;
 228
 229                 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
 230         }
 231 }
 232
 233 static struct drm_encoder *
 234 amdgpu_connector_find_encoder(struct drm_connector *connector,
 235                                int encoder_type)
 236 {
 237         struct drm_encoder *encoder;
 238
 239         drm_connector_for_each_possible_encoder(connector, encoder) {
 240                 if (encoder->encoder_type == encoder_type)
 241                         return encoder;
 242         }
 243
 244         return NULL;
 245 }
 246
 247 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
 248 {
 249         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 250         struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
 251
 252         if (amdgpu_connector->edid) {
 253                 return amdgpu_connector->edid;
 254         } else if (edid_blob) {
 255                 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
 256                 if (edid)
 257                         amdgpu_connector->edid = edid;
 258         }
 259         return amdgpu_connector->edid;
 260 }
 261
 262 static struct edid *
 263 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
 264 {
 265         struct edid *edid;
 266
 267         if (adev->mode_info.bios_hardcoded_edid) {
 268                 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 269                 if (edid) {
 270                         memcpy((unsigned char *)edid,
 271                                (unsigned char *)adev->mode_info.bios_hardcoded_edid,
 272                                adev->mode_info.bios_hardcoded_edid_size);
 273                         return edid;
 274                 }
 275         }
 276         return NULL;
 277 }
 278
 279 static void amdgpu_connector_get_edid(struct drm_connector *connector)
 280 {
 281         struct drm_device *dev = connector->dev;
 282         struct amdgpu_device *adev = dev->dev_private;
 283         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 284
 285         if (amdgpu_connector->edid)
 286                 return;
 287
 288         /* on hw with routers, select right port */
 289         if (amdgpu_connector->router.ddc_valid)
 290                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 291
 292         if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
 293              ENCODER_OBJECT_ID_NONE) &&
 294             amdgpu_connector->ddc_bus->has_aux) {
 295                 amdgpu_connector->edid = drm_get_edid(connector,
 296                                                       &amdgpu_connector->ddc_bus->aux.ddc);
 297         } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 298                    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
 299                 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 300
 301                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 302                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 303                     amdgpu_connector->ddc_bus->has_aux)
 304                         amdgpu_connector->edid = drm_get_edid(connector,
 305                                                               &amdgpu_connector->ddc_bus->aux.ddc);
 306                 else if (amdgpu_connector->ddc_bus)
 307                         amdgpu_connector->edid = drm_get_edid(connector,
 308                                                               &amdgpu_connector->ddc_bus->adapter);
 309         } else if (amdgpu_connector->ddc_bus) {
 310                 amdgpu_connector->edid = drm_get_edid(connector,
 311                                                       &amdgpu_connector->ddc_bus->adapter);
 312         }
 313
 314         if (!amdgpu_connector->edid) {
 315                 /* some laptops provide a hardcoded edid in rom for LCDs */
 316                 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 317                      (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
 318                         amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
 319         }
 320 }
 321
 322 static void amdgpu_connector_free_edid(struct drm_connector *connector)
 323 {
 324         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 325
 326         kfree(amdgpu_connector->edid);
 327         amdgpu_connector->edid = NULL;
 328 }
 329
 330 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
 331 {
 332         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 333         int ret;
 334
 335         if (amdgpu_connector->edid) {
 336                 drm_connector_update_edid_property(connector, amdgpu_connector->edid);
 337                 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
 338                 return ret;
 339         }
 340         drm_connector_update_edid_property(connector, NULL);
 341         return 0;
 342 }
 343
 344 static struct drm_encoder *
 345 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 346 {
 347         struct drm_encoder *encoder;
 348
 349         /* pick the first one */
 350         drm_connector_for_each_possible_encoder(connector, encoder)
 351                 return encoder;
 352
 353         return NULL;
 354 }
 355
 356 static void amdgpu_get_native_mode(struct drm_connector *connector)
 357 {
 358         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 359         struct amdgpu_encoder *amdgpu_encoder;
 360
 361         if (encoder == NULL)
 362                 return;
 363
 364         amdgpu_encoder = to_amdgpu_encoder(encoder);
 365
 366         if (!list_empty(&connector->probed_modes)) {
 367                 struct drm_display_mode *preferred_mode =
 368                         list_first_entry(&connector->probed_modes,
 369                                          struct drm_display_mode, head);
 370
 371                 amdgpu_encoder->native_mode = *preferred_mode;
 372         } else {
 373                 amdgpu_encoder->native_mode.clock = 0;
 374         }
 375 }
 376
 377 static struct drm_display_mode *
 378 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
 379 {
 380         struct drm_device *dev = encoder->dev;
 381         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 382         struct drm_display_mode *mode = NULL;
 383         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 384
 385         if (native_mode->hdisplay != 0 &&
 386             native_mode->vdisplay != 0 &&
 387             native_mode->clock != 0) {
 388                 mode = drm_mode_duplicate(dev, native_mode);
 389                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 390                 drm_mode_set_name(mode);
 391
 392                 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
 393         } else if (native_mode->hdisplay != 0 &&
 394                    native_mode->vdisplay != 0) {
 395                 /* mac laptops without an edid */
 396                 /* Note that this is not necessarily the exact panel mode,
 397                  * but an approximation based on the cvt formula.  For these
 398                  * systems we should ideally read the mode info out of the
 399                  * registers or add a mode table, but this works and is much
 400                  * simpler.
 401                  */
 402                 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
 403                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 404                 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
 405         }
 406         return mode;
 407 }
 408
 409 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
 410                                                struct drm_connector *connector)
 411 {
 412         struct drm_device *dev = encoder->dev;
 413         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 414         struct drm_display_mode *mode = NULL;
 415         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 416         int i;
 417         static const struct mode_size {
 418                 int w;
 419                 int h;
 420         } common_modes[17] = {
 421                 { 640,  480},
 422                 { 720,  480},
 423                 { 800,  600},
 424                 { 848,  480},
 425                 {1024,  768},
 426                 {1152,  768},
 427                 {1280,  720},
 428                 {1280,  800},
 429                 {1280,  854},
 430                 {1280,  960},
 431                 {1280, 1024},
 432                 {1440,  900},
 433                 {1400, 1050},
 434                 {1680, 1050},
 435                 {1600, 1200},
 436                 {1920, 1080},
 437                 {1920, 1200}
 438         };
 439
 440         for (i = 0; i < 17; i++) {
 441                 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 442                         if (common_modes[i].w > 1024 ||
 443                             common_modes[i].h > 768)
 444                                 continue;
 445                 }
 446                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 447                         if (common_modes[i].w > native_mode->hdisplay ||
 448                             common_modes[i].h > native_mode->vdisplay ||
 449                             (common_modes[i].w == native_mode->hdisplay &&
 450                              common_modes[i].h == native_mode->vdisplay))
 451                                 continue;
 452                 }
 453                 if (common_modes[i].w < 320 || common_modes[i].h < 200)
 454                         continue;
 455
 456                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 457                 drm_mode_probed_add(connector, mode);
 458         }
 459 }
 460
 461 static int amdgpu_connector_set_property(struct drm_connector *connector,
 462                                           struct drm_property *property,
 463                                           uint64_t val)
 464 {
 465         struct drm_device *dev = connector->dev;
 466         struct amdgpu_device *adev = dev->dev_private;
 467         struct drm_encoder *encoder;
 468         struct amdgpu_encoder *amdgpu_encoder;
 469
 470         if (property == adev->mode_info.coherent_mode_property) {
 471                 struct amdgpu_encoder_atom_dig *dig;
 472                 bool new_coherent_mode;
 473
 474                 /* need to find digital encoder on connector */
 475                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 476                 if (!encoder)
 477                         return 0;
 478
 479                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 480
 481                 if (!amdgpu_encoder->enc_priv)
 482                         return 0;
 483
 484                 dig = amdgpu_encoder->enc_priv;
 485                 new_coherent_mode = val ? true : false;
 486                 if (dig->coherent_mode != new_coherent_mode) {
 487                         dig->coherent_mode = new_coherent_mode;
 488                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 489                 }
 490         }
 491
 492         if (property == adev->mode_info.audio_property) {
 493                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 494                 /* need to find digital encoder on connector */
 495                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 496                 if (!encoder)
 497                         return 0;
 498
 499                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 500
 501                 if (amdgpu_connector->audio != val) {
 502                         amdgpu_connector->audio = val;
 503                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 504                 }
 505         }
 506
 507         if (property == adev->mode_info.dither_property) {
 508                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 509                 /* need to find digital encoder on connector */
 510                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 511                 if (!encoder)
 512                         return 0;
 513
 514                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 515
 516                 if (amdgpu_connector->dither != val) {
 517                         amdgpu_connector->dither = val;
 518                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 519                 }
 520         }
 521
 522         if (property == adev->mode_info.underscan_property) {
 523                 /* need to find digital encoder on connector */
 524                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 525                 if (!encoder)
 526                         return 0;
 527
 528                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 529
 530                 if (amdgpu_encoder->underscan_type != val) {
 531                         amdgpu_encoder->underscan_type = val;
 532                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 533                 }
 534         }
 535
 536         if (property == adev->mode_info.underscan_hborder_property) {
 537                 /* need to find digital encoder on connector */
 538                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 539                 if (!encoder)
 540                         return 0;
 541
 542                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 543
 544                 if (amdgpu_encoder->underscan_hborder != val) {
 545                         amdgpu_encoder->underscan_hborder = val;
 546                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 547                 }
 548         }
 549
 550         if (property == adev->mode_info.underscan_vborder_property) {
 551                 /* need to find digital encoder on connector */
 552                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 553                 if (!encoder)
 554                         return 0;
 555
 556                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 557
 558                 if (amdgpu_encoder->underscan_vborder != val) {
 559                         amdgpu_encoder->underscan_vborder = val;
 560                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 561                 }
 562         }
 563
 564         if (property == adev->mode_info.load_detect_property) {
 565                 struct amdgpu_connector *amdgpu_connector =
 566                         to_amdgpu_connector(connector);
 567
 568                 if (val == 0)
 569                         amdgpu_connector->dac_load_detect = false;
 570                 else
 571                         amdgpu_connector->dac_load_detect = true;
 572         }
 573
 574         if (property == dev->mode_config.scaling_mode_property) {
 575                 enum amdgpu_rmx_type rmx_type;
 576
 577                 if (connector->encoder) {
 578                         amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 579                 } else {
 580                         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 581                         amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 582                 }
 583
 584                 switch (val) {
 585                 default:
 586                 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 587                 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 588                 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 589                 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 590                 }
 591                 if (amdgpu_encoder->rmx_type == rmx_type)
 592                         return 0;
 593
 594                 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
 595                     (amdgpu_encoder->native_mode.clock == 0))
 596                         return 0;
 597
 598                 amdgpu_encoder->rmx_type = rmx_type;
 599
 600                 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 601         }
 602
 603         return 0;
 604 }
 605
 606 static void
 607 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
 608                                         struct drm_connector *connector)
 609 {
 610         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 611         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 612         struct drm_display_mode *t, *mode;
 613
 614         /* If the EDID preferred mode doesn't match the native mode, use it */
 615         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 616                 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
 617                         if (mode->hdisplay != native_mode->hdisplay ||
 618                             mode->vdisplay != native_mode->vdisplay)
 619                                 memcpy(native_mode, mode, sizeof(*mode));
 620                 }
 621         }
 622
 623         /* Try to get native mode details from EDID if necessary */
 624         if (!native_mode->clock) {
 625                 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 626                         if (mode->hdisplay == native_mode->hdisplay &&
 627                             mode->vdisplay == native_mode->vdisplay) {
 628                                 *native_mode = *mode;
 629                                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
 630                                 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
 631                                 break;
 632                         }
 633                 }
 634         }
 635
 636         if (!native_mode->clock) {
 637                 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
 638                 amdgpu_encoder->rmx_type = RMX_OFF;
 639         }
 640 }
 641
 642 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
 643 {
 644         struct drm_encoder *encoder;
 645         int ret = 0;
 646         struct drm_display_mode *mode;
 647
 648         amdgpu_connector_get_edid(connector);
 649         ret = amdgpu_connector_ddc_get_modes(connector);
 650         if (ret > 0) {
 651                 encoder = amdgpu_connector_best_single_encoder(connector);
 652                 if (encoder) {
 653                         amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
 654                         /* add scaled modes */
 655                         amdgpu_connector_add_common_modes(encoder, connector);
 656                 }
 657                 return ret;
 658         }
 659
 660         encoder = amdgpu_connector_best_single_encoder(connector);
 661         if (!encoder)
 662                 return 0;
 663
 664         /* we have no EDID modes */
 665         mode = amdgpu_connector_lcd_native_mode(encoder);
 666         if (mode) {
 667                 ret = 1;
 668                 drm_mode_probed_add(connector, mode);
 669                 /* add the width/height from vbios tables if available */
 670                 connector->display_info.width_mm = mode->width_mm;
 671                 connector->display_info.height_mm = mode->height_mm;
 672                 /* add scaled modes */
 673                 amdgpu_connector_add_common_modes(encoder, connector);
 674         }
 675
 676         return ret;
 677 }
 678
 679 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
 680                                              struct drm_display_mode *mode)
 681 {
 682         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 683
 684         if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
 685                 return MODE_PANEL;
 686
 687         if (encoder) {
 688                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 689                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 690
 691                 /* AVIVO hardware supports downscaling modes larger than the panel
 692                  * to the panel size, but I'm not sure this is desirable.
 693                  */
 694                 if ((mode->hdisplay > native_mode->hdisplay) ||
 695                     (mode->vdisplay > native_mode->vdisplay))
 696                         return MODE_PANEL;
 697
 698                 /* if scaling is disabled, block non-native modes */
 699                 if (amdgpu_encoder->rmx_type == RMX_OFF) {
 700                         if ((mode->hdisplay != native_mode->hdisplay) ||
 701                             (mode->vdisplay != native_mode->vdisplay))
 702                                 return MODE_PANEL;
 703                 }
 704         }
 705
 706         return MODE_OK;
 707 }
 708
 709 static enum drm_connector_status
 710 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
 711 {
 712         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 713         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 714         enum drm_connector_status ret = connector_status_disconnected;
 715         int r;
 716
 717         if (!drm_kms_helper_is_poll_worker()) {
 718                 r = pm_runtime_get_sync(connector->dev->dev);
 719                 if (r < 0)
 720                         return connector_status_disconnected;
 721         }
 722
 723         if (encoder) {
 724                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 725                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 726
 727                 /* check if panel is valid */
 728                 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
 729                         ret = connector_status_connected;
 730
 731         }
 732
 733         /* check for edid as well */
 734         amdgpu_connector_get_edid(connector);
 735         if (amdgpu_connector->edid)
 736                 ret = connector_status_connected;
 737         /* check acpi lid status ??? */
 738
 739         amdgpu_connector_update_scratch_regs(connector, ret);
 740
 741         if (!drm_kms_helper_is_poll_worker()) {
 742                 pm_runtime_mark_last_busy(connector->dev->dev);
 743                 pm_runtime_put_autosuspend(connector->dev->dev);
 744         }
 745
 746         return ret;
 747 }
 748
 749 static void amdgpu_connector_unregister(struct drm_connector *connector)
 750 {
 751         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 752
 753         if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
 754                 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
 755                 amdgpu_connector->ddc_bus->has_aux = false;
 756         }
 757 }
 758
 759 static void amdgpu_connector_destroy(struct drm_connector *connector)
 760 {
 761         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 762
 763         amdgpu_connector_free_edid(connector);
 764         kfree(amdgpu_connector->con_priv);
 765         drm_connector_unregister(connector);
 766         drm_connector_cleanup(connector);
 767         kfree(connector);
 768 }
 769
 770 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 771                                               struct drm_property *property,
 772                                               uint64_t value)
 773 {
 774         struct drm_device *dev = connector->dev;
 775         struct amdgpu_encoder *amdgpu_encoder;
 776         enum amdgpu_rmx_type rmx_type;
 777
 778         DRM_DEBUG_KMS("\n");
 779         if (property != dev->mode_config.scaling_mode_property)
 780                 return 0;
 781
 782         if (connector->encoder)
 783                 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 784         else {
 785                 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 786                 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 787         }
 788
 789         switch (value) {
 790         case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 791         case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 792         case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 793         default:
 794         case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 795         }
 796         if (amdgpu_encoder->rmx_type == rmx_type)
 797                 return 0;
 798
 799         amdgpu_encoder->rmx_type = rmx_type;
 800
 801         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 802         return 0;
 803 }
 804
 805
 806 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
 807         .get_modes = amdgpu_connector_lvds_get_modes,
 808         .mode_valid = amdgpu_connector_lvds_mode_valid,
 809         .best_encoder = amdgpu_connector_best_single_encoder,
 810 };
 811
 812 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
 813         .dpms = drm_helper_connector_dpms,
 814         .detect = amdgpu_connector_lvds_detect,
 815         .fill_modes = drm_helper_probe_single_connector_modes,
 816         .early_unregister = amdgpu_connector_unregister,
 817         .destroy = amdgpu_connector_destroy,
 818         .set_property = amdgpu_connector_set_lcd_property,
 819 };
 820
 821 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
 822 {
 823         int ret;
 824
 825         amdgpu_connector_get_edid(connector);
 826         ret = amdgpu_connector_ddc_get_modes(connector);
 827
 828         return ret;
 829 }
 830
 831 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
 832                                             struct drm_display_mode *mode)
 833 {
 834         struct drm_device *dev = connector->dev;
 835         struct amdgpu_device *adev = dev->dev_private;
 836
 837         /* XXX check mode bandwidth */
 838
 839         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
 840                 return MODE_CLOCK_HIGH;
 841
 842         return MODE_OK;
 843 }
 844
 845 static enum drm_connector_status
 846 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
 847 {
 848         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 849         struct drm_encoder *encoder;
 850         const struct drm_encoder_helper_funcs *encoder_funcs;
 851         bool dret = false;
 852         enum drm_connector_status ret = connector_status_disconnected;
 853         int r;
 854
 855         if (!drm_kms_helper_is_poll_worker()) {
 856                 r = pm_runtime_get_sync(connector->dev->dev);
 857                 if (r < 0)
 858                         return connector_status_disconnected;
 859         }
 860
 861         encoder = amdgpu_connector_best_single_encoder(connector);
 862         if (!encoder)
 863                 ret = connector_status_disconnected;
 864
 865         if (amdgpu_connector->ddc_bus)
 866                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
 867         if (dret) {
 868                 amdgpu_connector->detected_by_load = false;
 869                 amdgpu_connector_free_edid(connector);
 870                 amdgpu_connector_get_edid(connector);
 871
 872                 if (!amdgpu_connector->edid) {
 873                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 874                                         connector->name);
 875                         ret = connector_status_connected;
 876                 } else {
 877                         amdgpu_connector->use_digital =
 878                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 879
 880                         /* some oems have boards with separate digital and analog connectors
 881                          * with a shared ddc line (often vga + hdmi)
 882                          */
 883                         if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
 884                                 amdgpu_connector_free_edid(connector);
 885                                 ret = connector_status_disconnected;
 886                         } else {
 887                                 ret = connector_status_connected;
 888                         }
 889                 }
 890         } else {
 891
 892                 /* if we aren't forcing don't do destructive polling */
 893                 if (!force) {
 894                         /* only return the previous status if we last
 895                          * detected a monitor via load.
 896                          */
 897                         if (amdgpu_connector->detected_by_load)
 898                                 ret = connector->status;
 899                         goto out;
 900                 }
 901
 902                 if (amdgpu_connector->dac_load_detect && encoder) {
 903                         encoder_funcs = encoder->helper_private;
 904                         ret = encoder_funcs->detect(encoder, connector);
 905                         if (ret != connector_status_disconnected)
 906                                 amdgpu_connector->detected_by_load = true;
 907                 }
 908         }
 909
 910         amdgpu_connector_update_scratch_regs(connector, ret);
 911
 912 out:
 913         if (!drm_kms_helper_is_poll_worker()) {
 914                 pm_runtime_mark_last_busy(connector->dev->dev);
 915                 pm_runtime_put_autosuspend(connector->dev->dev);
 916         }
 917
 918         return ret;
 919 }
 920
 921 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
 922         .get_modes = amdgpu_connector_vga_get_modes,
 923         .mode_valid = amdgpu_connector_vga_mode_valid,
 924         .best_encoder = amdgpu_connector_best_single_encoder,
 925 };
 926
 927 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
 928         .dpms = drm_helper_connector_dpms,
 929         .detect = amdgpu_connector_vga_detect,
 930         .fill_modes = drm_helper_probe_single_connector_modes,
 931         .early_unregister = amdgpu_connector_unregister,
 932         .destroy = amdgpu_connector_destroy,
 933         .set_property = amdgpu_connector_set_property,
 934 };
 935
 936 static bool
 937 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
 938 {
 939         struct drm_device *dev = connector->dev;
 940         struct amdgpu_device *adev = dev->dev_private;
 941         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 942         enum drm_connector_status status;
 943
 944         if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
 945                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
 946                         status = connector_status_connected;
 947                 else
 948                         status = connector_status_disconnected;
 949                 if (connector->status == status)
 950                         return true;
 951         }
 952
 953         return false;
 954 }
 955
 956 /*
 957  * DVI is complicated
 958  * Do a DDC probe, if DDC probe passes, get the full EDID so
 959  * we can do analog/digital monitor detection at this point.
 960  * If the monitor is an analog monitor or we got no DDC,
 961  * we need to find the DAC encoder object for this connector.
 962  * If we got no DDC, we do load detection on the DAC encoder object.
 963  * If we got analog DDC or load detection passes on the DAC encoder
 964  * we have to check if this analog encoder is shared with anyone else (TV)
 965  * if its shared we have to set the other connector to disconnected.
 966  */
 967 static enum drm_connector_status
 968 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
 969 {
 970         struct drm_device *dev = connector->dev;
 971         struct amdgpu_device *adev = dev->dev_private;
 972         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 973         const struct drm_encoder_helper_funcs *encoder_funcs;
 974         int r;
 975         enum drm_connector_status ret = connector_status_disconnected;
 976         bool dret = false, broken_edid = false;
 977
 978         if (!drm_kms_helper_is_poll_worker()) {
 979                 r = pm_runtime_get_sync(connector->dev->dev);
 980                 if (r < 0)
 981                         return connector_status_disconnected;
 982         }
 983
 984         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
 985                 ret = connector->status;
 986                 goto exit;
 987         }
 988
 989         if (amdgpu_connector->ddc_bus)
 990                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
 991         if (dret) {
 992                 amdgpu_connector->detected_by_load = false;
 993                 amdgpu_connector_free_edid(connector);
 994                 amdgpu_connector_get_edid(connector);
 995
 996                 if (!amdgpu_connector->edid) {
 997                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 998                                         connector->name);
 999                         ret = connector_status_connected;
1000                         broken_edid = true; /* defer use_digital to later */
1001                 } else {
1002                         amdgpu_connector->use_digital =
1003                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1004
1005                         /* some oems have boards with separate digital and analog connectors
1006                          * with a shared ddc line (often vga + hdmi)
1007                          */
1008                         if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1009                                 amdgpu_connector_free_edid(connector);
1010                                 ret = connector_status_disconnected;
1011                         } else {
1012                                 ret = connector_status_connected;
1013                         }
1014
1015                         /* This gets complicated.  We have boards with VGA + HDMI with a
1016                          * shared DDC line and we have boards with DVI-D + HDMI with a shared
1017                          * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1018                          * you don't really know what's connected to which port as both are digital.
1019                          */
1020                         if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1021                                 struct drm_connector *list_connector;
1022                                 struct drm_connector_list_iter iter;
1023                                 struct amdgpu_connector *list_amdgpu_connector;
1024
1025                                 drm_connector_list_iter_begin(dev, &iter);
1026                                 drm_for_each_connector_iter(list_connector,
1027                                                             &iter) {
1028                                         if (connector == list_connector)
1029                                                 continue;
1030                                         list_amdgpu_connector = to_amdgpu_connector(list_connector);
1031                                         if (list_amdgpu_connector->shared_ddc &&
1032                                             (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1033                                              amdgpu_connector->ddc_bus->rec.i2c_id)) {
1034                                                 /* cases where both connectors are digital */
1035                                                 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1036                                                         /* hpd is our only option in this case */
1037                                                         if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1038                                                                 amdgpu_connector_free_edid(connector);
1039                                                                 ret = connector_status_disconnected;
1040                                                         }
1041                                                 }
1042                                         }
1043                                 }
1044                                 drm_connector_list_iter_end(&iter);
1045                         }
1046                 }
1047         }
1048
1049         if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1050                 goto out;
1051
1052         /* DVI-D and HDMI-A are digital only */
1053         if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1054             (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1055                 goto out;
1056
1057         /* if we aren't forcing don't do destructive polling */
1058         if (!force) {
1059                 /* only return the previous status if we last
1060                  * detected a monitor via load.
1061                  */
1062                 if (amdgpu_connector->detected_by_load)
1063                         ret = connector->status;
1064                 goto out;
1065         }
1066
1067         /* find analog encoder */
1068         if (amdgpu_connector->dac_load_detect) {
1069                 struct drm_encoder *encoder;
1070
1071                 drm_connector_for_each_possible_encoder(connector, encoder) {
1072                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1073                             encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1074                                 continue;
1075
1076                         encoder_funcs = encoder->helper_private;
1077                         if (encoder_funcs->detect) {
1078                                 if (!broken_edid) {
1079                                         if (ret != connector_status_connected) {
1080                                                 /* deal with analog monitors without DDC */
1081                                                 ret = encoder_funcs->detect(encoder, connector);
1082                                                 if (ret == connector_status_connected) {
1083                                                         amdgpu_connector->use_digital = false;
1084                                                 }
1085                                                 if (ret != connector_status_disconnected)
1086                                                         amdgpu_connector->detected_by_load = true;
1087                                         }
1088                                 } else {
1089                                         enum drm_connector_status lret;
1090                                         /* assume digital unless load detected otherwise */
1091                                         amdgpu_connector->use_digital = true;
1092                                         lret = encoder_funcs->detect(encoder, connector);
1093                                         DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1094                                         if (lret == connector_status_connected)
1095                                                 amdgpu_connector->use_digital = false;
1096                                 }
1097                                 break;
1098                         }
1099                 }
1100         }
1101
1102 out:
1103         /* updated in get modes as well since we need to know if it's analog or digital */
1104         amdgpu_connector_update_scratch_regs(connector, ret);
1105
1106 exit:
1107         if (!drm_kms_helper_is_poll_worker()) {
1108                 pm_runtime_mark_last_busy(connector->dev->dev);
1109                 pm_runtime_put_autosuspend(connector->dev->dev);
1110         }
1111
1112         return ret;
1113 }
1114
1115 /* okay need to be smart in here about which encoder to pick */
1116 static struct drm_encoder *
1117 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1118 {
1119         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1120         struct drm_encoder *encoder;
1121
1122         drm_connector_for_each_possible_encoder(connector, encoder) {
1123                 if (amdgpu_connector->use_digital == true) {
1124                         if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1125                                 return encoder;
1126                 } else {
1127                         if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1128                             encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1129                                 return encoder;
1130                 }
1131         }
1132
1133         /* see if we have a default encoder  TODO */
1134
1135         /* then check use digitial */
1136         /* pick the first one */
1137         drm_connector_for_each_possible_encoder(connector, encoder)
1138                 return encoder;
1139
1140         return NULL;
1141 }
1142
1143 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1144 {
1145         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1146         if (connector->force == DRM_FORCE_ON)
1147                 amdgpu_connector->use_digital = false;
1148         if (connector->force == DRM_FORCE_ON_DIGITAL)
1149                 amdgpu_connector->use_digital = true;
1150 }
1151
1152 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1153                                             struct drm_display_mode *mode)
1154 {
1155         struct drm_device *dev = connector->dev;
1156         struct amdgpu_device *adev = dev->dev_private;
1157         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1158
1159         /* XXX check mode bandwidth */
1160
1161         if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1162                 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1163                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1164                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1165                         return MODE_OK;
1166                 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1167                         /* HDMI 1.3+ supports max clock of 340 Mhz */
1168                         if (mode->clock > 340000)
1169                                 return MODE_CLOCK_HIGH;
1170                         else
1171                                 return MODE_OK;
1172                 } else {
1173                         return MODE_CLOCK_HIGH;
1174                 }
1175         }
1176
1177         /* check against the max pixel clock */
1178         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1179                 return MODE_CLOCK_HIGH;
1180
1181         return MODE_OK;
1182 }
1183
1184 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1185         .get_modes = amdgpu_connector_vga_get_modes,
1186         .mode_valid = amdgpu_connector_dvi_mode_valid,
1187         .best_encoder = amdgpu_connector_dvi_encoder,
1188 };
1189
1190 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1191         .dpms = drm_helper_connector_dpms,
1192         .detect = amdgpu_connector_dvi_detect,
1193         .fill_modes = drm_helper_probe_single_connector_modes,
1194         .set_property = amdgpu_connector_set_property,
1195         .early_unregister = amdgpu_connector_unregister,
1196         .destroy = amdgpu_connector_destroy,
1197         .force = amdgpu_connector_dvi_force,
1198 };
1199
1200 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1201 {
1202         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1203         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1204         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1205         int ret;
1206
1207         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1208             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1209                 struct drm_display_mode *mode;
1210
1211                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1212                         if (!amdgpu_dig_connector->edp_on)
1213                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1214                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1215                         amdgpu_connector_get_edid(connector);
1216                         ret = amdgpu_connector_ddc_get_modes(connector);
1217                         if (!amdgpu_dig_connector->edp_on)
1218                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1219                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1220                 } else {
1221                         /* need to setup ddc on the bridge */
1222                         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1223                             ENCODER_OBJECT_ID_NONE) {
1224                                 if (encoder)
1225                                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1226                         }
1227                         amdgpu_connector_get_edid(connector);
1228                         ret = amdgpu_connector_ddc_get_modes(connector);
1229                 }
1230
1231                 if (ret > 0) {
1232                         if (encoder) {
1233                                 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1234                                 /* add scaled modes */
1235                                 amdgpu_connector_add_common_modes(encoder, connector);
1236                         }
1237                         return ret;
1238                 }
1239
1240                 if (!encoder)
1241                         return 0;
1242
1243                 /* we have no EDID modes */
1244                 mode = amdgpu_connector_lcd_native_mode(encoder);
1245                 if (mode) {
1246                         ret = 1;
1247                         drm_mode_probed_add(connector, mode);
1248                         /* add the width/height from vbios tables if available */
1249                         connector->display_info.width_mm = mode->width_mm;
1250                         connector->display_info.height_mm = mode->height_mm;
1251                         /* add scaled modes */
1252                         amdgpu_connector_add_common_modes(encoder, connector);
1253                 }
1254         } else {
1255                 /* need to setup ddc on the bridge */
1256                 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1257                         ENCODER_OBJECT_ID_NONE) {
1258                         if (encoder)
1259                                 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1260                 }
1261                 amdgpu_connector_get_edid(connector);
1262                 ret = amdgpu_connector_ddc_get_modes(connector);
1263
1264                 amdgpu_get_native_mode(connector);
1265         }
1266
1267         return ret;
1268 }
1269
1270 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1271 {
1272         struct drm_encoder *encoder;
1273         struct amdgpu_encoder *amdgpu_encoder;
1274
1275         drm_connector_for_each_possible_encoder(connector, encoder) {
1276                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1277
1278                 switch (amdgpu_encoder->encoder_id) {
1279                 case ENCODER_OBJECT_ID_TRAVIS:
1280                 case ENCODER_OBJECT_ID_NUTMEG:
1281                         return amdgpu_encoder->encoder_id;
1282                 default:
1283                         break;
1284                 }
1285         }
1286
1287         return ENCODER_OBJECT_ID_NONE;
1288 }
1289
1290 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1291 {
1292         struct drm_encoder *encoder;
1293         struct amdgpu_encoder *amdgpu_encoder;
1294         bool found = false;
1295
1296         drm_connector_for_each_possible_encoder(connector, encoder) {
1297                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1298                 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1299                         found = true;
1300         }
1301
1302         return found;
1303 }
1304
1305 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1306 {
1307         struct drm_device *dev = connector->dev;
1308         struct amdgpu_device *adev = dev->dev_private;
1309
1310         if ((adev->clock.default_dispclk >= 53900) &&
1311             amdgpu_connector_encoder_is_hbr2(connector)) {
1312                 return true;
1313         }
1314
1315         return false;
1316 }
1317
1318 static enum drm_connector_status
1319 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1320 {
1321         struct drm_device *dev = connector->dev;
1322         struct amdgpu_device *adev = dev->dev_private;
1323         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1324         enum drm_connector_status ret = connector_status_disconnected;
1325         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1326         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1327         int r;
1328
1329         if (!drm_kms_helper_is_poll_worker()) {
1330                 r = pm_runtime_get_sync(connector->dev->dev);
1331                 if (r < 0)
1332                         return connector_status_disconnected;
1333         }
1334
1335         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1336                 ret = connector->status;
1337                 goto out;
1338         }
1339
1340         amdgpu_connector_free_edid(connector);
1341
1342         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1343             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1344                 if (encoder) {
1345                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1346                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1347
1348                         /* check if panel is valid */
1349                         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1350                                 ret = connector_status_connected;
1351                 }
1352                 /* eDP is always DP */
1353                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1354                 if (!amdgpu_dig_connector->edp_on)
1355                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1356                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1357                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1358                         ret = connector_status_connected;
1359                 if (!amdgpu_dig_connector->edp_on)
1360                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1361                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1362         } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1363                    ENCODER_OBJECT_ID_NONE) {
1364                 /* DP bridges are always DP */
1365                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1366                 /* get the DPCD from the bridge */
1367                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1368
1369                 if (encoder) {
1370                         /* setup ddc on the bridge */
1371                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1372                         /* bridge chips are always aux */
1373                         /* try DDC */
1374                         if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1375                                 ret = connector_status_connected;
1376                         else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1377                                 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1378                                 ret = encoder_funcs->detect(encoder, connector);
1379                         }
1380                 }
1381         } else {
1382                 amdgpu_dig_connector->dp_sink_type =
1383                         amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1384                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1385                         ret = connector_status_connected;
1386                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1387                                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1388                 } else {
1389                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1390                                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1391                                         ret = connector_status_connected;
1392                         } else {
1393                                 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1394                                 if (amdgpu_display_ddc_probe(amdgpu_connector,
1395                                                              false))
1396                                         ret = connector_status_connected;
1397                         }
1398                 }
1399         }
1400
1401         amdgpu_connector_update_scratch_regs(connector, ret);
1402 out:
1403         if (!drm_kms_helper_is_poll_worker()) {
1404                 pm_runtime_mark_last_busy(connector->dev->dev);
1405                 pm_runtime_put_autosuspend(connector->dev->dev);
1406         }
1407
1408         return ret;
1409 }
1410
1411 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1412                                            struct drm_display_mode *mode)
1413 {
1414         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1415         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1416
1417         /* XXX check mode bandwidth */
1418
1419         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1420             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1421                 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1422
1423                 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1424                         return MODE_PANEL;
1425
1426                 if (encoder) {
1427                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1428                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1429
1430                         /* AVIVO hardware supports downscaling modes larger than the panel
1431                          * to the panel size, but I'm not sure this is desirable.
1432                          */
1433                         if ((mode->hdisplay > native_mode->hdisplay) ||
1434                             (mode->vdisplay > native_mode->vdisplay))
1435                                 return MODE_PANEL;
1436
1437                         /* if scaling is disabled, block non-native modes */
1438                         if (amdgpu_encoder->rmx_type == RMX_OFF) {
1439                                 if ((mode->hdisplay != native_mode->hdisplay) ||
1440                                     (mode->vdisplay != native_mode->vdisplay))
1441                                         return MODE_PANEL;
1442                         }
1443                 }
1444                 return MODE_OK;
1445         } else {
1446                 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1447                     (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1448                         return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1449                 } else {
1450                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1451                                 /* HDMI 1.3+ supports max clock of 340 Mhz */
1452                                 if (mode->clock > 340000)
1453                                         return MODE_CLOCK_HIGH;
1454                         } else {
1455                                 if (mode->clock > 165000)
1456                                         return MODE_CLOCK_HIGH;
1457                         }
1458                 }
1459         }
1460
1461         return MODE_OK;
1462 }
1463
1464 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1465         .get_modes = amdgpu_connector_dp_get_modes,
1466         .mode_valid = amdgpu_connector_dp_mode_valid,
1467         .best_encoder = amdgpu_connector_dvi_encoder,
1468 };
1469
1470 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1471         .dpms = drm_helper_connector_dpms,
1472         .detect = amdgpu_connector_dp_detect,
1473         .fill_modes = drm_helper_probe_single_connector_modes,
1474         .set_property = amdgpu_connector_set_property,
1475         .early_unregister = amdgpu_connector_unregister,
1476         .destroy = amdgpu_connector_destroy,
1477         .force = amdgpu_connector_dvi_force,
1478 };
1479
1480 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1481         .dpms = drm_helper_connector_dpms,
1482         .detect = amdgpu_connector_dp_detect,
1483         .fill_modes = drm_helper_probe_single_connector_modes,
1484         .set_property = amdgpu_connector_set_lcd_property,
1485         .early_unregister = amdgpu_connector_unregister,
1486         .destroy = amdgpu_connector_destroy,
1487         .force = amdgpu_connector_dvi_force,
1488 };
1489
1490 void
1491 amdgpu_connector_add(struct amdgpu_device *adev,
1492                       uint32_t connector_id,
1493                       uint32_t supported_device,
1494                       int connector_type,
1495                       struct amdgpu_i2c_bus_rec *i2c_bus,
1496                       uint16_t connector_object_id,
1497                       struct amdgpu_hpd *hpd,
1498                       struct amdgpu_router *router)
1499 {
1500         struct drm_device *dev = adev->ddev;
1501         struct drm_connector *connector;
1502         struct drm_connector_list_iter iter;
1503         struct amdgpu_connector *amdgpu_connector;
1504         struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1505         struct drm_encoder *encoder;
1506         struct amdgpu_encoder *amdgpu_encoder;
1507         struct i2c_adapter *ddc = NULL;
1508         uint32_t subpixel_order = SubPixelNone;
1509         bool shared_ddc = false;
1510         bool is_dp_bridge = false;
1511         bool has_aux = false;
1512
1513         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1514                 return;
1515
1516         /* see if we already added it */
1517         drm_connector_list_iter_begin(dev, &iter);
1518         drm_for_each_connector_iter(connector, &iter) {
1519                 amdgpu_connector = to_amdgpu_connector(connector);
1520                 if (amdgpu_connector->connector_id == connector_id) {
1521                         amdgpu_connector->devices |= supported_device;
1522                         drm_connector_list_iter_end(&iter);
1523                         return;
1524                 }
1525                 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1526                         if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1527                                 amdgpu_connector->shared_ddc = true;
1528                                 shared_ddc = true;
1529                         }
1530                         if (amdgpu_connector->router_bus && router->ddc_valid &&
1531                             (amdgpu_connector->router.router_id == router->router_id)) {
1532                                 amdgpu_connector->shared_ddc = false;
1533                                 shared_ddc = false;
1534                         }
1535                 }
1536         }
1537         drm_connector_list_iter_end(&iter);
1538
1539         /* check if it's a dp bridge */
1540         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1541                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1542                 if (amdgpu_encoder->devices & supported_device) {
1543                         switch (amdgpu_encoder->encoder_id) {
1544                         case ENCODER_OBJECT_ID_TRAVIS:
1545                         case ENCODER_OBJECT_ID_NUTMEG:
1546                                 is_dp_bridge = true;
1547                                 break;
1548                         default:
1549                                 break;
1550                         }
1551                 }
1552         }
1553
1554         amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1555         if (!amdgpu_connector)
1556                 return;
1557
1558         connector = &amdgpu_connector->base;
1559
1560         amdgpu_connector->connector_id = connector_id;
1561         amdgpu_connector->devices = supported_device;
1562         amdgpu_connector->shared_ddc = shared_ddc;
1563         amdgpu_connector->connector_object_id = connector_object_id;
1564         amdgpu_connector->hpd = *hpd;
1565
1566         amdgpu_connector->router = *router;
1567         if (router->ddc_valid || router->cd_valid) {
1568                 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1569                 if (!amdgpu_connector->router_bus)
1570                         DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1571         }
1572
1573         if (is_dp_bridge) {
1574                 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1575                 if (!amdgpu_dig_connector)
1576                         goto failed;
1577                 amdgpu_connector->con_priv = amdgpu_dig_connector;
1578                 if (i2c_bus->valid) {
1579                         amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1580                         if (amdgpu_connector->ddc_bus) {
1581                                 has_aux = true;
1582                                 ddc = &amdgpu_connector->ddc_bus->adapter;
1583                         } else {
1584                                 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1585                         }
1586                 }
1587                 switch (connector_type) {
1588                 case DRM_MODE_CONNECTOR_VGA:
1589                 case DRM_MODE_CONNECTOR_DVIA:
1590                 default:
1591                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1592                                                     &amdgpu_connector_dp_funcs,
1593                                                     connector_type,
1594                                                     ddc);
1595                         drm_connector_helper_add(&amdgpu_connector->base,
1596                                                  &amdgpu_connector_dp_helper_funcs);
1597                         connector->interlace_allowed = true;
1598                         connector->doublescan_allowed = true;
1599                         amdgpu_connector->dac_load_detect = true;
1600                         drm_object_attach_property(&amdgpu_connector->base.base,
1601                                                       adev->mode_info.load_detect_property,
1602                                                       1);
1603                         drm_object_attach_property(&amdgpu_connector->base.base,
1604                                                    dev->mode_config.scaling_mode_property,
1605                                                    DRM_MODE_SCALE_NONE);
1606                         break;
1607                 case DRM_MODE_CONNECTOR_DVII:
1608                 case DRM_MODE_CONNECTOR_DVID:
1609                 case DRM_MODE_CONNECTOR_HDMIA:
1610                 case DRM_MODE_CONNECTOR_HDMIB:
1611                 case DRM_MODE_CONNECTOR_DisplayPort:
1612                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1613                                                     &amdgpu_connector_dp_funcs,
1614                                                     connector_type,
1615                                                     ddc);
1616                         drm_connector_helper_add(&amdgpu_connector->base,
1617                                                  &amdgpu_connector_dp_helper_funcs);
1618                         drm_object_attach_property(&amdgpu_connector->base.base,
1619                                                       adev->mode_info.underscan_property,
1620                                                       UNDERSCAN_OFF);
1621                         drm_object_attach_property(&amdgpu_connector->base.base,
1622                                                       adev->mode_info.underscan_hborder_property,
1623                                                       0);
1624                         drm_object_attach_property(&amdgpu_connector->base.base,
1625                                                       adev->mode_info.underscan_vborder_property,
1626                                                       0);
1627
1628                         drm_object_attach_property(&amdgpu_connector->base.base,
1629                                                    dev->mode_config.scaling_mode_property,
1630                                                    DRM_MODE_SCALE_NONE);
1631
1632                         drm_object_attach_property(&amdgpu_connector->base.base,
1633                                                    adev->mode_info.dither_property,
1634                                                    AMDGPU_FMT_DITHER_DISABLE);
1635
1636                         if (amdgpu_audio != 0)
1637                                 drm_object_attach_property(&amdgpu_connector->base.base,
1638                                                            adev->mode_info.audio_property,
1639                                                            AMDGPU_AUDIO_AUTO);
1640
1641                         subpixel_order = SubPixelHorizontalRGB;
1642                         connector->interlace_allowed = true;
1643                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1644                                 connector->doublescan_allowed = true;
1645                         else
1646                                 connector->doublescan_allowed = false;
1647                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1648                                 amdgpu_connector->dac_load_detect = true;
1649                                 drm_object_attach_property(&amdgpu_connector->base.base,
1650                                                               adev->mode_info.load_detect_property,
1651                                                               1);
1652                         }
1653                         break;
1654                 case DRM_MODE_CONNECTOR_LVDS:
1655                 case DRM_MODE_CONNECTOR_eDP:
1656                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1657                                                     &amdgpu_connector_edp_funcs,
1658                                                     connector_type,
1659                                                     ddc);
1660                         drm_connector_helper_add(&amdgpu_connector->base,
1661                                                  &amdgpu_connector_dp_helper_funcs);
1662                         drm_object_attach_property(&amdgpu_connector->base.base,
1663                                                       dev->mode_config.scaling_mode_property,
1664                                                       DRM_MODE_SCALE_FULLSCREEN);
1665                         subpixel_order = SubPixelHorizontalRGB;
1666                         connector->interlace_allowed = false;
1667                         connector->doublescan_allowed = false;
1668                         break;
1669                 }
1670         } else {
1671                 switch (connector_type) {
1672                 case DRM_MODE_CONNECTOR_VGA:
1673                         if (i2c_bus->valid) {
1674                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1675                                 if (!amdgpu_connector->ddc_bus)
1676                                         DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1677                                 else
1678                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1679                         }
1680                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1681                                                     &amdgpu_connector_vga_funcs,
1682                                                     connector_type,
1683                                                     ddc);
1684                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1685                         amdgpu_connector->dac_load_detect = true;
1686                         drm_object_attach_property(&amdgpu_connector->base.base,
1687                                                       adev->mode_info.load_detect_property,
1688                                                       1);
1689                         drm_object_attach_property(&amdgpu_connector->base.base,
1690                                                    dev->mode_config.scaling_mode_property,
1691                                                    DRM_MODE_SCALE_NONE);
1692                         /* no HPD on analog connectors */
1693                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1694                         connector->interlace_allowed = true;
1695                         connector->doublescan_allowed = true;
1696                         break;
1697                 case DRM_MODE_CONNECTOR_DVIA:
1698                         if (i2c_bus->valid) {
1699                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1700                                 if (!amdgpu_connector->ddc_bus)
1701                                         DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1702                                 else
1703                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1704                         }
1705                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1706                                                     &amdgpu_connector_vga_funcs,
1707                                                     connector_type,
1708                                                     ddc);
1709                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1710                         amdgpu_connector->dac_load_detect = true;
1711                         drm_object_attach_property(&amdgpu_connector->base.base,
1712                                                       adev->mode_info.load_detect_property,
1713                                                       1);
1714                         drm_object_attach_property(&amdgpu_connector->base.base,
1715                                                    dev->mode_config.scaling_mode_property,
1716                                                    DRM_MODE_SCALE_NONE);
1717                         /* no HPD on analog connectors */
1718                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1719                         connector->interlace_allowed = true;
1720                         connector->doublescan_allowed = true;
1721                         break;
1722                 case DRM_MODE_CONNECTOR_DVII:
1723                 case DRM_MODE_CONNECTOR_DVID:
1724                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1725                         if (!amdgpu_dig_connector)
1726                                 goto failed;
1727                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1728                         if (i2c_bus->valid) {
1729                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1730                                 if (!amdgpu_connector->ddc_bus)
1731                                         DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1732                                 else
1733                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1734                         }
1735                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1736                                                     &amdgpu_connector_dvi_funcs,
1737                                                     connector_type,
1738                                                     ddc);
1739                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1740                         subpixel_order = SubPixelHorizontalRGB;
1741                         drm_object_attach_property(&amdgpu_connector->base.base,
1742                                                       adev->mode_info.coherent_mode_property,
1743                                                       1);
1744                         drm_object_attach_property(&amdgpu_connector->base.base,
1745                                                    adev->mode_info.underscan_property,
1746                                                    UNDERSCAN_OFF);
1747                         drm_object_attach_property(&amdgpu_connector->base.base,
1748                                                    adev->mode_info.underscan_hborder_property,
1749                                                    0);
1750                         drm_object_attach_property(&amdgpu_connector->base.base,
1751                                                    adev->mode_info.underscan_vborder_property,
1752                                                    0);
1753                         drm_object_attach_property(&amdgpu_connector->base.base,
1754                                                    dev->mode_config.scaling_mode_property,
1755                                                    DRM_MODE_SCALE_NONE);
1756
1757                         if (amdgpu_audio != 0) {
1758                                 drm_object_attach_property(&amdgpu_connector->base.base,
1759                                                            adev->mode_info.audio_property,
1760                                                            AMDGPU_AUDIO_AUTO);
1761                         }
1762                         drm_object_attach_property(&amdgpu_connector->base.base,
1763                                                    adev->mode_info.dither_property,
1764                                                    AMDGPU_FMT_DITHER_DISABLE);
1765                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1766                                 amdgpu_connector->dac_load_detect = true;
1767                                 drm_object_attach_property(&amdgpu_connector->base.base,
1768                                                            adev->mode_info.load_detect_property,
1769                                                            1);
1770                         }
1771                         connector->interlace_allowed = true;
1772                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
1773                                 connector->doublescan_allowed = true;
1774                         else
1775                                 connector->doublescan_allowed = false;
1776                         break;
1777                 case DRM_MODE_CONNECTOR_HDMIA:
1778                 case DRM_MODE_CONNECTOR_HDMIB:
1779                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1780                         if (!amdgpu_dig_connector)
1781                                 goto failed;
1782                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1783                         if (i2c_bus->valid) {
1784                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1785                                 if (!amdgpu_connector->ddc_bus)
1786                                         DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1787                                 else
1788                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1789                         }
1790                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1791                                                     &amdgpu_connector_dvi_funcs,
1792                                                     connector_type,
1793                                                     ddc);
1794                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1795                         drm_object_attach_property(&amdgpu_connector->base.base,
1796                                                       adev->mode_info.coherent_mode_property,
1797                                                       1);
1798                         drm_object_attach_property(&amdgpu_connector->base.base,
1799                                                    adev->mode_info.underscan_property,
1800                                                    UNDERSCAN_OFF);
1801                         drm_object_attach_property(&amdgpu_connector->base.base,
1802                                                    adev->mode_info.underscan_hborder_property,
1803                                                    0);
1804                         drm_object_attach_property(&amdgpu_connector->base.base,
1805                                                    adev->mode_info.underscan_vborder_property,
1806                                                    0);
1807                         drm_object_attach_property(&amdgpu_connector->base.base,
1808                                                    dev->mode_config.scaling_mode_property,
1809                                                    DRM_MODE_SCALE_NONE);
1810                         if (amdgpu_audio != 0) {
1811                                 drm_object_attach_property(&amdgpu_connector->base.base,
1812                                                            adev->mode_info.audio_property,
1813                                                            AMDGPU_AUDIO_AUTO);
1814                         }
1815                         drm_object_attach_property(&amdgpu_connector->base.base,
1816                                                    adev->mode_info.dither_property,
1817                                                    AMDGPU_FMT_DITHER_DISABLE);
1818                         subpixel_order = SubPixelHorizontalRGB;
1819                         connector->interlace_allowed = true;
1820                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1821                                 connector->doublescan_allowed = true;
1822                         else
1823                                 connector->doublescan_allowed = false;
1824                         break;
1825                 case DRM_MODE_CONNECTOR_DisplayPort:
1826                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1827                         if (!amdgpu_dig_connector)
1828                                 goto failed;
1829                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1830                         if (i2c_bus->valid) {
1831                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1832                                 if (amdgpu_connector->ddc_bus) {
1833                                         has_aux = true;
1834                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1835                                 } else {
1836                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1837                                 }
1838                         }
1839                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1840                                                     &amdgpu_connector_dp_funcs,
1841                                                     connector_type,
1842                                                     ddc);
1843                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1844                         subpixel_order = SubPixelHorizontalRGB;
1845                         drm_object_attach_property(&amdgpu_connector->base.base,
1846                                                       adev->mode_info.coherent_mode_property,
1847                                                       1);
1848                         drm_object_attach_property(&amdgpu_connector->base.base,
1849                                                    adev->mode_info.underscan_property,
1850                                                    UNDERSCAN_OFF);
1851                         drm_object_attach_property(&amdgpu_connector->base.base,
1852                                                    adev->mode_info.underscan_hborder_property,
1853                                                    0);
1854                         drm_object_attach_property(&amdgpu_connector->base.base,
1855                                                    adev->mode_info.underscan_vborder_property,
1856                                                    0);
1857                         drm_object_attach_property(&amdgpu_connector->base.base,
1858                                                    dev->mode_config.scaling_mode_property,
1859                                                    DRM_MODE_SCALE_NONE);
1860                         if (amdgpu_audio != 0) {
1861                                 drm_object_attach_property(&amdgpu_connector->base.base,
1862                                                            adev->mode_info.audio_property,
1863                                                            AMDGPU_AUDIO_AUTO);
1864                         }
1865                         drm_object_attach_property(&amdgpu_connector->base.base,
1866                                                    adev->mode_info.dither_property,
1867                                                    AMDGPU_FMT_DITHER_DISABLE);
1868                         connector->interlace_allowed = true;
1869                         /* in theory with a DP to VGA converter... */
1870                         connector->doublescan_allowed = false;
1871                         break;
1872                 case DRM_MODE_CONNECTOR_eDP:
1873                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1874                         if (!amdgpu_dig_connector)
1875                                 goto failed;
1876                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1877                         if (i2c_bus->valid) {
1878                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1879                                 if (amdgpu_connector->ddc_bus) {
1880                                         has_aux = true;
1881                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1882                                 } else {
1883                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1884                                 }
1885                         }
1886                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1887                                                     &amdgpu_connector_edp_funcs,
1888                                                     connector_type,
1889                                                     ddc);
1890                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1891                         drm_object_attach_property(&amdgpu_connector->base.base,
1892                                                       dev->mode_config.scaling_mode_property,
1893                                                       DRM_MODE_SCALE_FULLSCREEN);
1894                         subpixel_order = SubPixelHorizontalRGB;
1895                         connector->interlace_allowed = false;
1896                         connector->doublescan_allowed = false;
1897                         break;
1898                 case DRM_MODE_CONNECTOR_LVDS:
1899                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1900                         if (!amdgpu_dig_connector)
1901                                 goto failed;
1902                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1903                         if (i2c_bus->valid) {
1904                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1905                                 if (!amdgpu_connector->ddc_bus)
1906                                         DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1907                                 else
1908                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1909                         }
1910                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1911                                                     &amdgpu_connector_lvds_funcs,
1912                                                     connector_type,
1913                                                     ddc);
1914                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1915                         drm_object_attach_property(&amdgpu_connector->base.base,
1916                                                       dev->mode_config.scaling_mode_property,
1917                                                       DRM_MODE_SCALE_FULLSCREEN);
1918                         subpixel_order = SubPixelHorizontalRGB;
1919                         connector->interlace_allowed = false;
1920                         connector->doublescan_allowed = false;
1921                         break;
1922                 }
1923         }
1924
1925         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1926                 if (i2c_bus->valid) {
1927                         connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1928                                             DRM_CONNECTOR_POLL_DISCONNECT;
1929                 }
1930         } else
1931                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1932
1933         connector->display_info.subpixel_order = subpixel_order;
1934         drm_connector_register(connector);
1935
1936         if (has_aux)
1937                 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1938
1939         return;
1940
1941 failed:
1942         drm_connector_cleanup(connector);
1943         kfree(connector);
1944 }