drivers/gpu/drm/amd/amdgpu/amdgpu_df.h

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_DF_H__
  25 #define __AMDGPU_DF_H__
  26
  27 struct amdgpu_df_hash_status {
  28         bool hash_64k;
  29         bool hash_2m;
  30         bool hash_1g;
  31 };
  32
  33 struct amdgpu_df_funcs {
  34         void (*sw_init)(struct amdgpu_device *adev);
  35         void (*sw_fini)(struct amdgpu_device *adev);
  36         void (*enable_broadcast_mode)(struct amdgpu_device *adev,
  37                                       bool enable);
  38         u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
  39         u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
  40         void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
  41                                                  bool enable);
  42         void (*get_clockgating_state)(struct amdgpu_device *adev,
  43                                       u32 *flags);
  44         void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
  45                                             bool enable);
  46         int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
  47                                          int is_enable);
  48         int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
  49                                          int is_disable);
  50         void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
  51                                          uint64_t *count);
  52         uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
  53         void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
  54                          uint32_t ficadl_val, uint32_t ficadh_val);
  55 };
  56
  57 struct amdgpu_df {
  58         struct amdgpu_df_hash_status    hash_status;
  59         const struct amdgpu_df_funcs    *funcs;
  60 };
  61
  62 #endif /* __AMDGPU_DF_H__ */