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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_display.c
blob6d520a3eec4090732ae62d91eaa6cd5a1babc9f7
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_i2c.h"
30 #include "atom.h"
31 #include "amdgpu_connectors.h"
32 #include "amdgpu_display.h"
33 #include <asm/div64.h>
34
35 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <drm/drm_crtc_helper.h>
38 #include <drm/drm_edid.h>
39 #include <drm/drm_gem_framebuffer_helper.h>
40 #include <drm/drm_fb_helper.h>
41 #include <drm/drm_vblank.h>
42
43 static void amdgpu_display_flip_callback(struct dma_fence *f,
44 struct dma_fence_cb *cb)
45 {
46 struct amdgpu_flip_work *work =
47 container_of(cb, struct amdgpu_flip_work, cb);
48
49 dma_fence_put(f);
50 schedule_work(&work->flip_work.work);
51 }
52
53 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
54 struct dma_fence **f)
55 {
56 struct dma_fence *fence= *f;
57
58 if (fence == NULL)
59 return false;
60
61 *f = NULL;
62
63 if (!dma_fence_add_callback(fence, &work->cb,
64 amdgpu_display_flip_callback))
65 return true;
66
67 dma_fence_put(fence);
68 return false;
69 }
70
71 static void amdgpu_display_flip_work_func(struct work_struct *__work)
72 {
73 struct delayed_work *delayed_work =
74 container_of(__work, struct delayed_work, work);
75 struct amdgpu_flip_work *work =
76 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
77 struct amdgpu_device *adev = work->adev;
78 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
79
80 struct drm_crtc *crtc = &amdgpu_crtc->base;
81 unsigned long flags;
82 unsigned i;
83 int vpos, hpos;
84
85 if (amdgpu_display_flip_handle_fence(work, &work->excl))
86 return;
87
88 for (i = 0; i < work->shared_count; ++i)
89 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
90 return;
91
92 /* Wait until we're out of the vertical blank period before the one
93 * targeted by the flip
94 */
95 if (amdgpu_crtc->enabled &&
96 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0,
97 &vpos, &hpos, NULL, NULL,
98 &crtc->hwmode)
99 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
100 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
101 (int)(work->target_vblank -
102 amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) {
103 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
104 return;
105 }
106
107 /* We borrow the event spin lock for protecting flip_status */
108 spin_lock_irqsave(&crtc->dev->event_lock, flags);
109
110 /* Do the flip (mmio) */
111 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
112
113 /* Set the flip status */
114 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
115 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
116
117
118 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
119 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
120
121 }
122
123 /*
124 * Handle unpin events outside the interrupt handler proper.
125 */
126 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
127 {
128 struct amdgpu_flip_work *work =
129 container_of(__work, struct amdgpu_flip_work, unpin_work);
130 int r;
131
132 /* unpin of the old buffer */
133 r = amdgpu_bo_reserve(work->old_abo, true);
134 if (likely(r == 0)) {
135 r = amdgpu_bo_unpin(work->old_abo);
136 if (unlikely(r != 0)) {
137 DRM_ERROR("failed to unpin buffer after flip\n");
138 }
139 amdgpu_bo_unreserve(work->old_abo);
140 } else
141 DRM_ERROR("failed to reserve buffer after flip\n");
142
143 amdgpu_bo_unref(&work->old_abo);
144 kfree(work->shared);
145 kfree(work);
146 }
147
148 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
149 struct drm_framebuffer *fb,
150 struct drm_pending_vblank_event *event,
151 uint32_t page_flip_flags, uint32_t target,
152 struct drm_modeset_acquire_ctx *ctx)
153 {
154 struct drm_device *dev = crtc->dev;
155 struct amdgpu_device *adev = dev->dev_private;
156 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
157 struct drm_gem_object *obj;
158 struct amdgpu_flip_work *work;
159 struct amdgpu_bo *new_abo;
160 unsigned long flags;
161 u64 tiling_flags;
162 int i, r;
163
164 work = kzalloc(sizeof *work, GFP_KERNEL);
165 if (work == NULL)
166 return -ENOMEM;
167
168 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
169 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
170
171 work->event = event;
172 work->adev = adev;
173 work->crtc_id = amdgpu_crtc->crtc_id;
174 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
175
176 /* schedule unpin of the old buffer */
177 obj = crtc->primary->fb->obj[0];
178
179 /* take a reference to the old object */
180 work->old_abo = gem_to_amdgpu_bo(obj);
181 amdgpu_bo_ref(work->old_abo);
182
183 obj = fb->obj[0];
184 new_abo = gem_to_amdgpu_bo(obj);
185
186 /* pin the new buffer */
187 r = amdgpu_bo_reserve(new_abo, false);
188 if (unlikely(r != 0)) {
189 DRM_ERROR("failed to reserve new abo buffer before flip\n");
190 goto cleanup;
191 }
192
193 if (!adev->enable_virtual_display) {
194 r = amdgpu_bo_pin(new_abo,
195 amdgpu_display_supported_domains(adev, new_abo->flags));
196 if (unlikely(r != 0)) {
197 DRM_ERROR("failed to pin new abo buffer before flip\n");
198 goto unreserve;
199 }
200 }
201
202 r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
203 if (unlikely(r != 0)) {
204 DRM_ERROR("%p bind failed\n", new_abo);
205 goto unpin;
206 }
207
208 r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl,
209 &work->shared_count,
210 &work->shared);
211 if (unlikely(r != 0)) {
212 DRM_ERROR("failed to get fences for buffer\n");
213 goto unpin;
214 }
215
216 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
217 amdgpu_bo_unreserve(new_abo);
218
219 if (!adev->enable_virtual_display)
220 work->base = amdgpu_bo_gpu_offset(new_abo);
221 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
222 amdgpu_get_vblank_counter_kms(dev, work->crtc_id);
223
224 /* we borrow the event spin lock for protecting flip_wrok */
225 spin_lock_irqsave(&crtc->dev->event_lock, flags);
226 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
227 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
228 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
229 r = -EBUSY;
230 goto pflip_cleanup;
231 }
232
233 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
234 amdgpu_crtc->pflip_works = work;
235
236
237 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
238 amdgpu_crtc->crtc_id, amdgpu_crtc, work);
239 /* update crtc fb */
240 crtc->primary->fb = fb;
241 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
242 amdgpu_display_flip_work_func(&work->flip_work.work);
243 return 0;
244
245 pflip_cleanup:
246 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
247 DRM_ERROR("failed to reserve new abo in error path\n");
248 goto cleanup;
249 }
250 unpin:
251 if (!adev->enable_virtual_display)
252 if (unlikely(amdgpu_bo_unpin(new_abo) != 0))
253 DRM_ERROR("failed to unpin new abo in error path\n");
254
255 unreserve:
256 amdgpu_bo_unreserve(new_abo);
257
258 cleanup:
259 amdgpu_bo_unref(&work->old_abo);
260 dma_fence_put(work->excl);
261 for (i = 0; i < work->shared_count; ++i)
262 dma_fence_put(work->shared[i]);
263 kfree(work->shared);
264 kfree(work);
265
266 return r;
267 }
268
269 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
270 struct drm_modeset_acquire_ctx *ctx)
271 {
272 struct drm_device *dev;
273 struct amdgpu_device *adev;
274 struct drm_crtc *crtc;
275 bool active = false;
276 int ret;
277
278 if (!set || !set->crtc)
279 return -EINVAL;
280
281 dev = set->crtc->dev;
282
283 ret = pm_runtime_get_sync(dev->dev);
284 if (ret < 0)
285 return ret;
286
287 ret = drm_crtc_helper_set_config(set, ctx);
288
289 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
290 if (crtc->enabled)
291 active = true;
292
293 pm_runtime_mark_last_busy(dev->dev);
294
295 adev = dev->dev_private;
296 /* if we have active crtcs and we don't have a power ref,
297 take the current one */
298 if (active && !adev->have_disp_power_ref) {
299 adev->have_disp_power_ref = true;
300 return ret;
301 }
302 /* if we have no active crtcs, then drop the power ref
303 we got before */
304 if (!active && adev->have_disp_power_ref) {
305 pm_runtime_put_autosuspend(dev->dev);
306 adev->have_disp_power_ref = false;
307 }
308
309 /* drop the power reference we got coming in here */
310 pm_runtime_put_autosuspend(dev->dev);
311 return ret;
312 }
313
314 static const char *encoder_names[41] = {
315 "NONE",
316 "INTERNAL_LVDS",
317 "INTERNAL_TMDS1",
318 "INTERNAL_TMDS2",
319 "INTERNAL_DAC1",
320 "INTERNAL_DAC2",
321 "INTERNAL_SDVOA",
322 "INTERNAL_SDVOB",
323 "SI170B",
324 "CH7303",
325 "CH7301",
326 "INTERNAL_DVO1",
327 "EXTERNAL_SDVOA",
328 "EXTERNAL_SDVOB",
329 "TITFP513",
330 "INTERNAL_LVTM1",
331 "VT1623",
332 "HDMI_SI1930",
333 "HDMI_INTERNAL",
334 "INTERNAL_KLDSCP_TMDS1",
335 "INTERNAL_KLDSCP_DVO1",
336 "INTERNAL_KLDSCP_DAC1",
337 "INTERNAL_KLDSCP_DAC2",
338 "SI178",
339 "MVPU_FPGA",
340 "INTERNAL_DDI",
341 "VT1625",
342 "HDMI_SI1932",
343 "DP_AN9801",
344 "DP_DP501",
345 "INTERNAL_UNIPHY",
346 "INTERNAL_KLDSCP_LVTMA",
347 "INTERNAL_UNIPHY1",
348 "INTERNAL_UNIPHY2",
349 "NUTMEG",
350 "TRAVIS",
351 "INTERNAL_VCE",
352 "INTERNAL_UNIPHY3",
353 "HDMI_ANX9805",
354 "INTERNAL_AMCLK",
355 "VIRTUAL",
356 };
357
358 static const char *hpd_names[6] = {
359 "HPD1",
360 "HPD2",
361 "HPD3",
362 "HPD4",
363 "HPD5",
364 "HPD6",
365 };
366
367 void amdgpu_display_print_display_setup(struct drm_device *dev)
368 {
369 struct drm_connector *connector;
370 struct amdgpu_connector *amdgpu_connector;
371 struct drm_encoder *encoder;
372 struct amdgpu_encoder *amdgpu_encoder;
373 struct drm_connector_list_iter iter;
374 uint32_t devices;
375 int i = 0;
376
377 drm_connector_list_iter_begin(dev, &iter);
378 DRM_INFO("AMDGPU Display Connectors\n");
379 drm_for_each_connector_iter(connector, &iter) {
380 amdgpu_connector = to_amdgpu_connector(connector);
381 DRM_INFO("Connector %d:\n", i);
382 DRM_INFO(" %s\n", connector->name);
383 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
384 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
385 if (amdgpu_connector->ddc_bus) {
386 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
387 amdgpu_connector->ddc_bus->rec.mask_clk_reg,
388 amdgpu_connector->ddc_bus->rec.mask_data_reg,
389 amdgpu_connector->ddc_bus->rec.a_clk_reg,
390 amdgpu_connector->ddc_bus->rec.a_data_reg,
391 amdgpu_connector->ddc_bus->rec.en_clk_reg,
392 amdgpu_connector->ddc_bus->rec.en_data_reg,
393 amdgpu_connector->ddc_bus->rec.y_clk_reg,
394 amdgpu_connector->ddc_bus->rec.y_data_reg);
395 if (amdgpu_connector->router.ddc_valid)
396 DRM_INFO(" DDC Router 0x%x/0x%x\n",
397 amdgpu_connector->router.ddc_mux_control_pin,
398 amdgpu_connector->router.ddc_mux_state);
399 if (amdgpu_connector->router.cd_valid)
400 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
401 amdgpu_connector->router.cd_mux_control_pin,
402 amdgpu_connector->router.cd_mux_state);
403 } else {
404 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
405 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
406 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
407 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
408 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
409 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
410 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
411 }
412 DRM_INFO(" Encoders:\n");
413 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
414 amdgpu_encoder = to_amdgpu_encoder(encoder);
415 devices = amdgpu_encoder->devices & amdgpu_connector->devices;
416 if (devices) {
417 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
418 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
419 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
420 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
421 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
422 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
423 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
424 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
425 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
426 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
427 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
428 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
429 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
430 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
431 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
432 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
433 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
434 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
435 if (devices & ATOM_DEVICE_TV1_SUPPORT)
436 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
437 if (devices & ATOM_DEVICE_CV_SUPPORT)
438 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
439 }
440 }
441 i++;
442 }
443 drm_connector_list_iter_end(&iter);
444 }
445
446 /**
447 * amdgpu_display_ddc_probe
448 *
449 */
450 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
451 bool use_aux)
452 {
453 u8 out = 0x0;
454 u8 buf[8];
455 int ret;
456 struct i2c_msg msgs[] = {
457 {
458 .addr = DDC_ADDR,
459 .flags = 0,
460 .len = 1,
461 .buf = &out,
462 },
463 {
464 .addr = DDC_ADDR,
465 .flags = I2C_M_RD,
466 .len = 8,
467 .buf = buf,
468 }
469 };
470
471 /* on hw with routers, select right port */
472 if (amdgpu_connector->router.ddc_valid)
473 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
474
475 if (use_aux) {
476 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
477 } else {
478 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
479 }
480
481 if (ret != 2)
482 /* Couldn't find an accessible DDC on this connector */
483 return false;
484 /* Probe also for valid EDID header
485 * EDID header starts with:
486 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
487 * Only the first 6 bytes must be valid as
488 * drm_edid_block_valid() can fix the last 2 bytes */
489 if (drm_edid_header_is_valid(buf) < 6) {
490 /* Couldn't find an accessible EDID on this
491 * connector */
492 return false;
493 }
494 return true;
495 }
496
497 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
498 .destroy = drm_gem_fb_destroy,
499 .create_handle = drm_gem_fb_create_handle,
500 };
501
502 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
503 uint64_t bo_flags)
504 {
505 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
506
507 #if defined(CONFIG_DRM_AMD_DC)
508 /*
509 * if amdgpu_bo_support_uswc returns false it means that USWC mappings
510 * is not supported for this board. But this mapping is required
511 * to avoid hang caused by placement of scanout BO in GTT on certain
512 * APUs. So force the BO placement to VRAM in case this architecture
513 * will not allow USWC mappings.
514 * Also, don't allow GTT domain if the BO doens't have USWC falg set.
515 */
516 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
517 amdgpu_bo_support_uswc(bo_flags) &&
518 amdgpu_device_asic_has_dc_support(adev->asic_type)) {
519 switch (adev->asic_type) {
520 case CHIP_CARRIZO:
521 case CHIP_STONEY:
522 domain |= AMDGPU_GEM_DOMAIN_GTT;
523 break;
524 case CHIP_RAVEN:
525 /* enable S/G on PCO and RV2 */
526 if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
527 domain |= AMDGPU_GEM_DOMAIN_GTT;
528 break;
529 default:
530 break;
531 }
532 }
533 #endif
534
535 return domain;
536 }
537
538 int amdgpu_display_framebuffer_init(struct drm_device *dev,
539 struct amdgpu_framebuffer *rfb,
540 const struct drm_mode_fb_cmd2 *mode_cmd,
541 struct drm_gem_object *obj)
542 {
543 int ret;
544 rfb->base.obj[0] = obj;
545 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
546 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
547 if (ret) {
548 rfb->base.obj[0] = NULL;
549 return ret;
550 }
551 return 0;
552 }
553
554 struct drm_framebuffer *
555 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
556 struct drm_file *file_priv,
557 const struct drm_mode_fb_cmd2 *mode_cmd)
558 {
559 struct drm_gem_object *obj;
560 struct amdgpu_framebuffer *amdgpu_fb;
561 int ret;
562
563 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
564 if (obj == NULL) {
565 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
566 "can't create framebuffer\n", mode_cmd->handles[0]);
567 return ERR_PTR(-ENOENT);
568 }
569
570 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
571 if (obj->import_attach) {
572 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
573 return ERR_PTR(-EINVAL);
574 }
575
576 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
577 if (amdgpu_fb == NULL) {
578 drm_gem_object_put_unlocked(obj);
579 return ERR_PTR(-ENOMEM);
580 }
581
582 ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
583 if (ret) {
584 kfree(amdgpu_fb);
585 drm_gem_object_put_unlocked(obj);
586 return ERR_PTR(ret);
587 }
588
589 return &amdgpu_fb->base;
590 }
591
592 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
593 .fb_create = amdgpu_display_user_framebuffer_create,
594 .output_poll_changed = drm_fb_helper_output_poll_changed,
595 };
596
597 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
598 { { UNDERSCAN_OFF, "off" },
599 { UNDERSCAN_ON, "on" },
600 { UNDERSCAN_AUTO, "auto" },
601 };
602
603 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
604 { { AMDGPU_AUDIO_DISABLE, "off" },
605 { AMDGPU_AUDIO_ENABLE, "on" },
606 { AMDGPU_AUDIO_AUTO, "auto" },
607 };
608
609 /* XXX support different dither options? spatial, temporal, both, etc. */
610 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
611 { { AMDGPU_FMT_DITHER_DISABLE, "off" },
612 { AMDGPU_FMT_DITHER_ENABLE, "on" },
613 };
614
615 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
616 {
617 int sz;
618
619 adev->mode_info.coherent_mode_property =
620 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1);
621 if (!adev->mode_info.coherent_mode_property)
622 return -ENOMEM;
623
624 adev->mode_info.load_detect_property =
625 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1);
626 if (!adev->mode_info.load_detect_property)
627 return -ENOMEM;
628
629 drm_mode_create_scaling_mode_property(adev->ddev);
630
631 sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
632 adev->mode_info.underscan_property =
633 drm_property_create_enum(adev->ddev, 0,
634 "underscan",
635 amdgpu_underscan_enum_list, sz);
636
637 adev->mode_info.underscan_hborder_property =
638 drm_property_create_range(adev->ddev, 0,
639 "underscan hborder", 0, 128);
640 if (!adev->mode_info.underscan_hborder_property)
641 return -ENOMEM;
642
643 adev->mode_info.underscan_vborder_property =
644 drm_property_create_range(adev->ddev, 0,
645 "underscan vborder", 0, 128);
646 if (!adev->mode_info.underscan_vborder_property)
647 return -ENOMEM;
648
649 sz = ARRAY_SIZE(amdgpu_audio_enum_list);
650 adev->mode_info.audio_property =
651 drm_property_create_enum(adev->ddev, 0,
652 "audio",
653 amdgpu_audio_enum_list, sz);
654
655 sz = ARRAY_SIZE(amdgpu_dither_enum_list);
656 adev->mode_info.dither_property =
657 drm_property_create_enum(adev->ddev, 0,
658 "dither",
659 amdgpu_dither_enum_list, sz);
660
661 if (amdgpu_device_has_dc_support(adev)) {
662 adev->mode_info.abm_level_property =
663 drm_property_create_range(adev->ddev, 0,
664 "abm level", 0, 4);
665 if (!adev->mode_info.abm_level_property)
666 return -ENOMEM;
667 }
668
669 return 0;
670 }
671
672 void amdgpu_display_update_priority(struct amdgpu_device *adev)
673 {
674 /* adjustment options for the display watermarks */
675 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
676 adev->mode_info.disp_priority = 0;
677 else
678 adev->mode_info.disp_priority = amdgpu_disp_priority;
679
680 }
681
682 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
683 {
684 /* try and guess if this is a tv or a monitor */
685 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
686 (mode->vdisplay == 576) || /* 576p */
687 (mode->vdisplay == 720) || /* 720p */
688 (mode->vdisplay == 1080)) /* 1080p */
689 return true;
690 else
691 return false;
692 }
693
694 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
695 const struct drm_display_mode *mode,
696 struct drm_display_mode *adjusted_mode)
697 {
698 struct drm_device *dev = crtc->dev;
699 struct drm_encoder *encoder;
700 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
701 struct amdgpu_encoder *amdgpu_encoder;
702 struct drm_connector *connector;
703 u32 src_v = 1, dst_v = 1;
704 u32 src_h = 1, dst_h = 1;
705
706 amdgpu_crtc->h_border = 0;
707 amdgpu_crtc->v_border = 0;
708
709 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
710 if (encoder->crtc != crtc)
711 continue;
712 amdgpu_encoder = to_amdgpu_encoder(encoder);
713 connector = amdgpu_get_connector_for_encoder(encoder);
714
715 /* set scaling */
716 if (amdgpu_encoder->rmx_type == RMX_OFF)
717 amdgpu_crtc->rmx_type = RMX_OFF;
718 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
719 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
720 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
721 else
722 amdgpu_crtc->rmx_type = RMX_OFF;
723 /* copy native mode */
724 memcpy(&amdgpu_crtc->native_mode,
725 &amdgpu_encoder->native_mode,
726 sizeof(struct drm_display_mode));
727 src_v = crtc->mode.vdisplay;
728 dst_v = amdgpu_crtc->native_mode.vdisplay;
729 src_h = crtc->mode.hdisplay;
730 dst_h = amdgpu_crtc->native_mode.hdisplay;
731
732 /* fix up for overscan on hdmi */
733 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
734 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
735 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
736 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
737 amdgpu_display_is_hdtv_mode(mode)))) {
738 if (amdgpu_encoder->underscan_hborder != 0)
739 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
740 else
741 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
742 if (amdgpu_encoder->underscan_vborder != 0)
743 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
744 else
745 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
746 amdgpu_crtc->rmx_type = RMX_FULL;
747 src_v = crtc->mode.vdisplay;
748 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
749 src_h = crtc->mode.hdisplay;
750 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
751 }
752 }
753 if (amdgpu_crtc->rmx_type != RMX_OFF) {
754 fixed20_12 a, b;
755 a.full = dfixed_const(src_v);
756 b.full = dfixed_const(dst_v);
757 amdgpu_crtc->vsc.full = dfixed_div(a, b);
758 a.full = dfixed_const(src_h);
759 b.full = dfixed_const(dst_h);
760 amdgpu_crtc->hsc.full = dfixed_div(a, b);
761 } else {
762 amdgpu_crtc->vsc.full = dfixed_const(1);
763 amdgpu_crtc->hsc.full = dfixed_const(1);
764 }
765 return true;
766 }
767
768 /*
769 * Retrieve current video scanout position of crtc on a given gpu, and
770 * an optional accurate timestamp of when query happened.
771 *
772 * \param dev Device to query.
773 * \param pipe Crtc to query.
774 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
775 * For driver internal use only also supports these flags:
776 *
777 * USE_REAL_VBLANKSTART to use the real start of vblank instead
778 * of a fudged earlier start of vblank.
779 *
780 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
781 * fudged earlier start of vblank in *vpos and the distance
782 * to true start of vblank in *hpos.
783 *
784 * \param *vpos Location where vertical scanout position should be stored.
785 * \param *hpos Location where horizontal scanout position should go.
786 * \param *stime Target location for timestamp taken immediately before
787 * scanout position query. Can be NULL to skip timestamp.
788 * \param *etime Target location for timestamp taken immediately after
789 * scanout position query. Can be NULL to skip timestamp.
790 *
791 * Returns vpos as a positive number while in active scanout area.
792 * Returns vpos as a negative number inside vblank, counting the number
793 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
794 * until start of active scanout / end of vblank."
795 *
796 * \return Flags, or'ed together as follows:
797 *
798 * DRM_SCANOUTPOS_VALID = Query successful.
799 * DRM_SCANOUTPOS_INVBL = Inside vblank.
800 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
801 * this flag means that returned position may be offset by a constant but
802 * unknown small number of scanlines wrt. real scanout position.
803 *
804 */
805 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
806 unsigned int pipe, unsigned int flags, int *vpos,
807 int *hpos, ktime_t *stime, ktime_t *etime,
808 const struct drm_display_mode *mode)
809 {
810 u32 vbl = 0, position = 0;
811 int vbl_start, vbl_end, vtotal, ret = 0;
812 bool in_vbl = true;
813
814 struct amdgpu_device *adev = dev->dev_private;
815
816 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
817
818 /* Get optional system timestamp before query. */
819 if (stime)
820 *stime = ktime_get();
821
822 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
823 ret |= DRM_SCANOUTPOS_VALID;
824
825 /* Get optional system timestamp after query. */
826 if (etime)
827 *etime = ktime_get();
828
829 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
830
831 /* Decode into vertical and horizontal scanout position. */
832 *vpos = position & 0x1fff;
833 *hpos = (position >> 16) & 0x1fff;
834
835 /* Valid vblank area boundaries from gpu retrieved? */
836 if (vbl > 0) {
837 /* Yes: Decode. */
838 ret |= DRM_SCANOUTPOS_ACCURATE;
839 vbl_start = vbl & 0x1fff;
840 vbl_end = (vbl >> 16) & 0x1fff;
841 }
842 else {
843 /* No: Fake something reasonable which gives at least ok results. */
844 vbl_start = mode->crtc_vdisplay;
845 vbl_end = 0;
846 }
847
848 /* Called from driver internal vblank counter query code? */
849 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
850 /* Caller wants distance from real vbl_start in *hpos */
851 *hpos = *vpos - vbl_start;
852 }
853
854 /* Fudge vblank to start a few scanlines earlier to handle the
855 * problem that vblank irqs fire a few scanlines before start
856 * of vblank. Some driver internal callers need the true vblank
857 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
858 *
859 * The cause of the "early" vblank irq is that the irq is triggered
860 * by the line buffer logic when the line buffer read position enters
861 * the vblank, whereas our crtc scanout position naturally lags the
862 * line buffer read position.
863 */
864 if (!(flags & USE_REAL_VBLANKSTART))
865 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
866
867 /* Test scanout position against vblank region. */
868 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
869 in_vbl = false;
870
871 /* In vblank? */
872 if (in_vbl)
873 ret |= DRM_SCANOUTPOS_IN_VBLANK;
874
875 /* Called from driver internal vblank counter query code? */
876 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
877 /* Caller wants distance from fudged earlier vbl_start */
878 *vpos -= vbl_start;
879 return ret;
880 }
881
882 /* Check if inside vblank area and apply corrective offsets:
883 * vpos will then be >=0 in video scanout area, but negative
884 * within vblank area, counting down the number of lines until
885 * start of scanout.
886 */
887
888 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
889 if (in_vbl && (*vpos >= vbl_start)) {
890 vtotal = mode->crtc_vtotal;
891
892 /* With variable refresh rate displays the vpos can exceed
893 * the vtotal value. Clamp to 0 to return -vbl_end instead
894 * of guessing the remaining number of lines until scanout.
895 */
896 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
897 }
898
899 /* Correct for shifted end of vbl at vbl_end. */
900 *vpos = *vpos - vbl_end;
901
902 return ret;
903 }
904
905 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
906 {
907 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
908 return AMDGPU_CRTC_IRQ_NONE;
909
910 switch (crtc) {
911 case 0:
912 return AMDGPU_CRTC_IRQ_VBLANK1;
913 case 1:
914 return AMDGPU_CRTC_IRQ_VBLANK2;
915 case 2:
916 return AMDGPU_CRTC_IRQ_VBLANK3;
917 case 3:
918 return AMDGPU_CRTC_IRQ_VBLANK4;
919 case 4:
920 return AMDGPU_CRTC_IRQ_VBLANK5;
921 case 5:
922 return AMDGPU_CRTC_IRQ_VBLANK6;
923 default:
924 return AMDGPU_CRTC_IRQ_NONE;
925 }
926 }
Linux with added FPC-III support