drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 #ifndef __AMDGPU_GMC_H__
  27 #define __AMDGPU_GMC_H__
  28
  29 #include <linux/types.h>
  30
  31 #include "amdgpu_irq.h"
  32
  33 /* VA hole for 48bit addresses on Vega10 */
  34 #define AMDGPU_GMC_HOLE_START   0x0000800000000000ULL
  35 #define AMDGPU_GMC_HOLE_END     0xffff800000000000ULL
  36
  37 /*
  38  * Hardware is programmed as if the hole doesn't exists with start and end
  39  * address values.
  40  *
  41  * This mask is used to remove the upper 16bits of the VA and so come up with
  42  * the linear addr value.
  43  */
  44 #define AMDGPU_GMC_HOLE_MASK    0x0000ffffffffffffULL
  45
  46 /*
  47  * Ring size as power of two for the log of recent faults.
  48  */
  49 #define AMDGPU_GMC_FAULT_RING_ORDER     8
  50 #define AMDGPU_GMC_FAULT_RING_SIZE      (1 << AMDGPU_GMC_FAULT_RING_ORDER)
  51
  52 /*
  53  * Hash size as power of two for the log of recent faults
  54  */
  55 #define AMDGPU_GMC_FAULT_HASH_ORDER     8
  56 #define AMDGPU_GMC_FAULT_HASH_SIZE      (1 << AMDGPU_GMC_FAULT_HASH_ORDER)
  57
  58 /*
  59  * Number of IH timestamp ticks until a fault is considered handled
  60  */
  61 #define AMDGPU_GMC_FAULT_TIMEOUT        5000ULL
  62
  63 /*
  64  * Default stolen memory size, 1024 * 768 * 4
  65  */
  66 #define AMDGPU_STOLEN_BIST_TRAINING_DEFAULT_SIZE        0x300000ULL
  67
  68 struct firmware;
  69
  70 /*
  71  * GMC page fault information
  72  */
  73 struct amdgpu_gmc_fault {
  74         uint64_t        timestamp;
  75         uint64_t        next:AMDGPU_GMC_FAULT_RING_ORDER;
  76         uint64_t        key:52;
  77 };
  78
  79 /*
  80  * VMHUB structures, functions & helpers
  81  */
  82 struct amdgpu_vmhub {
  83         uint32_t        ctx0_ptb_addr_lo32;
  84         uint32_t        ctx0_ptb_addr_hi32;
  85         uint32_t        vm_inv_eng0_sem;
  86         uint32_t        vm_inv_eng0_req;
  87         uint32_t        vm_inv_eng0_ack;
  88         uint32_t        vm_context0_cntl;
  89         uint32_t        vm_l2_pro_fault_status;
  90         uint32_t        vm_l2_pro_fault_cntl;
  91 };
  92
  93 /*
  94  * GPU MC structures, functions & helpers
  95  */
  96 struct amdgpu_gmc_funcs {
  97         /* flush the vm tlb via mmio */
  98         void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
  99                                 uint32_t vmhub, uint32_t flush_type);
 100         /* flush the vm tlb via pasid */
 101         int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
 102                                         uint32_t flush_type, bool all_hub);
 103         /* flush the vm tlb via ring */
 104         uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
 105                                        uint64_t pd_addr);
 106         /* Change the VMID -> PASID mapping */
 107         void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
 108                                    unsigned pasid);
 109         /* enable/disable PRT support */
 110         void (*set_prt)(struct amdgpu_device *adev, bool enable);
 111         /* map mtype to hardware flags */
 112         uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags);
 113         /* get the pde for a given mc addr */
 114         void (*get_vm_pde)(struct amdgpu_device *adev, int level,
 115                            u64 *dst, u64 *flags);
 116         /* get the pte flags to use for a BO VA mapping */
 117         void (*get_vm_pte)(struct amdgpu_device *adev,
 118                            struct amdgpu_bo_va_mapping *mapping,
 119                            uint64_t *flags);
 120 };
 121
 122 struct amdgpu_xgmi {
 123         /* from psp */
 124         u64 node_id;
 125         u64 hive_id;
 126         /* fixed per family */
 127         u64 node_segment_size;
 128         /* physical node (0-3) */
 129         unsigned physical_node_id;
 130         /* number of nodes (0-4) */
 131         unsigned num_physical_nodes;
 132         /* gpu list in the same hive */
 133         struct list_head head;
 134         bool supported;
 135         struct ras_common_if *ras_if;
 136 };
 137
 138 struct amdgpu_gmc {
 139         /* FB's physical address in MMIO space (for CPU to
 140          * map FB). This is different compared to the agp/
 141          * gart/vram_start/end field as the later is from
 142          * GPU's view and aper_base is from CPU's view.
 143          */
 144         resource_size_t         aper_size;
 145         resource_size_t         aper_base;
 146         /* for some chips with <= 32MB we need to lie
 147          * about vram size near mc fb location */
 148         u64                     mc_vram_size;
 149         u64                     visible_vram_size;
 150         /* AGP aperture start and end in MC address space
 151          * Driver find a hole in the MC address space
 152          * to place AGP by setting MC_VM_AGP_BOT/TOP registers
 153          * Under VMID0, logical address == MC address. AGP
 154          * aperture maps to physical bus or IOVA addressed.
 155          * AGP aperture is used to simulate FB in ZFB case.
 156          * AGP aperture is also used for page table in system
 157          * memory (mainly for APU).
 158          *
 159          */
 160         u64                     agp_size;
 161         u64                     agp_start;
 162         u64                     agp_end;
 163         /* GART aperture start and end in MC address space
 164          * Driver find a hole in the MC address space
 165          * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR
 166          * registers
 167          * Under VMID0, logical address inside GART aperture will
 168          * be translated through gpuvm gart page table to access
 169          * paged system memory
 170          */
 171         u64                     gart_size;
 172         u64                     gart_start;
 173         u64                     gart_end;
 174         /* Frame buffer aperture of this GPU device. Different from
 175          * fb_start (see below), this only covers the local GPU device.
 176          * Driver get fb_start from MC_VM_FB_LOCATION_BASE (set by vbios)
 177          * and calculate vram_start of this local device by adding an
 178          * offset inside the XGMI hive.
 179          * Under VMID0, logical address == MC address
 180          */
 181         u64                     vram_start;
 182         u64                     vram_end;
 183         /* FB region , it's same as local vram region in single GPU, in XGMI
 184          * configuration, this region covers all GPUs in the same hive ,
 185          * each GPU in the hive has the same view of this FB region .
 186          * GPU0's vram starts at offset (0 * segment size) ,
 187          * GPU1 starts at offset (1 * segment size), etc.
 188          */
 189         u64                     fb_start;
 190         u64                     fb_end;
 191         unsigned                vram_width;
 192         u64                     real_vram_size;
 193         int                     vram_mtrr;
 194         u64                     mc_mask;
 195         const struct firmware   *fw;    /* MC firmware */
 196         uint32_t                fw_version;
 197         struct amdgpu_irq_src   vm_fault;
 198         uint32_t                vram_type;
 199         uint8_t                 vram_vendor;
 200         uint32_t                srbm_soft_reset;
 201         bool                    prt_warning;
 202         uint64_t                stolen_size;
 203         /* apertures */
 204         u64                     shared_aperture_start;
 205         u64                     shared_aperture_end;
 206         u64                     private_aperture_start;
 207         u64                     private_aperture_end;
 208         /* protects concurrent invalidation */
 209         spinlock_t              invalidate_lock;
 210         bool                    translate_further;
 211         struct kfd_vm_fault_info *vm_fault_info;
 212         atomic_t                vm_fault_info_updated;
 213
 214         struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE];
 215         struct {
 216                 uint64_t        idx:AMDGPU_GMC_FAULT_RING_ORDER;
 217         } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE];
 218         uint64_t                last_fault:AMDGPU_GMC_FAULT_RING_ORDER;
 219
 220         const struct amdgpu_gmc_funcs   *gmc_funcs;
 221
 222         struct amdgpu_xgmi xgmi;
 223         struct amdgpu_irq_src   ecc_irq;
 224 };
 225
 226 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
 227 #define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
 228         ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
 229         ((adev), (pasid), (type), (allhub)))
 230 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
 231 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
 232 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
 233 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
 234 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags))
 235
 236 /**
 237  * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
 238  *
 239  * @adev: amdgpu_device pointer
 240  *
 241  * Returns:
 242  * True if full VRAM is visible through the BAR
 243  */
 244 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
 245 {
 246         WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
 247
 248         return (gmc->real_vram_size == gmc->visible_vram_size);
 249 }
 250
 251 /**
 252  * amdgpu_gmc_sign_extend - sign extend the given gmc address
 253  *
 254  * @addr: address to extend
 255  */
 256 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
 257 {
 258         if (addr >= AMDGPU_GMC_HOLE_START)
 259                 addr |= AMDGPU_GMC_HOLE_END;
 260
 261         return addr;
 262 }
 263
 264 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
 265                                uint64_t *addr, uint64_t *flags);
 266 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
 267                                 uint32_t gpu_page_idx, uint64_t addr,
 268                                 uint64_t flags);
 269 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
 270 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
 271 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
 272                               u64 base);
 273 void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
 274                               struct amdgpu_gmc *mc);
 275 void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
 276                              struct amdgpu_gmc *mc);
 277 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
 278                               uint16_t pasid, uint64_t timestamp);
 279 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev);
 280 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
 281 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev);
 282
 283 #endif