drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __AMDGPU_OBJECT_H__
  29 #define __AMDGPU_OBJECT_H__
  30
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu.h"
  33 #ifdef CONFIG_MMU_NOTIFIER
  34 #include <linux/mmu_notifier.h>
  35 #endif
  36
  37 #define AMDGPU_BO_INVALID_OFFSET        LONG_MAX
  38 #define AMDGPU_BO_MAX_PLACEMENTS        3
  39
  40 struct amdgpu_bo_param {
  41         unsigned long                   size;
  42         int                             byte_align;
  43         u32                             domain;
  44         u32                             preferred_domain;
  45         u64                             flags;
  46         enum ttm_bo_type                type;
  47         bool                            no_wait_gpu;
  48         struct dma_resv *resv;
  49 };
  50
  51 /* bo virtual addresses in a vm */
  52 struct amdgpu_bo_va_mapping {
  53         struct amdgpu_bo_va             *bo_va;
  54         struct list_head                list;
  55         struct rb_node                  rb;
  56         uint64_t                        start;
  57         uint64_t                        last;
  58         uint64_t                        __subtree_last;
  59         uint64_t                        offset;
  60         uint64_t                        flags;
  61 };
  62
  63 /* User space allocated BO in a VM */
  64 struct amdgpu_bo_va {
  65         struct amdgpu_vm_bo_base        base;
  66
  67         /* protected by bo being reserved */
  68         unsigned                        ref_count;
  69
  70         /* all other members protected by the VM PD being reserved */
  71         struct dma_fence                *last_pt_update;
  72
  73         /* mappings for this bo_va */
  74         struct list_head                invalids;
  75         struct list_head                valids;
  76
  77         /* If the mappings are cleared or filled */
  78         bool                            cleared;
  79
  80         bool                            is_xgmi;
  81 };
  82
  83 struct amdgpu_bo {
  84         /* Protected by tbo.reserved */
  85         u32                             preferred_domains;
  86         u32                             allowed_domains;
  87         struct ttm_place                placements[AMDGPU_BO_MAX_PLACEMENTS];
  88         struct ttm_placement            placement;
  89         struct ttm_buffer_object        tbo;
  90         struct ttm_bo_kmap_obj          kmap;
  91         u64                             flags;
  92         unsigned                        pin_count;
  93         u64                             tiling_flags;
  94         u64                             metadata_flags;
  95         void                            *metadata;
  96         u32                             metadata_size;
  97         unsigned                        prime_shared_count;
  98         /* per VM structure for page tables and with virtual addresses */
  99         struct amdgpu_vm_bo_base        *vm_bo;
 100         /* Constant after initialization */
 101         struct amdgpu_bo                *parent;
 102         struct amdgpu_bo                *shadow;
 103
 104         struct ttm_bo_kmap_obj          dma_buf_vmap;
 105         struct amdgpu_mn                *mn;
 106
 107
 108 #ifdef CONFIG_MMU_NOTIFIER
 109         struct mmu_interval_notifier    notifier;
 110 #endif
 111
 112         struct list_head                shadow_list;
 113
 114         struct kgd_mem                  *kfd_bo;
 115 };
 116
 117 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
 118 {
 119         return container_of(tbo, struct amdgpu_bo, tbo);
 120 }
 121
 122 /**
 123  * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
 124  * @mem_type:   ttm memory type
 125  *
 126  * Returns corresponding domain of the ttm mem_type
 127  */
 128 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
 129 {
 130         switch (mem_type) {
 131         case TTM_PL_VRAM:
 132                 return AMDGPU_GEM_DOMAIN_VRAM;
 133         case TTM_PL_TT:
 134                 return AMDGPU_GEM_DOMAIN_GTT;
 135         case TTM_PL_SYSTEM:
 136                 return AMDGPU_GEM_DOMAIN_CPU;
 137         case AMDGPU_PL_GDS:
 138                 return AMDGPU_GEM_DOMAIN_GDS;
 139         case AMDGPU_PL_GWS:
 140                 return AMDGPU_GEM_DOMAIN_GWS;
 141         case AMDGPU_PL_OA:
 142                 return AMDGPU_GEM_DOMAIN_OA;
 143         default:
 144                 break;
 145         }
 146         return 0;
 147 }
 148
 149 /**
 150  * amdgpu_bo_reserve - reserve bo
 151  * @bo:         bo structure
 152  * @no_intr:    don't return -ERESTARTSYS on pending signal
 153  *
 154  * Returns:
 155  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
 156  * a signal. Release all buffer reservations and return to user-space.
 157  */
 158 static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
 159 {
 160         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 161         int r;
 162
 163         r = __ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
 164         if (unlikely(r != 0)) {
 165                 if (r != -ERESTARTSYS)
 166                         dev_err(adev->dev, "%p reserve failed\n", bo);
 167                 return r;
 168         }
 169         return 0;
 170 }
 171
 172 static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
 173 {
 174         ttm_bo_unreserve(&bo->tbo);
 175 }
 176
 177 static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
 178 {
 179         return bo->tbo.num_pages << PAGE_SHIFT;
 180 }
 181
 182 static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
 183 {
 184         return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
 185 }
 186
 187 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
 188 {
 189         return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
 190 }
 191
 192 /**
 193  * amdgpu_bo_mmap_offset - return mmap offset of bo
 194  * @bo: amdgpu object for which we query the offset
 195  *
 196  * Returns mmap offset of the object.
 197  */
 198 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
 199 {
 200         return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
 201 }
 202
 203 /**
 204  * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM
 205  */
 206 static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
 207 {
 208         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 209         unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 210         struct drm_mm_node *node = bo->tbo.mem.mm_node;
 211         unsigned long pages_left;
 212
 213         if (bo->tbo.mem.mem_type != TTM_PL_VRAM)
 214                 return false;
 215
 216         for (pages_left = bo->tbo.mem.num_pages; pages_left;
 217              pages_left -= node->size, node++)
 218                 if (node->start < fpfn)
 219                         return true;
 220
 221         return false;
 222 }
 223
 224 /**
 225  * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
 226  */
 227 static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
 228 {
 229         return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
 230 }
 231
 232 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
 233 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
 234
 235 int amdgpu_bo_create(struct amdgpu_device *adev,
 236                      struct amdgpu_bo_param *bp,
 237                      struct amdgpu_bo **bo_ptr);
 238 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 239                               unsigned long size, int align,
 240                               u32 domain, struct amdgpu_bo **bo_ptr,
 241                               u64 *gpu_addr, void **cpu_addr);
 242 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 243                             unsigned long size, int align,
 244                             u32 domain, struct amdgpu_bo **bo_ptr,
 245                             u64 *gpu_addr, void **cpu_addr);
 246 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
 247                                uint64_t offset, uint64_t size, uint32_t domain,
 248                                struct amdgpu_bo **bo_ptr, void **cpu_addr);
 249 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 250                            void **cpu_addr);
 251 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
 252 void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
 253 void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
 254 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
 255 void amdgpu_bo_unref(struct amdgpu_bo **bo);
 256 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
 257 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 258                              u64 min_offset, u64 max_offset);
 259 int amdgpu_bo_unpin(struct amdgpu_bo *bo);
 260 int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
 261 int amdgpu_bo_init(struct amdgpu_device *adev);
 262 int amdgpu_bo_late_init(struct amdgpu_device *adev);
 263 void amdgpu_bo_fini(struct amdgpu_device *adev);
 264 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 265                                 struct vm_area_struct *vma);
 266 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
 267 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
 268 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 269                             uint32_t metadata_size, uint64_t flags);
 270 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 271                            size_t buffer_size, uint32_t *metadata_size,
 272                            uint64_t *flags);
 273 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 274                            bool evict,
 275                            struct ttm_mem_reg *new_mem);
 276 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
 277 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 278 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
 279                      bool shared);
 280 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
 281 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
 282 int amdgpu_bo_validate(struct amdgpu_bo *bo);
 283 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
 284                              struct dma_fence **fence);
 285 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
 286                                             uint32_t domain);
 287
 288 /*
 289  * sub allocation
 290  */
 291
 292 static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
 293 {
 294         return sa_bo->manager->gpu_addr + sa_bo->soffset;
 295 }
 296
 297 static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
 298 {
 299         return sa_bo->manager->cpu_ptr + sa_bo->soffset;
 300 }
 301
 302 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
 303                                      struct amdgpu_sa_manager *sa_manager,
 304                                      unsigned size, u32 align, u32 domain);
 305 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
 306                                       struct amdgpu_sa_manager *sa_manager);
 307 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
 308                                       struct amdgpu_sa_manager *sa_manager);
 309 int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
 310                      struct amdgpu_sa_bo **sa_bo,
 311                      unsigned size, unsigned align);
 312 void amdgpu_sa_bo_free(struct amdgpu_device *adev,
 313                               struct amdgpu_sa_bo **sa_bo,
 314                               struct dma_fence *fence);
 315 #if defined(CONFIG_DEBUG_FS)
 316 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
 317                                          struct seq_file *m);
 318 #endif
 319
 320 bool amdgpu_bo_support_uswc(u64 bo_flags);
 321
 322
 323 #endif