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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ras.c
blob766be7f182825e6ff5c8e4885a82d5f3b1c6eba4
1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24 #include <linux/debugfs.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/uaccess.h>
28 #include <linux/reboot.h>
29 #include <linux/syscalls.h>
30
31 #include "amdgpu.h"
32 #include "amdgpu_ras.h"
33 #include "amdgpu_atomfirmware.h"
34 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
35
36 const char *ras_error_string[] = {
37 "none",
38 "parity",
39 "single_correctable",
40 "multi_uncorrectable",
41 "poison",
42 };
43
44 const char *ras_block_string[] = {
45 "umc",
46 "sdma",
47 "gfx",
48 "mmhub",
49 "athub",
50 "pcie_bif",
51 "hdp",
52 "xgmi_wafl",
53 "df",
54 "smn",
55 "sem",
56 "mp0",
57 "mp1",
58 "fuse",
59 };
60
61 #define ras_err_str(i) (ras_error_string[ffs(i)])
62 #define ras_block_str(i) (ras_block_string[i])
63
64 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS 1
65 #define AMDGPU_RAS_FLAG_INIT_NEED_RESET 2
66 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
67
68 /* inject address is 52 bits */
69 #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
70
71 enum amdgpu_ras_retire_page_reservation {
72 AMDGPU_RAS_RETIRE_PAGE_RESERVED,
73 AMDGPU_RAS_RETIRE_PAGE_PENDING,
74 AMDGPU_RAS_RETIRE_PAGE_FAULT,
75 };
76
77 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
78
79 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
80 uint64_t addr);
81
82 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
83 size_t size, loff_t *pos)
84 {
85 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
86 struct ras_query_if info = {
87 .head = obj->head,
88 };
89 ssize_t s;
90 char val[128];
91
92 if (amdgpu_ras_error_query(obj->adev, &info))
93 return -EINVAL;
94
95 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
96 "ue", info.ue_count,
97 "ce", info.ce_count);
98 if (*pos >= s)
99 return 0;
100
101 s -= *pos;
102 s = min_t(u64, s, size);
103
104
105 if (copy_to_user(buf, &val[*pos], s))
106 return -EINVAL;
107
108 *pos += s;
109
110 return s;
111 }
112
113 static const struct file_operations amdgpu_ras_debugfs_ops = {
114 .owner = THIS_MODULE,
115 .read = amdgpu_ras_debugfs_read,
116 .write = NULL,
117 .llseek = default_llseek
118 };
119
120 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
121 {
122 int i;
123
124 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
125 *block_id = i;
126 if (strcmp(name, ras_block_str(i)) == 0)
127 return 0;
128 }
129 return -EINVAL;
130 }
131
132 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
133 const char __user *buf, size_t size,
134 loff_t *pos, struct ras_debug_if *data)
135 {
136 ssize_t s = min_t(u64, 64, size);
137 char str[65];
138 char block_name[33];
139 char err[9] = "ue";
140 int op = -1;
141 int block_id;
142 uint32_t sub_block;
143 u64 address, value;
144
145 if (*pos)
146 return -EINVAL;
147 *pos = size;
148
149 memset(str, 0, sizeof(str));
150 memset(data, 0, sizeof(*data));
151
152 if (copy_from_user(str, buf, s))
153 return -EINVAL;
154
155 if (sscanf(str, "disable %32s", block_name) == 1)
156 op = 0;
157 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
158 op = 1;
159 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
160 op = 2;
161 else if (str[0] && str[1] && str[2] && str[3])
162 /* ascii string, but commands are not matched. */
163 return -EINVAL;
164
165 if (op != -1) {
166 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
167 return -EINVAL;
168
169 data->head.block = block_id;
170 /* only ue and ce errors are supported */
171 if (!memcmp("ue", err, 2))
172 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
173 else if (!memcmp("ce", err, 2))
174 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
175 else
176 return -EINVAL;
177
178 data->op = op;
179
180 if (op == 2) {
181 if (sscanf(str, "%*s %*s %*s %u %llu %llu",
182 &sub_block, &address, &value) != 3)
183 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
184 &sub_block, &address, &value) != 3)
185 return -EINVAL;
186 data->head.sub_block_index = sub_block;
187 data->inject.address = address;
188 data->inject.value = value;
189 }
190 } else {
191 if (size < sizeof(*data))
192 return -EINVAL;
193
194 if (copy_from_user(data, buf, sizeof(*data)))
195 return -EINVAL;
196 }
197
198 return 0;
199 }
200
201 /**
202 * DOC: AMDGPU RAS debugfs control interface
203 *
204 * It accepts struct ras_debug_if who has two members.
205 *
206 * First member: ras_debug_if::head or ras_debug_if::inject.
207 *
208 * head is used to indicate which IP block will be under control.
209 *
210 * head has four members, they are block, type, sub_block_index, name.
211 * block: which IP will be under control.
212 * type: what kind of error will be enabled/disabled/injected.
213 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
214 * name: the name of IP.
215 *
216 * inject has two more members than head, they are address, value.
217 * As their names indicate, inject operation will write the
218 * value to the address.
219 *
220 * The second member: struct ras_debug_if::op.
221 * It has three kinds of operations.
222 *
223 * - 0: disable RAS on the block. Take ::head as its data.
224 * - 1: enable RAS on the block. Take ::head as its data.
225 * - 2: inject errors on the block. Take ::inject as its data.
226 *
227 * How to use the interface?
228 *
229 * Programs
230 *
231 * Copy the struct ras_debug_if in your codes and initialize it.
232 * Write the struct to the control node.
233 *
234 * Shells
235 *
236 * .. code-block:: bash
237 *
238 * echo op block [error [sub_block address value]] > .../ras/ras_ctrl
239 *
240 * Parameters:
241 *
242 * op: disable, enable, inject
243 * disable: only block is needed
244 * enable: block and error are needed
245 * inject: error, address, value are needed
246 * block: umc, sdma, gfx, .........
247 * see ras_block_string[] for details
248 * error: ue, ce
249 * ue: multi_uncorrectable
250 * ce: single_correctable
251 * sub_block:
252 * sub block index, pass 0 if there is no sub block
253 *
254 * here are some examples for bash commands:
255 *
256 * .. code-block:: bash
257 *
258 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
259 * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
260 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
261 *
262 * How to check the result?
263 *
264 * For disable/enable, please check ras features at
265 * /sys/class/drm/card[0/1/2...]/device/ras/features
266 *
267 * For inject, please check corresponding err count at
268 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
269 *
270 * .. note::
271 * Operations are only allowed on blocks which are supported.
272 * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
273 * to see which blocks support RAS on a particular asic.
274 *
275 */
276 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
277 size_t size, loff_t *pos)
278 {
279 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
280 struct ras_debug_if data;
281 int ret = 0;
282
283 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
284 if (ret)
285 return -EINVAL;
286
287 if (!amdgpu_ras_is_supported(adev, data.head.block))
288 return -EINVAL;
289
290 switch (data.op) {
291 case 0:
292 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
293 break;
294 case 1:
295 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
296 break;
297 case 2:
298 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
299 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
300 ret = -EINVAL;
301 break;
302 }
303
304 /* umc ce/ue error injection for a bad page is not allowed */
305 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
306 amdgpu_ras_check_bad_page(adev, data.inject.address)) {
307 DRM_WARN("RAS WARN: 0x%llx has been marked as bad before error injection!\n",
308 data.inject.address);
309 break;
310 }
311
312 /* data.inject.address is offset instead of absolute gpu address */
313 ret = amdgpu_ras_error_inject(adev, &data.inject);
314 break;
315 default:
316 ret = -EINVAL;
317 break;
318 }
319
320 if (ret)
321 return -EINVAL;
322
323 return size;
324 }
325
326 /**
327 * DOC: AMDGPU RAS debugfs EEPROM table reset interface
328 *
329 * Some boards contain an EEPROM which is used to persistently store a list of
330 * bad pages which experiences ECC errors in vram. This interface provides
331 * a way to reset the EEPROM, e.g., after testing error injection.
332 *
333 * Usage:
334 *
335 * .. code-block:: bash
336 *
337 * echo 1 > ../ras/ras_eeprom_reset
338 *
339 * will reset EEPROM table to 0 entries.
340 *
341 */
342 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
343 size_t size, loff_t *pos)
344 {
345 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
346 int ret;
347
348 ret = amdgpu_ras_eeprom_reset_table(&adev->psp.ras.ras->eeprom_control);
349
350 return ret == 1 ? size : -EIO;
351 }
352
353 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
354 .owner = THIS_MODULE,
355 .read = NULL,
356 .write = amdgpu_ras_debugfs_ctrl_write,
357 .llseek = default_llseek
358 };
359
360 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
361 .owner = THIS_MODULE,
362 .read = NULL,
363 .write = amdgpu_ras_debugfs_eeprom_write,
364 .llseek = default_llseek
365 };
366
367 /**
368 * DOC: AMDGPU RAS sysfs Error Count Interface
369 *
370 * It allows the user to read the error count for each IP block on the gpu through
371 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
372 *
373 * It outputs the multiple lines which report the uncorrected (ue) and corrected
374 * (ce) error counts.
375 *
376 * The format of one line is below,
377 *
378 * [ce|ue]: count
379 *
380 * Example:
381 *
382 * .. code-block:: bash
383 *
384 * ue: 0
385 * ce: 1
386 *
387 */
388 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
389 struct device_attribute *attr, char *buf)
390 {
391 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
392 struct ras_query_if info = {
393 .head = obj->head,
394 };
395
396 if (amdgpu_ras_error_query(obj->adev, &info))
397 return -EINVAL;
398
399 return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n",
400 "ue", info.ue_count,
401 "ce", info.ce_count);
402 }
403
404 /* obj begin */
405
406 #define get_obj(obj) do { (obj)->use++; } while (0)
407 #define alive_obj(obj) ((obj)->use)
408
409 static inline void put_obj(struct ras_manager *obj)
410 {
411 if (obj && --obj->use == 0)
412 list_del(&obj->node);
413 if (obj && obj->use < 0) {
414 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
415 }
416 }
417
418 /* make one obj and return it. */
419 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
420 struct ras_common_if *head)
421 {
422 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
423 struct ras_manager *obj;
424
425 if (!con)
426 return NULL;
427
428 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
429 return NULL;
430
431 obj = &con->objs[head->block];
432 /* already exist. return obj? */
433 if (alive_obj(obj))
434 return NULL;
435
436 obj->head = *head;
437 obj->adev = adev;
438 list_add(&obj->node, &con->head);
439 get_obj(obj);
440
441 return obj;
442 }
443
444 /* return an obj equal to head, or the first when head is NULL */
445 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
446 struct ras_common_if *head)
447 {
448 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
449 struct ras_manager *obj;
450 int i;
451
452 if (!con)
453 return NULL;
454
455 if (head) {
456 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
457 return NULL;
458
459 obj = &con->objs[head->block];
460
461 if (alive_obj(obj)) {
462 WARN_ON(head->block != obj->head.block);
463 return obj;
464 }
465 } else {
466 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
467 obj = &con->objs[i];
468 if (alive_obj(obj)) {
469 WARN_ON(i != obj->head.block);
470 return obj;
471 }
472 }
473 }
474
475 return NULL;
476 }
477 /* obj end */
478
479 /* feature ctl begin */
480 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
481 struct ras_common_if *head)
482 {
483 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
484
485 return con->hw_supported & BIT(head->block);
486 }
487
488 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
489 struct ras_common_if *head)
490 {
491 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
492
493 return con->features & BIT(head->block);
494 }
495
496 /*
497 * if obj is not created, then create one.
498 * set feature enable flag.
499 */
500 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
501 struct ras_common_if *head, int enable)
502 {
503 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
504 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
505
506 /* If hardware does not support ras, then do not create obj.
507 * But if hardware support ras, we can create the obj.
508 * Ras framework checks con->hw_supported to see if it need do
509 * corresponding initialization.
510 * IP checks con->support to see if it need disable ras.
511 */
512 if (!amdgpu_ras_is_feature_allowed(adev, head))
513 return 0;
514 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
515 return 0;
516
517 if (enable) {
518 if (!obj) {
519 obj = amdgpu_ras_create_obj(adev, head);
520 if (!obj)
521 return -EINVAL;
522 } else {
523 /* In case we create obj somewhere else */
524 get_obj(obj);
525 }
526 con->features |= BIT(head->block);
527 } else {
528 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
529 con->features &= ~BIT(head->block);
530 put_obj(obj);
531 }
532 }
533
534 return 0;
535 }
536
537 /* wrapper of psp_ras_enable_features */
538 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
539 struct ras_common_if *head, bool enable)
540 {
541 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
542 union ta_ras_cmd_input info;
543 int ret;
544
545 if (!con)
546 return -EINVAL;
547
548 if (!enable) {
549 info.disable_features = (struct ta_ras_disable_features_input) {
550 .block_id = amdgpu_ras_block_to_ta(head->block),
551 .error_type = amdgpu_ras_error_to_ta(head->type),
552 };
553 } else {
554 info.enable_features = (struct ta_ras_enable_features_input) {
555 .block_id = amdgpu_ras_block_to_ta(head->block),
556 .error_type = amdgpu_ras_error_to_ta(head->type),
557 };
558 }
559
560 /* Do not enable if it is not allowed. */
561 WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
562 /* Are we alerady in that state we are going to set? */
563 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
564 return 0;
565
566 if (!amdgpu_ras_intr_triggered()) {
567 ret = psp_ras_enable_features(&adev->psp, &info, enable);
568 if (ret) {
569 DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n",
570 enable ? "enable":"disable",
571 ras_block_str(head->block),
572 ret);
573 if (ret == TA_RAS_STATUS__RESET_NEEDED)
574 return -EAGAIN;
575 return -EINVAL;
576 }
577 }
578
579 /* setup the obj */
580 __amdgpu_ras_feature_enable(adev, head, enable);
581
582 return 0;
583 }
584
585 /* Only used in device probe stage and called only once. */
586 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
587 struct ras_common_if *head, bool enable)
588 {
589 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
590 int ret;
591
592 if (!con)
593 return -EINVAL;
594
595 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
596 if (enable) {
597 /* There is no harm to issue a ras TA cmd regardless of
598 * the currecnt ras state.
599 * If current state == target state, it will do nothing
600 * But sometimes it requests driver to reset and repost
601 * with error code -EAGAIN.
602 */
603 ret = amdgpu_ras_feature_enable(adev, head, 1);
604 /* With old ras TA, we might fail to enable ras.
605 * Log it and just setup the object.
606 * TODO need remove this WA in the future.
607 */
608 if (ret == -EINVAL) {
609 ret = __amdgpu_ras_feature_enable(adev, head, 1);
610 if (!ret)
611 DRM_INFO("RAS INFO: %s setup object\n",
612 ras_block_str(head->block));
613 }
614 } else {
615 /* setup the object then issue a ras TA disable cmd.*/
616 ret = __amdgpu_ras_feature_enable(adev, head, 1);
617 if (ret)
618 return ret;
619
620 ret = amdgpu_ras_feature_enable(adev, head, 0);
621 }
622 } else
623 ret = amdgpu_ras_feature_enable(adev, head, enable);
624
625 return ret;
626 }
627
628 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
629 bool bypass)
630 {
631 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
632 struct ras_manager *obj, *tmp;
633
634 list_for_each_entry_safe(obj, tmp, &con->head, node) {
635 /* bypass psp.
636 * aka just release the obj and corresponding flags
637 */
638 if (bypass) {
639 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
640 break;
641 } else {
642 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
643 break;
644 }
645 }
646
647 return con->features;
648 }
649
650 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
651 bool bypass)
652 {
653 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
654 int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
655 int i;
656 const enum amdgpu_ras_error_type default_ras_type =
657 AMDGPU_RAS_ERROR__NONE;
658
659 for (i = 0; i < ras_block_count; i++) {
660 struct ras_common_if head = {
661 .block = i,
662 .type = default_ras_type,
663 .sub_block_index = 0,
664 };
665 strcpy(head.name, ras_block_str(i));
666 if (bypass) {
667 /*
668 * bypass psp. vbios enable ras for us.
669 * so just create the obj
670 */
671 if (__amdgpu_ras_feature_enable(adev, &head, 1))
672 break;
673 } else {
674 if (amdgpu_ras_feature_enable(adev, &head, 1))
675 break;
676 }
677 }
678
679 return con->features;
680 }
681 /* feature ctl end */
682
683 /* query/inject/cure begin */
684 int amdgpu_ras_error_query(struct amdgpu_device *adev,
685 struct ras_query_if *info)
686 {
687 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
688 struct ras_err_data err_data = {0, 0, 0, NULL};
689 int i;
690
691 if (!obj)
692 return -EINVAL;
693
694 switch (info->head.block) {
695 case AMDGPU_RAS_BLOCK__UMC:
696 if (adev->umc.funcs->query_ras_error_count)
697 adev->umc.funcs->query_ras_error_count(adev, &err_data);
698 /* umc query_ras_error_address is also responsible for clearing
699 * error status
700 */
701 if (adev->umc.funcs->query_ras_error_address)
702 adev->umc.funcs->query_ras_error_address(adev, &err_data);
703 break;
704 case AMDGPU_RAS_BLOCK__SDMA:
705 if (adev->sdma.funcs->query_ras_error_count) {
706 for (i = 0; i < adev->sdma.num_instances; i++)
707 adev->sdma.funcs->query_ras_error_count(adev, i,
708 &err_data);
709 }
710 break;
711 case AMDGPU_RAS_BLOCK__GFX:
712 if (adev->gfx.funcs->query_ras_error_count)
713 adev->gfx.funcs->query_ras_error_count(adev, &err_data);
714 break;
715 case AMDGPU_RAS_BLOCK__MMHUB:
716 if (adev->mmhub.funcs->query_ras_error_count)
717 adev->mmhub.funcs->query_ras_error_count(adev, &err_data);
718 break;
719 case AMDGPU_RAS_BLOCK__PCIE_BIF:
720 if (adev->nbio.funcs->query_ras_error_count)
721 adev->nbio.funcs->query_ras_error_count(adev, &err_data);
722 break;
723 default:
724 break;
725 }
726
727 obj->err_data.ue_count += err_data.ue_count;
728 obj->err_data.ce_count += err_data.ce_count;
729
730 info->ue_count = obj->err_data.ue_count;
731 info->ce_count = obj->err_data.ce_count;
732
733 if (err_data.ce_count) {
734 dev_info(adev->dev, "%ld correctable errors detected in %s block\n",
735 obj->err_data.ce_count, ras_block_str(info->head.block));
736 }
737 if (err_data.ue_count) {
738 dev_info(adev->dev, "%ld uncorrectable errors detected in %s block\n",
739 obj->err_data.ue_count, ras_block_str(info->head.block));
740 }
741
742 return 0;
743 }
744
745 /* wrapper of psp_ras_trigger_error */
746 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
747 struct ras_inject_if *info)
748 {
749 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
750 struct ta_ras_trigger_error_input block_info = {
751 .block_id = amdgpu_ras_block_to_ta(info->head.block),
752 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
753 .sub_block_index = info->head.sub_block_index,
754 .address = info->address,
755 .value = info->value,
756 };
757 int ret = 0;
758
759 if (!obj)
760 return -EINVAL;
761
762 switch (info->head.block) {
763 case AMDGPU_RAS_BLOCK__GFX:
764 if (adev->gfx.funcs->ras_error_inject)
765 ret = adev->gfx.funcs->ras_error_inject(adev, info);
766 else
767 ret = -EINVAL;
768 break;
769 case AMDGPU_RAS_BLOCK__UMC:
770 case AMDGPU_RAS_BLOCK__MMHUB:
771 case AMDGPU_RAS_BLOCK__XGMI_WAFL:
772 case AMDGPU_RAS_BLOCK__PCIE_BIF:
773 ret = psp_ras_trigger_error(&adev->psp, &block_info);
774 break;
775 default:
776 DRM_INFO("%s error injection is not supported yet\n",
777 ras_block_str(info->head.block));
778 ret = -EINVAL;
779 }
780
781 if (ret)
782 DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n",
783 ras_block_str(info->head.block),
784 ret);
785
786 return ret;
787 }
788
789 int amdgpu_ras_error_cure(struct amdgpu_device *adev,
790 struct ras_cure_if *info)
791 {
792 /* psp fw has no cure interface for now. */
793 return 0;
794 }
795
796 /* get the total error counts on all IPs */
797 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
798 bool is_ce)
799 {
800 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
801 struct ras_manager *obj;
802 struct ras_err_data data = {0, 0};
803
804 if (!con)
805 return 0;
806
807 list_for_each_entry(obj, &con->head, node) {
808 struct ras_query_if info = {
809 .head = obj->head,
810 };
811
812 if (amdgpu_ras_error_query(adev, &info))
813 return 0;
814
815 data.ce_count += info.ce_count;
816 data.ue_count += info.ue_count;
817 }
818
819 return is_ce ? data.ce_count : data.ue_count;
820 }
821 /* query/inject/cure end */
822
823
824 /* sysfs begin */
825
826 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
827 struct ras_badpage **bps, unsigned int *count);
828
829 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
830 {
831 switch (flags) {
832 case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
833 return "R";
834 case AMDGPU_RAS_RETIRE_PAGE_PENDING:
835 return "P";
836 case AMDGPU_RAS_RETIRE_PAGE_FAULT:
837 default:
838 return "F";
839 };
840 }
841
842 /**
843 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
844 *
845 * It allows user to read the bad pages of vram on the gpu through
846 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
847 *
848 * It outputs multiple lines, and each line stands for one gpu page.
849 *
850 * The format of one line is below,
851 * gpu pfn : gpu page size : flags
852 *
853 * gpu pfn and gpu page size are printed in hex format.
854 * flags can be one of below character,
855 *
856 * R: reserved, this gpu page is reserved and not able to use.
857 *
858 * P: pending for reserve, this gpu page is marked as bad, will be reserved
859 * in next window of page_reserve.
860 *
861 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
862 *
863 * Examples:
864 *
865 * .. code-block:: bash
866 *
867 * 0x00000001 : 0x00001000 : R
868 * 0x00000002 : 0x00001000 : P
869 *
870 */
871
872 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
873 struct kobject *kobj, struct bin_attribute *attr,
874 char *buf, loff_t ppos, size_t count)
875 {
876 struct amdgpu_ras *con =
877 container_of(attr, struct amdgpu_ras, badpages_attr);
878 struct amdgpu_device *adev = con->adev;
879 const unsigned int element_size =
880 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
881 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
882 unsigned int end = div64_ul(ppos + count - 1, element_size);
883 ssize_t s = 0;
884 struct ras_badpage *bps = NULL;
885 unsigned int bps_count = 0;
886
887 memset(buf, 0, count);
888
889 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
890 return 0;
891
892 for (; start < end && start < bps_count; start++)
893 s += scnprintf(&buf[s], element_size + 1,
894 "0x%08x : 0x%08x : %1s\n",
895 bps[start].bp,
896 bps[start].size,
897 amdgpu_ras_badpage_flags_str(bps[start].flags));
898
899 kfree(bps);
900
901 return s;
902 }
903
904 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
905 struct device_attribute *attr, char *buf)
906 {
907 struct amdgpu_ras *con =
908 container_of(attr, struct amdgpu_ras, features_attr);
909
910 return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
911 }
912
913 static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev)
914 {
915 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
916 struct attribute *attrs[] = {
917 &con->features_attr.attr,
918 NULL
919 };
920 struct bin_attribute *bin_attrs[] = {
921 &con->badpages_attr,
922 NULL
923 };
924 struct attribute_group group = {
925 .name = "ras",
926 .attrs = attrs,
927 .bin_attrs = bin_attrs,
928 };
929
930 con->features_attr = (struct device_attribute) {
931 .attr = {
932 .name = "features",
933 .mode = S_IRUGO,
934 },
935 .show = amdgpu_ras_sysfs_features_read,
936 };
937
938 con->badpages_attr = (struct bin_attribute) {
939 .attr = {
940 .name = "gpu_vram_bad_pages",
941 .mode = S_IRUGO,
942 },
943 .size = 0,
944 .private = NULL,
945 .read = amdgpu_ras_sysfs_badpages_read,
946 };
947
948 sysfs_attr_init(attrs[0]);
949 sysfs_bin_attr_init(bin_attrs[0]);
950
951 return sysfs_create_group(&adev->dev->kobj, &group);
952 }
953
954 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
955 {
956 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
957 struct attribute *attrs[] = {
958 &con->features_attr.attr,
959 NULL
960 };
961 struct bin_attribute *bin_attrs[] = {
962 &con->badpages_attr,
963 NULL
964 };
965 struct attribute_group group = {
966 .name = "ras",
967 .attrs = attrs,
968 .bin_attrs = bin_attrs,
969 };
970
971 sysfs_remove_group(&adev->dev->kobj, &group);
972
973 return 0;
974 }
975
976 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
977 struct ras_fs_if *head)
978 {
979 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
980
981 if (!obj || obj->attr_inuse)
982 return -EINVAL;
983
984 get_obj(obj);
985
986 memcpy(obj->fs_data.sysfs_name,
987 head->sysfs_name,
988 sizeof(obj->fs_data.sysfs_name));
989
990 obj->sysfs_attr = (struct device_attribute){
991 .attr = {
992 .name = obj->fs_data.sysfs_name,
993 .mode = S_IRUGO,
994 },
995 .show = amdgpu_ras_sysfs_read,
996 };
997 sysfs_attr_init(&obj->sysfs_attr.attr);
998
999 if (sysfs_add_file_to_group(&adev->dev->kobj,
1000 &obj->sysfs_attr.attr,
1001 "ras")) {
1002 put_obj(obj);
1003 return -EINVAL;
1004 }
1005
1006 obj->attr_inuse = 1;
1007
1008 return 0;
1009 }
1010
1011 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1012 struct ras_common_if *head)
1013 {
1014 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1015
1016 if (!obj || !obj->attr_inuse)
1017 return -EINVAL;
1018
1019 sysfs_remove_file_from_group(&adev->dev->kobj,
1020 &obj->sysfs_attr.attr,
1021 "ras");
1022 obj->attr_inuse = 0;
1023 put_obj(obj);
1024
1025 return 0;
1026 }
1027
1028 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1029 {
1030 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1031 struct ras_manager *obj, *tmp;
1032
1033 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1034 amdgpu_ras_sysfs_remove(adev, &obj->head);
1035 }
1036
1037 amdgpu_ras_sysfs_remove_feature_node(adev);
1038
1039 return 0;
1040 }
1041 /* sysfs end */
1042
1043 /**
1044 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1045 *
1046 * Normally when there is an uncorrectable error, the driver will reset
1047 * the GPU to recover. However, in the event of an unrecoverable error,
1048 * the driver provides an interface to reboot the system automatically
1049 * in that event.
1050 *
1051 * The following file in debugfs provides that interface:
1052 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1053 *
1054 * Usage:
1055 *
1056 * .. code-block:: bash
1057 *
1058 * echo true > .../ras/auto_reboot
1059 *
1060 */
1061 /* debugfs begin */
1062 static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1063 {
1064 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1065 struct drm_minor *minor = adev->ddev->primary;
1066
1067 con->dir = debugfs_create_dir("ras", minor->debugfs_root);
1068 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir,
1069 adev, &amdgpu_ras_debugfs_ctrl_ops);
1070 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir,
1071 adev, &amdgpu_ras_debugfs_eeprom_ops);
1072
1073 /*
1074 * After one uncorrectable error happens, usually GPU recovery will
1075 * be scheduled. But due to the known problem in GPU recovery failing
1076 * to bring GPU back, below interface provides one direct way to
1077 * user to reboot system automatically in such case within
1078 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1079 * will never be called.
1080 */
1081 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, con->dir,
1082 &con->reboot);
1083 }
1084
1085 void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1086 struct ras_fs_if *head)
1087 {
1088 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1089 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1090
1091 if (!obj || obj->ent)
1092 return;
1093
1094 get_obj(obj);
1095
1096 memcpy(obj->fs_data.debugfs_name,
1097 head->debugfs_name,
1098 sizeof(obj->fs_data.debugfs_name));
1099
1100 obj->ent = debugfs_create_file(obj->fs_data.debugfs_name,
1101 S_IWUGO | S_IRUGO, con->dir, obj,
1102 &amdgpu_ras_debugfs_ops);
1103 }
1104
1105 void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
1106 struct ras_common_if *head)
1107 {
1108 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1109
1110 if (!obj || !obj->ent)
1111 return;
1112
1113 debugfs_remove(obj->ent);
1114 obj->ent = NULL;
1115 put_obj(obj);
1116 }
1117
1118 static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev)
1119 {
1120 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1121 struct ras_manager *obj, *tmp;
1122
1123 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1124 amdgpu_ras_debugfs_remove(adev, &obj->head);
1125 }
1126
1127 debugfs_remove_recursive(con->dir);
1128 con->dir = NULL;
1129 }
1130 /* debugfs end */
1131
1132 /* ras fs */
1133
1134 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1135 {
1136 amdgpu_ras_sysfs_create_feature_node(adev);
1137 amdgpu_ras_debugfs_create_ctrl_node(adev);
1138
1139 return 0;
1140 }
1141
1142 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1143 {
1144 amdgpu_ras_debugfs_remove_all(adev);
1145 amdgpu_ras_sysfs_remove_all(adev);
1146 return 0;
1147 }
1148 /* ras fs end */
1149
1150 /* ih begin */
1151 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1152 {
1153 struct ras_ih_data *data = &obj->ih_data;
1154 struct amdgpu_iv_entry entry;
1155 int ret;
1156 struct ras_err_data err_data = {0, 0, 0, NULL};
1157
1158 while (data->rptr != data->wptr) {
1159 rmb();
1160 memcpy(&entry, &data->ring[data->rptr],
1161 data->element_size);
1162
1163 wmb();
1164 data->rptr = (data->aligned_element_size +
1165 data->rptr) % data->ring_size;
1166
1167 /* Let IP handle its data, maybe we need get the output
1168 * from the callback to udpate the error type/count, etc
1169 */
1170 if (data->cb) {
1171 ret = data->cb(obj->adev, &err_data, &entry);
1172 /* ue will trigger an interrupt, and in that case
1173 * we need do a reset to recovery the whole system.
1174 * But leave IP do that recovery, here we just dispatch
1175 * the error.
1176 */
1177 if (ret == AMDGPU_RAS_SUCCESS) {
1178 /* these counts could be left as 0 if
1179 * some blocks do not count error number
1180 */
1181 obj->err_data.ue_count += err_data.ue_count;
1182 obj->err_data.ce_count += err_data.ce_count;
1183 }
1184 }
1185 }
1186 }
1187
1188 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1189 {
1190 struct ras_ih_data *data =
1191 container_of(work, struct ras_ih_data, ih_work);
1192 struct ras_manager *obj =
1193 container_of(data, struct ras_manager, ih_data);
1194
1195 amdgpu_ras_interrupt_handler(obj);
1196 }
1197
1198 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1199 struct ras_dispatch_if *info)
1200 {
1201 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1202 struct ras_ih_data *data = &obj->ih_data;
1203
1204 if (!obj)
1205 return -EINVAL;
1206
1207 if (data->inuse == 0)
1208 return 0;
1209
1210 /* Might be overflow... */
1211 memcpy(&data->ring[data->wptr], info->entry,
1212 data->element_size);
1213
1214 wmb();
1215 data->wptr = (data->aligned_element_size +
1216 data->wptr) % data->ring_size;
1217
1218 schedule_work(&data->ih_work);
1219
1220 return 0;
1221 }
1222
1223 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1224 struct ras_ih_if *info)
1225 {
1226 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1227 struct ras_ih_data *data;
1228
1229 if (!obj)
1230 return -EINVAL;
1231
1232 data = &obj->ih_data;
1233 if (data->inuse == 0)
1234 return 0;
1235
1236 cancel_work_sync(&data->ih_work);
1237
1238 kfree(data->ring);
1239 memset(data, 0, sizeof(*data));
1240 put_obj(obj);
1241
1242 return 0;
1243 }
1244
1245 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1246 struct ras_ih_if *info)
1247 {
1248 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1249 struct ras_ih_data *data;
1250
1251 if (!obj) {
1252 /* in case we registe the IH before enable ras feature */
1253 obj = amdgpu_ras_create_obj(adev, &info->head);
1254 if (!obj)
1255 return -EINVAL;
1256 } else
1257 get_obj(obj);
1258
1259 data = &obj->ih_data;
1260 /* add the callback.etc */
1261 *data = (struct ras_ih_data) {
1262 .inuse = 0,
1263 .cb = info->cb,
1264 .element_size = sizeof(struct amdgpu_iv_entry),
1265 .rptr = 0,
1266 .wptr = 0,
1267 };
1268
1269 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1270
1271 data->aligned_element_size = ALIGN(data->element_size, 8);
1272 /* the ring can store 64 iv entries. */
1273 data->ring_size = 64 * data->aligned_element_size;
1274 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1275 if (!data->ring) {
1276 put_obj(obj);
1277 return -ENOMEM;
1278 }
1279
1280 /* IH is ready */
1281 data->inuse = 1;
1282
1283 return 0;
1284 }
1285
1286 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1287 {
1288 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1289 struct ras_manager *obj, *tmp;
1290
1291 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1292 struct ras_ih_if info = {
1293 .head = obj->head,
1294 };
1295 amdgpu_ras_interrupt_remove_handler(adev, &info);
1296 }
1297
1298 return 0;
1299 }
1300 /* ih end */
1301
1302 /* recovery begin */
1303
1304 /* return 0 on success.
1305 * caller need free bps.
1306 */
1307 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1308 struct ras_badpage **bps, unsigned int *count)
1309 {
1310 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1311 struct ras_err_handler_data *data;
1312 int i = 0;
1313 int ret = 0;
1314
1315 if (!con || !con->eh_data || !bps || !count)
1316 return -EINVAL;
1317
1318 mutex_lock(&con->recovery_lock);
1319 data = con->eh_data;
1320 if (!data || data->count == 0) {
1321 *bps = NULL;
1322 ret = -EINVAL;
1323 goto out;
1324 }
1325
1326 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1327 if (!*bps) {
1328 ret = -ENOMEM;
1329 goto out;
1330 }
1331
1332 for (; i < data->count; i++) {
1333 (*bps)[i] = (struct ras_badpage){
1334 .bp = data->bps[i].retired_page,
1335 .size = AMDGPU_GPU_PAGE_SIZE,
1336 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1337 };
1338
1339 if (data->last_reserved <= i)
1340 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1341 else if (data->bps_bo[i] == NULL)
1342 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1343 }
1344
1345 *count = data->count;
1346 out:
1347 mutex_unlock(&con->recovery_lock);
1348 return ret;
1349 }
1350
1351 static void amdgpu_ras_do_recovery(struct work_struct *work)
1352 {
1353 struct amdgpu_ras *ras =
1354 container_of(work, struct amdgpu_ras, recovery_work);
1355
1356 if (amdgpu_device_should_recover_gpu(ras->adev))
1357 amdgpu_device_gpu_recover(ras->adev, 0);
1358 atomic_set(&ras->in_recovery, 0);
1359 }
1360
1361 /* alloc/realloc bps array */
1362 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1363 struct ras_err_handler_data *data, int pages)
1364 {
1365 unsigned int old_space = data->count + data->space_left;
1366 unsigned int new_space = old_space + pages;
1367 unsigned int align_space = ALIGN(new_space, 512);
1368 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1369 struct amdgpu_bo **bps_bo =
1370 kmalloc(align_space * sizeof(*data->bps_bo), GFP_KERNEL);
1371
1372 if (!bps || !bps_bo) {
1373 kfree(bps);
1374 kfree(bps_bo);
1375 return -ENOMEM;
1376 }
1377
1378 if (data->bps) {
1379 memcpy(bps, data->bps,
1380 data->count * sizeof(*data->bps));
1381 kfree(data->bps);
1382 }
1383 if (data->bps_bo) {
1384 memcpy(bps_bo, data->bps_bo,
1385 data->count * sizeof(*data->bps_bo));
1386 kfree(data->bps_bo);
1387 }
1388
1389 data->bps = bps;
1390 data->bps_bo = bps_bo;
1391 data->space_left += align_space - old_space;
1392 return 0;
1393 }
1394
1395 /* it deal with vram only. */
1396 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1397 struct eeprom_table_record *bps, int pages)
1398 {
1399 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1400 struct ras_err_handler_data *data;
1401 int ret = 0;
1402
1403 if (!con || !con->eh_data || !bps || pages <= 0)
1404 return 0;
1405
1406 mutex_lock(&con->recovery_lock);
1407 data = con->eh_data;
1408 if (!data)
1409 goto out;
1410
1411 if (data->space_left <= pages)
1412 if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) {
1413 ret = -ENOMEM;
1414 goto out;
1415 }
1416
1417 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps));
1418 data->count += pages;
1419 data->space_left -= pages;
1420
1421 out:
1422 mutex_unlock(&con->recovery_lock);
1423
1424 return ret;
1425 }
1426
1427 /*
1428 * write error record array to eeprom, the function should be
1429 * protected by recovery_lock
1430 */
1431 static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1432 {
1433 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1434 struct ras_err_handler_data *data;
1435 struct amdgpu_ras_eeprom_control *control;
1436 int save_count;
1437
1438 if (!con || !con->eh_data)
1439 return 0;
1440
1441 control = &con->eeprom_control;
1442 data = con->eh_data;
1443 save_count = data->count - control->num_recs;
1444 /* only new entries are saved */
1445 if (save_count > 0)
1446 if (amdgpu_ras_eeprom_process_recods(control,
1447 &data->bps[control->num_recs],
1448 true,
1449 save_count)) {
1450 DRM_ERROR("Failed to save EEPROM table data!");
1451 return -EIO;
1452 }
1453
1454 return 0;
1455 }
1456
1457 /*
1458 * read error record array in eeprom and reserve enough space for
1459 * storing new bad pages
1460 */
1461 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1462 {
1463 struct amdgpu_ras_eeprom_control *control =
1464 &adev->psp.ras.ras->eeprom_control;
1465 struct eeprom_table_record *bps = NULL;
1466 int ret = 0;
1467
1468 /* no bad page record, skip eeprom access */
1469 if (!control->num_recs)
1470 return ret;
1471
1472 bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1473 if (!bps)
1474 return -ENOMEM;
1475
1476 if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1477 control->num_recs)) {
1478 DRM_ERROR("Failed to load EEPROM table records!");
1479 ret = -EIO;
1480 goto out;
1481 }
1482
1483 ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1484
1485 out:
1486 kfree(bps);
1487 return ret;
1488 }
1489
1490 /*
1491 * check if an address belongs to bad page
1492 *
1493 * Note: this check is only for umc block
1494 */
1495 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1496 uint64_t addr)
1497 {
1498 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1499 struct ras_err_handler_data *data;
1500 int i;
1501 bool ret = false;
1502
1503 if (!con || !con->eh_data)
1504 return ret;
1505
1506 mutex_lock(&con->recovery_lock);
1507 data = con->eh_data;
1508 if (!data)
1509 goto out;
1510
1511 addr >>= AMDGPU_GPU_PAGE_SHIFT;
1512 for (i = 0; i < data->count; i++)
1513 if (addr == data->bps[i].retired_page) {
1514 ret = true;
1515 goto out;
1516 }
1517
1518 out:
1519 mutex_unlock(&con->recovery_lock);
1520 return ret;
1521 }
1522
1523 /* called in gpu recovery/init */
1524 int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
1525 {
1526 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1527 struct ras_err_handler_data *data;
1528 uint64_t bp;
1529 struct amdgpu_bo *bo = NULL;
1530 int i, ret = 0;
1531
1532 if (!con || !con->eh_data)
1533 return 0;
1534
1535 mutex_lock(&con->recovery_lock);
1536 data = con->eh_data;
1537 if (!data)
1538 goto out;
1539 /* reserve vram at driver post stage. */
1540 for (i = data->last_reserved; i < data->count; i++) {
1541 bp = data->bps[i].retired_page;
1542
1543 /* There are two cases of reserve error should be ignored:
1544 * 1) a ras bad page has been allocated (used by someone);
1545 * 2) a ras bad page has been reserved (duplicate error injection
1546 * for one page);
1547 */
1548 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
1549 AMDGPU_GPU_PAGE_SIZE,
1550 AMDGPU_GEM_DOMAIN_VRAM,
1551 &bo, NULL))
1552 DRM_WARN("RAS WARN: reserve vram for retired page %llx fail\n", bp);
1553
1554 data->bps_bo[i] = bo;
1555 data->last_reserved = i + 1;
1556 bo = NULL;
1557 }
1558
1559 /* continue to save bad pages to eeprom even reesrve_vram fails */
1560 ret = amdgpu_ras_save_bad_pages(adev);
1561 out:
1562 mutex_unlock(&con->recovery_lock);
1563 return ret;
1564 }
1565
1566 /* called when driver unload */
1567 static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev)
1568 {
1569 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1570 struct ras_err_handler_data *data;
1571 struct amdgpu_bo *bo;
1572 int i;
1573
1574 if (!con || !con->eh_data)
1575 return 0;
1576
1577 mutex_lock(&con->recovery_lock);
1578 data = con->eh_data;
1579 if (!data)
1580 goto out;
1581
1582 for (i = data->last_reserved - 1; i >= 0; i--) {
1583 bo = data->bps_bo[i];
1584
1585 amdgpu_bo_free_kernel(&bo, NULL, NULL);
1586
1587 data->bps_bo[i] = bo;
1588 data->last_reserved = i;
1589 }
1590 out:
1591 mutex_unlock(&con->recovery_lock);
1592 return 0;
1593 }
1594
1595 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1596 {
1597 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1598 struct ras_err_handler_data **data;
1599 int ret;
1600
1601 if (con)
1602 data = &con->eh_data;
1603 else
1604 return 0;
1605
1606 *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1607 if (!*data) {
1608 ret = -ENOMEM;
1609 goto out;
1610 }
1611
1612 mutex_init(&con->recovery_lock);
1613 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1614 atomic_set(&con->in_recovery, 0);
1615 con->adev = adev;
1616
1617 ret = amdgpu_ras_eeprom_init(&con->eeprom_control);
1618 if (ret)
1619 goto free;
1620
1621 if (con->eeprom_control.num_recs) {
1622 ret = amdgpu_ras_load_bad_pages(adev);
1623 if (ret)
1624 goto free;
1625 ret = amdgpu_ras_reserve_bad_pages(adev);
1626 if (ret)
1627 goto release;
1628 }
1629
1630 return 0;
1631
1632 release:
1633 amdgpu_ras_release_bad_pages(adev);
1634 free:
1635 kfree((*data)->bps);
1636 kfree((*data)->bps_bo);
1637 kfree(*data);
1638 con->eh_data = NULL;
1639 out:
1640 DRM_WARN("Failed to initialize ras recovery!\n");
1641
1642 return ret;
1643 }
1644
1645 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1646 {
1647 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1648 struct ras_err_handler_data *data = con->eh_data;
1649
1650 /* recovery_init failed to init it, fini is useless */
1651 if (!data)
1652 return 0;
1653
1654 cancel_work_sync(&con->recovery_work);
1655 amdgpu_ras_release_bad_pages(adev);
1656
1657 mutex_lock(&con->recovery_lock);
1658 con->eh_data = NULL;
1659 kfree(data->bps);
1660 kfree(data->bps_bo);
1661 kfree(data);
1662 mutex_unlock(&con->recovery_lock);
1663
1664 return 0;
1665 }
1666 /* recovery end */
1667
1668 /* return 0 if ras will reset gpu and repost.*/
1669 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
1670 unsigned int block)
1671 {
1672 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1673
1674 if (!ras)
1675 return -EINVAL;
1676
1677 ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
1678 return 0;
1679 }
1680
1681 /*
1682 * check hardware's ras ability which will be saved in hw_supported.
1683 * if hardware does not support ras, we can skip some ras initializtion and
1684 * forbid some ras operations from IP.
1685 * if software itself, say boot parameter, limit the ras ability. We still
1686 * need allow IP do some limited operations, like disable. In such case,
1687 * we have to initialize ras as normal. but need check if operation is
1688 * allowed or not in each function.
1689 */
1690 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
1691 uint32_t *hw_supported, uint32_t *supported)
1692 {
1693 *hw_supported = 0;
1694 *supported = 0;
1695
1696 if (amdgpu_sriov_vf(adev) ||
1697 (adev->asic_type != CHIP_VEGA20 &&
1698 adev->asic_type != CHIP_ARCTURUS))
1699 return;
1700
1701 if (adev->is_atom_fw &&
1702 (amdgpu_atomfirmware_mem_ecc_supported(adev) ||
1703 amdgpu_atomfirmware_sram_ecc_supported(adev)))
1704 *hw_supported = AMDGPU_RAS_BLOCK_MASK;
1705
1706 *supported = amdgpu_ras_enable == 0 ?
1707 0 : *hw_supported & amdgpu_ras_mask;
1708 }
1709
1710 int amdgpu_ras_init(struct amdgpu_device *adev)
1711 {
1712 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1713 int r;
1714
1715 if (con)
1716 return 0;
1717
1718 con = kmalloc(sizeof(struct amdgpu_ras) +
1719 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
1720 GFP_KERNEL|__GFP_ZERO);
1721 if (!con)
1722 return -ENOMEM;
1723
1724 con->objs = (struct ras_manager *)(con + 1);
1725
1726 amdgpu_ras_set_context(adev, con);
1727
1728 amdgpu_ras_check_supported(adev, &con->hw_supported,
1729 &con->supported);
1730 if (!con->hw_supported) {
1731 amdgpu_ras_set_context(adev, NULL);
1732 kfree(con);
1733 return 0;
1734 }
1735
1736 con->features = 0;
1737 INIT_LIST_HEAD(&con->head);
1738 /* Might need get this flag from vbios. */
1739 con->flags = RAS_DEFAULT_FLAGS;
1740
1741 if (adev->nbio.funcs->init_ras_controller_interrupt) {
1742 r = adev->nbio.funcs->init_ras_controller_interrupt(adev);
1743 if (r)
1744 return r;
1745 }
1746
1747 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) {
1748 r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev);
1749 if (r)
1750 return r;
1751 }
1752
1753 amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK;
1754
1755 if (amdgpu_ras_fs_init(adev))
1756 goto fs_out;
1757
1758 DRM_INFO("RAS INFO: ras initialized successfully, "
1759 "hardware ability[%x] ras_mask[%x]\n",
1760 con->hw_supported, con->supported);
1761 return 0;
1762 fs_out:
1763 amdgpu_ras_set_context(adev, NULL);
1764 kfree(con);
1765
1766 return -EINVAL;
1767 }
1768
1769 /* helper function to handle common stuff in ip late init phase */
1770 int amdgpu_ras_late_init(struct amdgpu_device *adev,
1771 struct ras_common_if *ras_block,
1772 struct ras_fs_if *fs_info,
1773 struct ras_ih_if *ih_info)
1774 {
1775 int r;
1776
1777 /* disable RAS feature per IP block if it is not supported */
1778 if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
1779 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
1780 return 0;
1781 }
1782
1783 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
1784 if (r) {
1785 if (r == -EAGAIN) {
1786 /* request gpu reset. will run again */
1787 amdgpu_ras_request_reset_on_boot(adev,
1788 ras_block->block);
1789 return 0;
1790 } else if (adev->in_suspend || adev->in_gpu_reset) {
1791 /* in resume phase, if fail to enable ras,
1792 * clean up all ras fs nodes, and disable ras */
1793 goto cleanup;
1794 } else
1795 return r;
1796 }
1797
1798 /* in resume phase, no need to create ras fs node */
1799 if (adev->in_suspend || adev->in_gpu_reset)
1800 return 0;
1801
1802 if (ih_info->cb) {
1803 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
1804 if (r)
1805 goto interrupt;
1806 }
1807
1808 amdgpu_ras_debugfs_create(adev, fs_info);
1809
1810 r = amdgpu_ras_sysfs_create(adev, fs_info);
1811 if (r)
1812 goto sysfs;
1813
1814 return 0;
1815 cleanup:
1816 amdgpu_ras_sysfs_remove(adev, ras_block);
1817 sysfs:
1818 amdgpu_ras_debugfs_remove(adev, ras_block);
1819 if (ih_info->cb)
1820 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
1821 interrupt:
1822 amdgpu_ras_feature_enable(adev, ras_block, 0);
1823 return r;
1824 }
1825
1826 /* helper function to remove ras fs node and interrupt handler */
1827 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
1828 struct ras_common_if *ras_block,
1829 struct ras_ih_if *ih_info)
1830 {
1831 if (!ras_block || !ih_info)
1832 return;
1833
1834 amdgpu_ras_sysfs_remove(adev, ras_block);
1835 amdgpu_ras_debugfs_remove(adev, ras_block);
1836 if (ih_info->cb)
1837 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
1838 amdgpu_ras_feature_enable(adev, ras_block, 0);
1839 }
1840
1841 /* do some init work after IP late init as dependence.
1842 * and it runs in resume/gpu reset/booting up cases.
1843 */
1844 void amdgpu_ras_resume(struct amdgpu_device *adev)
1845 {
1846 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1847 struct ras_manager *obj, *tmp;
1848
1849 if (!con)
1850 return;
1851
1852 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
1853 /* Set up all other IPs which are not implemented. There is a
1854 * tricky thing that IP's actual ras error type should be
1855 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
1856 * ERROR_NONE make sense anyway.
1857 */
1858 amdgpu_ras_enable_all_features(adev, 1);
1859
1860 /* We enable ras on all hw_supported block, but as boot
1861 * parameter might disable some of them and one or more IP has
1862 * not implemented yet. So we disable them on behalf.
1863 */
1864 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1865 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
1866 amdgpu_ras_feature_enable(adev, &obj->head, 0);
1867 /* there should be no any reference. */
1868 WARN_ON(alive_obj(obj));
1869 }
1870 }
1871 }
1872
1873 if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
1874 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
1875 /* setup ras obj state as disabled.
1876 * for init_by_vbios case.
1877 * if we want to enable ras, just enable it in a normal way.
1878 * If we want do disable it, need setup ras obj as enabled,
1879 * then issue another TA disable cmd.
1880 * See feature_enable_on_boot
1881 */
1882 amdgpu_ras_disable_all_features(adev, 1);
1883 amdgpu_ras_reset_gpu(adev);
1884 }
1885 }
1886
1887 void amdgpu_ras_suspend(struct amdgpu_device *adev)
1888 {
1889 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1890
1891 if (!con)
1892 return;
1893
1894 amdgpu_ras_disable_all_features(adev, 0);
1895 /* Make sure all ras objects are disabled. */
1896 if (con->features)
1897 amdgpu_ras_disable_all_features(adev, 1);
1898 }
1899
1900 /* do some fini work before IP fini as dependence */
1901 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
1902 {
1903 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1904
1905 if (!con)
1906 return 0;
1907
1908 /* Need disable ras on all IPs here before ip [hw/sw]fini */
1909 amdgpu_ras_disable_all_features(adev, 0);
1910 amdgpu_ras_recovery_fini(adev);
1911 return 0;
1912 }
1913
1914 int amdgpu_ras_fini(struct amdgpu_device *adev)
1915 {
1916 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1917
1918 if (!con)
1919 return 0;
1920
1921 amdgpu_ras_fs_fini(adev);
1922 amdgpu_ras_interrupt_remove_all(adev);
1923
1924 WARN(con->features, "Feature mask is not cleared");
1925
1926 if (con->features)
1927 amdgpu_ras_disable_all_features(adev, 1);
1928
1929 amdgpu_ras_set_context(adev, NULL);
1930 kfree(con);
1931
1932 return 0;
1933 }
1934
1935 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
1936 {
1937 uint32_t hw_supported, supported;
1938
1939 amdgpu_ras_check_supported(adev, &hw_supported, &supported);
1940 if (!hw_supported)
1941 return;
1942
1943 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
1944 DRM_WARN("RAS event of type ERREVENT_ATHUB_INTERRUPT detected!\n");
1945
1946 amdgpu_ras_reset_gpu(adev);
1947 }
1948 }
Linux with added FPC-III support