treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vce.c
blobceb0dbf685f172da1eceaf23f266656eff1d0549
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
25 * Authors: Christian König <christian.koenig@amd.com>
28 #include <linux/firmware.h>
29 #include <linux/module.h>
31 #include <drm/drm.h>
33 #include "amdgpu.h"
34 #include "amdgpu_pm.h"
35 #include "amdgpu_vce.h"
36 #include "cikd.h"
38 /* 1 second timeout */
39 #define VCE_IDLE_TIMEOUT msecs_to_jiffies(1000)
41 /* Firmware Names */
42 #ifdef CONFIG_DRM_AMDGPU_CIK
43 #define FIRMWARE_BONAIRE "amdgpu/bonaire_vce.bin"
44 #define FIRMWARE_KABINI "amdgpu/kabini_vce.bin"
45 #define FIRMWARE_KAVERI "amdgpu/kaveri_vce.bin"
46 #define FIRMWARE_HAWAII "amdgpu/hawaii_vce.bin"
47 #define FIRMWARE_MULLINS "amdgpu/mullins_vce.bin"
48 #endif
49 #define FIRMWARE_TONGA "amdgpu/tonga_vce.bin"
50 #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin"
51 #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin"
52 #define FIRMWARE_STONEY "amdgpu/stoney_vce.bin"
53 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_vce.bin"
54 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin"
55 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_vce.bin"
56 #define FIRMWARE_VEGAM "amdgpu/vegam_vce.bin"
58 #define FIRMWARE_VEGA10 "amdgpu/vega10_vce.bin"
59 #define FIRMWARE_VEGA12 "amdgpu/vega12_vce.bin"
60 #define FIRMWARE_VEGA20 "amdgpu/vega20_vce.bin"
62 #ifdef CONFIG_DRM_AMDGPU_CIK
63 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
64 MODULE_FIRMWARE(FIRMWARE_KABINI);
65 MODULE_FIRMWARE(FIRMWARE_KAVERI);
66 MODULE_FIRMWARE(FIRMWARE_HAWAII);
67 MODULE_FIRMWARE(FIRMWARE_MULLINS);
68 #endif
69 MODULE_FIRMWARE(FIRMWARE_TONGA);
70 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
71 MODULE_FIRMWARE(FIRMWARE_FIJI);
72 MODULE_FIRMWARE(FIRMWARE_STONEY);
73 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
74 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
75 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
76 MODULE_FIRMWARE(FIRMWARE_VEGAM);
78 MODULE_FIRMWARE(FIRMWARE_VEGA10);
79 MODULE_FIRMWARE(FIRMWARE_VEGA12);
80 MODULE_FIRMWARE(FIRMWARE_VEGA20);
82 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
83 static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
84 struct amdgpu_bo *bo,
85 struct dma_fence **fence);
86 static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
87 bool direct, struct dma_fence **fence);
89 /**
90 * amdgpu_vce_init - allocate memory, load vce firmware
92 * @adev: amdgpu_device pointer
94 * First step to get VCE online, allocate memory and load the firmware
96 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
98 const char *fw_name;
99 const struct common_firmware_header *hdr;
100 unsigned ucode_version, version_major, version_minor, binary_id;
101 int i, r;
103 switch (adev->asic_type) {
104 #ifdef CONFIG_DRM_AMDGPU_CIK
105 case CHIP_BONAIRE:
106 fw_name = FIRMWARE_BONAIRE;
107 break;
108 case CHIP_KAVERI:
109 fw_name = FIRMWARE_KAVERI;
110 break;
111 case CHIP_KABINI:
112 fw_name = FIRMWARE_KABINI;
113 break;
114 case CHIP_HAWAII:
115 fw_name = FIRMWARE_HAWAII;
116 break;
117 case CHIP_MULLINS:
118 fw_name = FIRMWARE_MULLINS;
119 break;
120 #endif
121 case CHIP_TONGA:
122 fw_name = FIRMWARE_TONGA;
123 break;
124 case CHIP_CARRIZO:
125 fw_name = FIRMWARE_CARRIZO;
126 break;
127 case CHIP_FIJI:
128 fw_name = FIRMWARE_FIJI;
129 break;
130 case CHIP_STONEY:
131 fw_name = FIRMWARE_STONEY;
132 break;
133 case CHIP_POLARIS10:
134 fw_name = FIRMWARE_POLARIS10;
135 break;
136 case CHIP_POLARIS11:
137 fw_name = FIRMWARE_POLARIS11;
138 break;
139 case CHIP_POLARIS12:
140 fw_name = FIRMWARE_POLARIS12;
141 break;
142 case CHIP_VEGAM:
143 fw_name = FIRMWARE_VEGAM;
144 break;
145 case CHIP_VEGA10:
146 fw_name = FIRMWARE_VEGA10;
147 break;
148 case CHIP_VEGA12:
149 fw_name = FIRMWARE_VEGA12;
150 break;
151 case CHIP_VEGA20:
152 fw_name = FIRMWARE_VEGA20;
153 break;
155 default:
156 return -EINVAL;
159 r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
160 if (r) {
161 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
162 fw_name);
163 return r;
166 r = amdgpu_ucode_validate(adev->vce.fw);
167 if (r) {
168 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
169 fw_name);
170 release_firmware(adev->vce.fw);
171 adev->vce.fw = NULL;
172 return r;
175 hdr = (const struct common_firmware_header *)adev->vce.fw->data;
177 ucode_version = le32_to_cpu(hdr->ucode_version);
178 version_major = (ucode_version >> 20) & 0xfff;
179 version_minor = (ucode_version >> 8) & 0xfff;
180 binary_id = ucode_version & 0xff;
181 DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
182 version_major, version_minor, binary_id);
183 adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
184 (binary_id << 8));
186 r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
187 AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo,
188 &adev->vce.gpu_addr, &adev->vce.cpu_addr);
189 if (r) {
190 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
191 return r;
194 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
195 atomic_set(&adev->vce.handles[i], 0);
196 adev->vce.filp[i] = NULL;
199 INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
200 mutex_init(&adev->vce.idle_mutex);
202 return 0;
206 * amdgpu_vce_fini - free memory
208 * @adev: amdgpu_device pointer
210 * Last step on VCE teardown, free firmware memory
212 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
214 unsigned i;
216 if (adev->vce.vcpu_bo == NULL)
217 return 0;
219 cancel_delayed_work_sync(&adev->vce.idle_work);
220 drm_sched_entity_destroy(&adev->vce.entity);
222 amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,
223 (void **)&adev->vce.cpu_addr);
225 for (i = 0; i < adev->vce.num_rings; i++)
226 amdgpu_ring_fini(&adev->vce.ring[i]);
228 release_firmware(adev->vce.fw);
229 mutex_destroy(&adev->vce.idle_mutex);
231 return 0;
235 * amdgpu_vce_entity_init - init entity
237 * @adev: amdgpu_device pointer
240 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
242 struct amdgpu_ring *ring;
243 struct drm_gpu_scheduler *sched;
244 int r;
246 ring = &adev->vce.ring[0];
247 sched = &ring->sched;
248 r = drm_sched_entity_init(&adev->vce.entity, DRM_SCHED_PRIORITY_NORMAL,
249 &sched, 1, NULL);
250 if (r != 0) {
251 DRM_ERROR("Failed setting up VCE run queue.\n");
252 return r;
255 return 0;
259 * amdgpu_vce_suspend - unpin VCE fw memory
261 * @adev: amdgpu_device pointer
264 int amdgpu_vce_suspend(struct amdgpu_device *adev)
266 int i;
268 cancel_delayed_work_sync(&adev->vce.idle_work);
270 if (adev->vce.vcpu_bo == NULL)
271 return 0;
273 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
274 if (atomic_read(&adev->vce.handles[i]))
275 break;
277 if (i == AMDGPU_MAX_VCE_HANDLES)
278 return 0;
280 /* TODO: suspending running encoding sessions isn't supported */
281 return -EINVAL;
285 * amdgpu_vce_resume - pin VCE fw memory
287 * @adev: amdgpu_device pointer
290 int amdgpu_vce_resume(struct amdgpu_device *adev)
292 void *cpu_addr;
293 const struct common_firmware_header *hdr;
294 unsigned offset;
295 int r;
297 if (adev->vce.vcpu_bo == NULL)
298 return -EINVAL;
300 r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
301 if (r) {
302 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
303 return r;
306 r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
307 if (r) {
308 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
309 dev_err(adev->dev, "(%d) VCE map failed\n", r);
310 return r;
313 hdr = (const struct common_firmware_header *)adev->vce.fw->data;
314 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
315 memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
316 adev->vce.fw->size - offset);
318 amdgpu_bo_kunmap(adev->vce.vcpu_bo);
320 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
322 return 0;
326 * amdgpu_vce_idle_work_handler - power off VCE
328 * @work: pointer to work structure
330 * power of VCE when it's not used any more
332 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
334 struct amdgpu_device *adev =
335 container_of(work, struct amdgpu_device, vce.idle_work.work);
336 unsigned i, count = 0;
338 for (i = 0; i < adev->vce.num_rings; i++)
339 count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);
341 if (count == 0) {
342 if (adev->pm.dpm_enabled) {
343 amdgpu_dpm_enable_vce(adev, false);
344 } else {
345 amdgpu_asic_set_vce_clocks(adev, 0, 0);
346 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
347 AMD_PG_STATE_GATE);
348 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
349 AMD_CG_STATE_GATE);
351 } else {
352 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
357 * amdgpu_vce_ring_begin_use - power up VCE
359 * @ring: amdgpu ring
361 * Make sure VCE is powerd up when we want to use it
363 void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
365 struct amdgpu_device *adev = ring->adev;
366 bool set_clocks;
368 if (amdgpu_sriov_vf(adev))
369 return;
371 mutex_lock(&adev->vce.idle_mutex);
372 set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
373 if (set_clocks) {
374 if (adev->pm.dpm_enabled) {
375 amdgpu_dpm_enable_vce(adev, true);
376 } else {
377 amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
378 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
379 AMD_CG_STATE_UNGATE);
380 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
381 AMD_PG_STATE_UNGATE);
385 mutex_unlock(&adev->vce.idle_mutex);
389 * amdgpu_vce_ring_end_use - power VCE down
391 * @ring: amdgpu ring
393 * Schedule work to power VCE down again
395 void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring)
397 if (!amdgpu_sriov_vf(ring->adev))
398 schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);
402 * amdgpu_vce_free_handles - free still open VCE handles
404 * @adev: amdgpu_device pointer
405 * @filp: drm file pointer
407 * Close all VCE handles still open by this file pointer
409 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
411 struct amdgpu_ring *ring = &adev->vce.ring[0];
412 int i, r;
413 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
414 uint32_t handle = atomic_read(&adev->vce.handles[i]);
416 if (!handle || adev->vce.filp[i] != filp)
417 continue;
419 r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
420 if (r)
421 DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
423 adev->vce.filp[i] = NULL;
424 atomic_set(&adev->vce.handles[i], 0);
429 * amdgpu_vce_get_create_msg - generate a VCE create msg
431 * @adev: amdgpu_device pointer
432 * @ring: ring we should submit the msg to
433 * @handle: VCE session handle to use
434 * @fence: optional fence to return
436 * Open up a stream for HW test
438 static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
439 struct amdgpu_bo *bo,
440 struct dma_fence **fence)
442 const unsigned ib_size_dw = 1024;
443 struct amdgpu_job *job;
444 struct amdgpu_ib *ib;
445 struct dma_fence *f = NULL;
446 uint64_t addr;
447 int i, r;
449 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
450 if (r)
451 return r;
453 ib = &job->ibs[0];
455 addr = amdgpu_bo_gpu_offset(bo);
457 /* stitch together an VCE create msg */
458 ib->length_dw = 0;
459 ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
460 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
461 ib->ptr[ib->length_dw++] = handle;
463 if ((ring->adev->vce.fw_version >> 24) >= 52)
464 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
465 else
466 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
467 ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
468 ib->ptr[ib->length_dw++] = 0x00000000;
469 ib->ptr[ib->length_dw++] = 0x00000042;
470 ib->ptr[ib->length_dw++] = 0x0000000a;
471 ib->ptr[ib->length_dw++] = 0x00000001;
472 ib->ptr[ib->length_dw++] = 0x00000080;
473 ib->ptr[ib->length_dw++] = 0x00000060;
474 ib->ptr[ib->length_dw++] = 0x00000100;
475 ib->ptr[ib->length_dw++] = 0x00000100;
476 ib->ptr[ib->length_dw++] = 0x0000000c;
477 ib->ptr[ib->length_dw++] = 0x00000000;
478 if ((ring->adev->vce.fw_version >> 24) >= 52) {
479 ib->ptr[ib->length_dw++] = 0x00000000;
480 ib->ptr[ib->length_dw++] = 0x00000000;
481 ib->ptr[ib->length_dw++] = 0x00000000;
482 ib->ptr[ib->length_dw++] = 0x00000000;
485 ib->ptr[ib->length_dw++] = 0x00000014; /* len */
486 ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
487 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
488 ib->ptr[ib->length_dw++] = addr;
489 ib->ptr[ib->length_dw++] = 0x00000001;
491 for (i = ib->length_dw; i < ib_size_dw; ++i)
492 ib->ptr[i] = 0x0;
494 r = amdgpu_job_submit_direct(job, ring, &f);
495 if (r)
496 goto err;
498 if (fence)
499 *fence = dma_fence_get(f);
500 dma_fence_put(f);
501 return 0;
503 err:
504 amdgpu_job_free(job);
505 return r;
509 * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
511 * @adev: amdgpu_device pointer
512 * @ring: ring we should submit the msg to
513 * @handle: VCE session handle to use
514 * @fence: optional fence to return
516 * Close up a stream for HW test or if userspace failed to do so
518 static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
519 bool direct, struct dma_fence **fence)
521 const unsigned ib_size_dw = 1024;
522 struct amdgpu_job *job;
523 struct amdgpu_ib *ib;
524 struct dma_fence *f = NULL;
525 int i, r;
527 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
528 if (r)
529 return r;
531 ib = &job->ibs[0];
533 /* stitch together an VCE destroy msg */
534 ib->length_dw = 0;
535 ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
536 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
537 ib->ptr[ib->length_dw++] = handle;
539 ib->ptr[ib->length_dw++] = 0x00000020; /* len */
540 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
541 ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
542 ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
543 ib->ptr[ib->length_dw++] = 0x00000000;
544 ib->ptr[ib->length_dw++] = 0x00000000;
545 ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
546 ib->ptr[ib->length_dw++] = 0x00000000;
548 ib->ptr[ib->length_dw++] = 0x00000008; /* len */
549 ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
551 for (i = ib->length_dw; i < ib_size_dw; ++i)
552 ib->ptr[i] = 0x0;
554 if (direct)
555 r = amdgpu_job_submit_direct(job, ring, &f);
556 else
557 r = amdgpu_job_submit(job, &ring->adev->vce.entity,
558 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
559 if (r)
560 goto err;
562 if (fence)
563 *fence = dma_fence_get(f);
564 dma_fence_put(f);
565 return 0;
567 err:
568 amdgpu_job_free(job);
569 return r;
573 * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary
575 * @p: parser context
576 * @lo: address of lower dword
577 * @hi: address of higher dword
578 * @size: minimum size
579 * @index: bs/fb index
581 * Make sure that no BO cross a 4GB boundary.
583 static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx,
584 int lo, int hi, unsigned size, int32_t index)
586 int64_t offset = ((uint64_t)size) * ((int64_t)index);
587 struct ttm_operation_ctx ctx = { false, false };
588 struct amdgpu_bo_va_mapping *mapping;
589 unsigned i, fpfn, lpfn;
590 struct amdgpu_bo *bo;
591 uint64_t addr;
592 int r;
594 addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
595 ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
596 if (index >= 0) {
597 addr += offset;
598 fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT;
599 lpfn = 0x100000000ULL >> PAGE_SHIFT;
600 } else {
601 fpfn = 0;
602 lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT;
605 r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
606 if (r) {
607 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
608 addr, lo, hi, size, index);
609 return r;
612 for (i = 0; i < bo->placement.num_placement; ++i) {
613 bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
614 bo->placements[i].lpfn = bo->placements[i].lpfn ?
615 min(bo->placements[i].lpfn, lpfn) : lpfn;
617 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
622 * amdgpu_vce_cs_reloc - command submission relocation
624 * @p: parser context
625 * @lo: address of lower dword
626 * @hi: address of higher dword
627 * @size: minimum size
629 * Patch relocation inside command stream with real buffer address
631 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
632 int lo, int hi, unsigned size, uint32_t index)
634 struct amdgpu_bo_va_mapping *mapping;
635 struct amdgpu_bo *bo;
636 uint64_t addr;
637 int r;
639 if (index == 0xffffffff)
640 index = 0;
642 addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
643 ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
644 addr += ((uint64_t)size) * ((uint64_t)index);
646 r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
647 if (r) {
648 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
649 addr, lo, hi, size, index);
650 return r;
653 if ((addr + (uint64_t)size) >
654 (mapping->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
655 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
656 addr, lo, hi);
657 return -EINVAL;
660 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
661 addr += amdgpu_bo_gpu_offset(bo);
662 addr -= ((uint64_t)size) * ((uint64_t)index);
664 amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));
665 amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));
667 return 0;
671 * amdgpu_vce_validate_handle - validate stream handle
673 * @p: parser context
674 * @handle: handle to validate
675 * @allocated: allocated a new handle?
677 * Validates the handle and return the found session index or -EINVAL
678 * we we don't have another free session index.
680 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
681 uint32_t handle, uint32_t *allocated)
683 unsigned i;
685 /* validate the handle */
686 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
687 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
688 if (p->adev->vce.filp[i] != p->filp) {
689 DRM_ERROR("VCE handle collision detected!\n");
690 return -EINVAL;
692 return i;
696 /* handle not found try to alloc a new one */
697 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
698 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
699 p->adev->vce.filp[i] = p->filp;
700 p->adev->vce.img_size[i] = 0;
701 *allocated |= 1 << i;
702 return i;
706 DRM_ERROR("No more free VCE handles!\n");
707 return -EINVAL;
711 * amdgpu_vce_cs_parse - parse and validate the command stream
713 * @p: parser context
716 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
718 struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
719 unsigned fb_idx = 0, bs_idx = 0;
720 int session_idx = -1;
721 uint32_t destroyed = 0;
722 uint32_t created = 0;
723 uint32_t allocated = 0;
724 uint32_t tmp, handle = 0;
725 uint32_t *size = &tmp;
726 unsigned idx;
727 int i, r = 0;
729 p->job->vm = NULL;
730 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
732 for (idx = 0; idx < ib->length_dw;) {
733 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
734 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
736 if ((len < 8) || (len & 3)) {
737 DRM_ERROR("invalid VCE command length (%d)!\n", len);
738 r = -EINVAL;
739 goto out;
742 switch (cmd) {
743 case 0x00000002: /* task info */
744 fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
745 bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
746 break;
748 case 0x03000001: /* encode */
749 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10,
750 idx + 9, 0, 0);
751 if (r)
752 goto out;
754 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12,
755 idx + 11, 0, 0);
756 if (r)
757 goto out;
758 break;
760 case 0x05000001: /* context buffer */
761 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
762 idx + 2, 0, 0);
763 if (r)
764 goto out;
765 break;
767 case 0x05000004: /* video bitstream buffer */
768 tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
769 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
770 tmp, bs_idx);
771 if (r)
772 goto out;
773 break;
775 case 0x05000005: /* feedback buffer */
776 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
777 4096, fb_idx);
778 if (r)
779 goto out;
780 break;
782 case 0x0500000d: /* MV buffer */
783 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
784 idx + 2, 0, 0);
785 if (r)
786 goto out;
788 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 8,
789 idx + 7, 0, 0);
790 if (r)
791 goto out;
792 break;
795 idx += len / 4;
798 for (idx = 0; idx < ib->length_dw;) {
799 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
800 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
802 switch (cmd) {
803 case 0x00000001: /* session */
804 handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
805 session_idx = amdgpu_vce_validate_handle(p, handle,
806 &allocated);
807 if (session_idx < 0) {
808 r = session_idx;
809 goto out;
811 size = &p->adev->vce.img_size[session_idx];
812 break;
814 case 0x00000002: /* task info */
815 fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
816 bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
817 break;
819 case 0x01000001: /* create */
820 created |= 1 << session_idx;
821 if (destroyed & (1 << session_idx)) {
822 destroyed &= ~(1 << session_idx);
823 allocated |= 1 << session_idx;
825 } else if (!(allocated & (1 << session_idx))) {
826 DRM_ERROR("Handle already in use!\n");
827 r = -EINVAL;
828 goto out;
831 *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
832 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
833 8 * 3 / 2;
834 break;
836 case 0x04000001: /* config extension */
837 case 0x04000002: /* pic control */
838 case 0x04000005: /* rate control */
839 case 0x04000007: /* motion estimation */
840 case 0x04000008: /* rdo */
841 case 0x04000009: /* vui */
842 case 0x05000002: /* auxiliary buffer */
843 case 0x05000009: /* clock table */
844 break;
846 case 0x0500000c: /* hw config */
847 switch (p->adev->asic_type) {
848 #ifdef CONFIG_DRM_AMDGPU_CIK
849 case CHIP_KAVERI:
850 case CHIP_MULLINS:
851 #endif
852 case CHIP_CARRIZO:
853 break;
854 default:
855 r = -EINVAL;
856 goto out;
858 break;
860 case 0x03000001: /* encode */
861 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
862 *size, 0);
863 if (r)
864 goto out;
866 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
867 *size / 3, 0);
868 if (r)
869 goto out;
870 break;
872 case 0x02000001: /* destroy */
873 destroyed |= 1 << session_idx;
874 break;
876 case 0x05000001: /* context buffer */
877 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
878 *size * 2, 0);
879 if (r)
880 goto out;
881 break;
883 case 0x05000004: /* video bitstream buffer */
884 tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
885 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
886 tmp, bs_idx);
887 if (r)
888 goto out;
889 break;
891 case 0x05000005: /* feedback buffer */
892 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
893 4096, fb_idx);
894 if (r)
895 goto out;
896 break;
898 case 0x0500000d: /* MV buffer */
899 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3,
900 idx + 2, *size, 0);
901 if (r)
902 goto out;
904 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 8,
905 idx + 7, *size / 12, 0);
906 if (r)
907 goto out;
908 break;
910 default:
911 DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
912 r = -EINVAL;
913 goto out;
916 if (session_idx == -1) {
917 DRM_ERROR("no session command at start of IB\n");
918 r = -EINVAL;
919 goto out;
922 idx += len / 4;
925 if (allocated & ~created) {
926 DRM_ERROR("New session without create command!\n");
927 r = -ENOENT;
930 out:
931 if (!r) {
932 /* No error, free all destroyed handle slots */
933 tmp = destroyed;
934 } else {
935 /* Error during parsing, free all allocated handle slots */
936 tmp = allocated;
939 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
940 if (tmp & (1 << i))
941 atomic_set(&p->adev->vce.handles[i], 0);
943 return r;
947 * amdgpu_vce_cs_parse_vm - parse the command stream in VM mode
949 * @p: parser context
952 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx)
954 struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
955 int session_idx = -1;
956 uint32_t destroyed = 0;
957 uint32_t created = 0;
958 uint32_t allocated = 0;
959 uint32_t tmp, handle = 0;
960 int i, r = 0, idx = 0;
962 while (idx < ib->length_dw) {
963 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
964 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
966 if ((len < 8) || (len & 3)) {
967 DRM_ERROR("invalid VCE command length (%d)!\n", len);
968 r = -EINVAL;
969 goto out;
972 switch (cmd) {
973 case 0x00000001: /* session */
974 handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
975 session_idx = amdgpu_vce_validate_handle(p, handle,
976 &allocated);
977 if (session_idx < 0) {
978 r = session_idx;
979 goto out;
981 break;
983 case 0x01000001: /* create */
984 created |= 1 << session_idx;
985 if (destroyed & (1 << session_idx)) {
986 destroyed &= ~(1 << session_idx);
987 allocated |= 1 << session_idx;
989 } else if (!(allocated & (1 << session_idx))) {
990 DRM_ERROR("Handle already in use!\n");
991 r = -EINVAL;
992 goto out;
995 break;
997 case 0x02000001: /* destroy */
998 destroyed |= 1 << session_idx;
999 break;
1001 default:
1002 break;
1005 if (session_idx == -1) {
1006 DRM_ERROR("no session command at start of IB\n");
1007 r = -EINVAL;
1008 goto out;
1011 idx += len / 4;
1014 if (allocated & ~created) {
1015 DRM_ERROR("New session without create command!\n");
1016 r = -ENOENT;
1019 out:
1020 if (!r) {
1021 /* No error, free all destroyed handle slots */
1022 tmp = destroyed;
1023 amdgpu_ib_free(p->adev, ib, NULL);
1024 } else {
1025 /* Error during parsing, free all allocated handle slots */
1026 tmp = allocated;
1029 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
1030 if (tmp & (1 << i))
1031 atomic_set(&p->adev->vce.handles[i], 0);
1033 return r;
1037 * amdgpu_vce_ring_emit_ib - execute indirect buffer
1039 * @ring: engine to use
1040 * @ib: the IB to execute
1043 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring,
1044 struct amdgpu_job *job,
1045 struct amdgpu_ib *ib,
1046 uint32_t flags)
1048 amdgpu_ring_write(ring, VCE_CMD_IB);
1049 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1050 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1051 amdgpu_ring_write(ring, ib->length_dw);
1055 * amdgpu_vce_ring_emit_fence - add a fence command to the ring
1057 * @ring: engine to use
1058 * @fence: the fence
1061 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1062 unsigned flags)
1064 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1066 amdgpu_ring_write(ring, VCE_CMD_FENCE);
1067 amdgpu_ring_write(ring, addr);
1068 amdgpu_ring_write(ring, upper_32_bits(addr));
1069 amdgpu_ring_write(ring, seq);
1070 amdgpu_ring_write(ring, VCE_CMD_TRAP);
1071 amdgpu_ring_write(ring, VCE_CMD_END);
1075 * amdgpu_vce_ring_test_ring - test if VCE ring is working
1077 * @ring: the engine to test on
1080 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
1082 struct amdgpu_device *adev = ring->adev;
1083 uint32_t rptr;
1084 unsigned i;
1085 int r, timeout = adev->usec_timeout;
1087 /* skip ring test for sriov*/
1088 if (amdgpu_sriov_vf(adev))
1089 return 0;
1091 r = amdgpu_ring_alloc(ring, 16);
1092 if (r)
1093 return r;
1095 rptr = amdgpu_ring_get_rptr(ring);
1097 amdgpu_ring_write(ring, VCE_CMD_END);
1098 amdgpu_ring_commit(ring);
1100 for (i = 0; i < timeout; i++) {
1101 if (amdgpu_ring_get_rptr(ring) != rptr)
1102 break;
1103 udelay(1);
1106 if (i >= timeout)
1107 r = -ETIMEDOUT;
1109 return r;
1113 * amdgpu_vce_ring_test_ib - test if VCE IBs are working
1115 * @ring: the engine to test on
1118 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1120 struct dma_fence *fence = NULL;
1121 struct amdgpu_bo *bo = NULL;
1122 long r;
1124 /* skip vce ring1/2 ib test for now, since it's not reliable */
1125 if (ring != &ring->adev->vce.ring[0])
1126 return 0;
1128 r = amdgpu_bo_create_reserved(ring->adev, 512, PAGE_SIZE,
1129 AMDGPU_GEM_DOMAIN_VRAM,
1130 &bo, NULL, NULL);
1131 if (r)
1132 return r;
1134 r = amdgpu_vce_get_create_msg(ring, 1, bo, NULL);
1135 if (r)
1136 goto error;
1138 r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
1139 if (r)
1140 goto error;
1142 r = dma_fence_wait_timeout(fence, false, timeout);
1143 if (r == 0)
1144 r = -ETIMEDOUT;
1145 else if (r > 0)
1146 r = 0;
1148 error:
1149 dma_fence_put(fence);
1150 amdgpu_bo_unreserve(bo);
1151 amdgpu_bo_unref(&bo);
1152 return r;