drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "amdgpu_vm.h"
  24 #include "amdgpu_job.h"
  25 #include "amdgpu_object.h"
  26 #include "amdgpu_trace.h"
  27
  28 #define AMDGPU_VM_SDMA_MIN_NUM_DW       256u
  29 #define AMDGPU_VM_SDMA_MAX_NUM_DW       (16u * 1024u)
  30
  31 /**
  32  * amdgpu_vm_sdma_map_table - make sure new PDs/PTs are GTT mapped
  33  *
  34  * @table: newly allocated or validated PD/PT
  35  */
  36 static int amdgpu_vm_sdma_map_table(struct amdgpu_bo *table)
  37 {
  38         int r;
  39
  40         r = amdgpu_ttm_alloc_gart(&table->tbo);
  41         if (r)
  42                 return r;
  43
  44         if (table->shadow)
  45                 r = amdgpu_ttm_alloc_gart(&table->shadow->tbo);
  46
  47         return r;
  48 }
  49
  50 /**
  51  * amdgpu_vm_sdma_prepare - prepare SDMA command submission
  52  *
  53  * @p: see amdgpu_vm_update_params definition
  54  * @owner: owner we need to sync to
  55  * @exclusive: exclusive move fence we need to sync to
  56  *
  57  * Returns:
  58  * Negativ errno, 0 for success.
  59  */
  60 static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
  61                                   void *owner, struct dma_fence *exclusive)
  62 {
  63         struct amdgpu_bo *root = p->vm->root.base.bo;
  64         unsigned int ndw = AMDGPU_VM_SDMA_MIN_NUM_DW;
  65         int r;
  66
  67         r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, &p->job);
  68         if (r)
  69                 return r;
  70
  71         p->num_dw_left = ndw;
  72
  73         /* Wait for moves to be completed */
  74         r = amdgpu_sync_fence(&p->job->sync, exclusive, false);
  75         if (r)
  76                 return r;
  77
  78         /* Don't wait for any submissions during page fault handling */
  79         if (p->direct)
  80                 return 0;
  81
  82         return amdgpu_sync_resv(p->adev, &p->job->sync, root->tbo.base.resv,
  83                                 owner, false);
  84 }
  85
  86 /**
  87  * amdgpu_vm_sdma_commit - commit SDMA command submission
  88  *
  89  * @p: see amdgpu_vm_update_params definition
  90  * @fence: resulting fence
  91  *
  92  * Returns:
  93  * Negativ errno, 0 for success.
  94  */
  95 static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
  96                                  struct dma_fence **fence)
  97 {
  98         struct amdgpu_ib *ib = p->job->ibs;
  99         struct drm_sched_entity *entity;
 100         struct dma_fence *f, *tmp;
 101         struct amdgpu_ring *ring;
 102         int r;
 103
 104         entity = p->direct ? &p->vm->direct : &p->vm->delayed;
 105         ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
 106
 107         WARN_ON(ib->length_dw == 0);
 108         amdgpu_ring_pad_ib(ring, ib);
 109         WARN_ON(ib->length_dw > p->num_dw_left);
 110         r = amdgpu_job_submit(p->job, entity, AMDGPU_FENCE_OWNER_VM, &f);
 111         if (r)
 112                 goto error;
 113
 114         tmp = dma_fence_get(f);
 115         if (p->direct)
 116                 swap(p->vm->last_direct, tmp);
 117         else
 118                 swap(p->vm->last_delayed, tmp);
 119         dma_fence_put(tmp);
 120
 121         if (fence && !p->direct)
 122                 swap(*fence, f);
 123         dma_fence_put(f);
 124         return 0;
 125
 126 error:
 127         amdgpu_job_free(p->job);
 128         return r;
 129 }
 130
 131 /**
 132  * amdgpu_vm_sdma_copy_ptes - copy the PTEs from mapping
 133  *
 134  * @p: see amdgpu_vm_update_params definition
 135  * @bo: PD/PT to update
 136  * @pe: addr of the page entry
 137  * @count: number of page entries to copy
 138  *
 139  * Traces the parameters and calls the DMA function to copy the PTEs.
 140  */
 141 static void amdgpu_vm_sdma_copy_ptes(struct amdgpu_vm_update_params *p,
 142                                      struct amdgpu_bo *bo, uint64_t pe,
 143                                      unsigned count)
 144 {
 145         struct amdgpu_ib *ib = p->job->ibs;
 146         uint64_t src = ib->gpu_addr;
 147
 148         src += p->num_dw_left * 4;
 149
 150         pe += amdgpu_bo_gpu_offset(bo);
 151         trace_amdgpu_vm_copy_ptes(pe, src, count, p->direct);
 152
 153         amdgpu_vm_copy_pte(p->adev, ib, pe, src, count);
 154 }
 155
 156 /**
 157  * amdgpu_vm_sdma_set_ptes - helper to call the right asic function
 158  *
 159  * @p: see amdgpu_vm_update_params definition
 160  * @bo: PD/PT to update
 161  * @pe: addr of the page entry
 162  * @addr: dst addr to write into pe
 163  * @count: number of page entries to update
 164  * @incr: increase next addr by incr bytes
 165  * @flags: hw access flags
 166  *
 167  * Traces the parameters and calls the right asic functions
 168  * to setup the page table using the DMA.
 169  */
 170 static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p,
 171                                     struct amdgpu_bo *bo, uint64_t pe,
 172                                     uint64_t addr, unsigned count,
 173                                     uint32_t incr, uint64_t flags)
 174 {
 175         struct amdgpu_ib *ib = p->job->ibs;
 176
 177         pe += amdgpu_bo_gpu_offset(bo);
 178         trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->direct);
 179         if (count < 3) {
 180                 amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags,
 181                                     count, incr);
 182         } else {
 183                 amdgpu_vm_set_pte_pde(p->adev, ib, pe, addr,
 184                                       count, incr, flags);
 185         }
 186 }
 187
 188 /**
 189  * amdgpu_vm_sdma_update - execute VM update
 190  *
 191  * @p: see amdgpu_vm_update_params definition
 192  * @bo: PD/PT to update
 193  * @pe: addr of the page entry
 194  * @addr: dst addr to write into pe
 195  * @count: number of page entries to update
 196  * @incr: increase next addr by incr bytes
 197  * @flags: hw access flags
 198  *
 199  * Reserve space in the IB, setup mapping buffer on demand and write commands to
 200  * the IB.
 201  */
 202 static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
 203                                  struct amdgpu_bo *bo, uint64_t pe,
 204                                  uint64_t addr, unsigned count, uint32_t incr,
 205                                  uint64_t flags)
 206 {
 207         unsigned int i, ndw, nptes;
 208         uint64_t *pte;
 209         int r;
 210
 211         do {
 212                 ndw = p->num_dw_left;
 213                 ndw -= p->job->ibs->length_dw;
 214
 215                 if (ndw < 32) {
 216                         r = amdgpu_vm_sdma_commit(p, NULL);
 217                         if (r)
 218                                 return r;
 219
 220                         /* estimate how many dw we need */
 221                         ndw = 32;
 222                         if (p->pages_addr)
 223                                 ndw += count * 2;
 224                         ndw = max(ndw, AMDGPU_VM_SDMA_MIN_NUM_DW);
 225                         ndw = min(ndw, AMDGPU_VM_SDMA_MAX_NUM_DW);
 226
 227                         r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, &p->job);
 228                         if (r)
 229                                 return r;
 230
 231                         p->num_dw_left = ndw;
 232                 }
 233
 234                 if (!p->pages_addr) {
 235                         /* set page commands needed */
 236                         if (bo->shadow)
 237                                 amdgpu_vm_sdma_set_ptes(p, bo->shadow, pe, addr,
 238                                                         count, incr, flags);
 239                         amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count,
 240                                                 incr, flags);
 241                         return 0;
 242                 }
 243
 244                 /* copy commands needed */
 245                 ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw *
 246                         (bo->shadow ? 2 : 1);
 247
 248                 /* for padding */
 249                 ndw -= 7;
 250
 251                 nptes = min(count, ndw / 2);
 252
 253                 /* Put the PTEs at the end of the IB. */
 254                 p->num_dw_left -= nptes * 2;
 255                 pte = (uint64_t *)&(p->job->ibs->ptr[p->num_dw_left]);
 256                 for (i = 0; i < nptes; ++i, addr += incr) {
 257                         pte[i] = amdgpu_vm_map_gart(p->pages_addr, addr);
 258                         pte[i] |= flags;
 259                 }
 260
 261                 if (bo->shadow)
 262                         amdgpu_vm_sdma_copy_ptes(p, bo->shadow, pe, nptes);
 263                 amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes);
 264
 265                 pe += nptes * 8;
 266                 count -= nptes;
 267         } while (count);
 268
 269         return 0;
 270 }
 271
 272 const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs = {
 273         .map_table = amdgpu_vm_sdma_map_table,
 274         .prepare = amdgpu_vm_sdma_prepare,
 275         .update = amdgpu_vm_sdma_update,
 276         .commit = amdgpu_vm_sdma_commit
 277 };