2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <drm/drm_fourcc.h>
25 #include <drm/drm_vblank.h>
28 #include "amdgpu_pm.h"
29 #include "amdgpu_i2c.h"
32 #include "amdgpu_atombios.h"
33 #include "atombios_crtc.h"
34 #include "atombios_encoders.h"
35 #include "amdgpu_pll.h"
36 #include "amdgpu_connectors.h"
37 #include "amdgpu_display.h"
38 #include "dce_v11_0.h"
40 #include "dce/dce_11_0_d.h"
41 #include "dce/dce_11_0_sh_mask.h"
42 #include "dce/dce_11_0_enum.h"
43 #include "oss/oss_3_0_d.h"
44 #include "oss/oss_3_0_sh_mask.h"
45 #include "gmc/gmc_8_1_d.h"
46 #include "gmc/gmc_8_1_sh_mask.h"
48 #include "ivsrcid/ivsrcid_vislands30.h"
50 static void dce_v11_0_set_display_funcs(struct amdgpu_device
*adev
);
51 static void dce_v11_0_set_irq_funcs(struct amdgpu_device
*adev
);
53 static const u32 crtc_offsets
[] =
55 CRTC0_REGISTER_OFFSET
,
56 CRTC1_REGISTER_OFFSET
,
57 CRTC2_REGISTER_OFFSET
,
58 CRTC3_REGISTER_OFFSET
,
59 CRTC4_REGISTER_OFFSET
,
60 CRTC5_REGISTER_OFFSET
,
64 static const u32 hpd_offsets
[] =
74 static const uint32_t dig_offsets
[] = {
92 } interrupt_status_offsets
[] = { {
93 .reg
= mmDISP_INTERRUPT_STATUS
,
94 .vblank
= DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK
,
95 .vline
= DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK
,
96 .hpd
= DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
98 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE
,
99 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK
,
100 .vline
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK
,
101 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
103 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE2
,
104 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK
,
105 .vline
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK
,
106 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
108 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE3
,
109 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK
,
110 .vline
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK
,
111 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
113 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE4
,
114 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK
,
115 .vline
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK
,
116 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
118 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE5
,
119 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK
,
120 .vline
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK
,
121 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
124 static const u32 cz_golden_settings_a11
[] =
126 mmCRTC_DOUBLE_BUFFER_CONTROL
, 0x00010101, 0x00010000,
127 mmFBC_MISC
, 0x1f311fff, 0x14300000,
130 static const u32 cz_mgcg_cgcg_init
[] =
132 mmXDMA_CLOCK_GATING_CNTL
, 0xffffffff, 0x00000100,
133 mmXDMA_MEM_POWER_CNTL
, 0x00000101, 0x00000000,
136 static const u32 stoney_golden_settings_a11
[] =
138 mmCRTC_DOUBLE_BUFFER_CONTROL
, 0x00010101, 0x00010000,
139 mmFBC_MISC
, 0x1f311fff, 0x14302000,
142 static const u32 polaris11_golden_settings_a11
[] =
144 mmDCI_CLK_CNTL
, 0x00000080, 0x00000000,
145 mmFBC_DEBUG_COMP
, 0x000000f0, 0x00000070,
146 mmFBC_DEBUG1
, 0xffffffff, 0x00000008,
147 mmFBC_MISC
, 0x9f313fff, 0x14302008,
148 mmHDMI_CONTROL
, 0x313f031f, 0x00000011,
151 static const u32 polaris10_golden_settings_a11
[] =
153 mmDCI_CLK_CNTL
, 0x00000080, 0x00000000,
154 mmFBC_DEBUG_COMP
, 0x000000f0, 0x00000070,
155 mmFBC_MISC
, 0x9f313fff, 0x14302008,
156 mmHDMI_CONTROL
, 0x313f031f, 0x00000011,
159 static void dce_v11_0_init_golden_registers(struct amdgpu_device
*adev
)
161 switch (adev
->asic_type
) {
163 amdgpu_device_program_register_sequence(adev
,
165 ARRAY_SIZE(cz_mgcg_cgcg_init
));
166 amdgpu_device_program_register_sequence(adev
,
167 cz_golden_settings_a11
,
168 ARRAY_SIZE(cz_golden_settings_a11
));
171 amdgpu_device_program_register_sequence(adev
,
172 stoney_golden_settings_a11
,
173 ARRAY_SIZE(stoney_golden_settings_a11
));
177 amdgpu_device_program_register_sequence(adev
,
178 polaris11_golden_settings_a11
,
179 ARRAY_SIZE(polaris11_golden_settings_a11
));
183 amdgpu_device_program_register_sequence(adev
,
184 polaris10_golden_settings_a11
,
185 ARRAY_SIZE(polaris10_golden_settings_a11
));
192 static u32
dce_v11_0_audio_endpt_rreg(struct amdgpu_device
*adev
,
193 u32 block_offset
, u32 reg
)
198 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
199 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
200 r
= RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
);
201 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
206 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device
*adev
,
207 u32 block_offset
, u32 reg
, u32 v
)
211 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
212 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
213 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
, v
);
214 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
217 static u32
dce_v11_0_vblank_get_counter(struct amdgpu_device
*adev
, int crtc
)
219 if (crtc
< 0 || crtc
>= adev
->mode_info
.num_crtc
)
222 return RREG32(mmCRTC_STATUS_FRAME_COUNT
+ crtc_offsets
[crtc
]);
225 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device
*adev
)
229 /* Enable pflip interrupts */
230 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
231 amdgpu_irq_get(adev
, &adev
->pageflip_irq
, i
);
234 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device
*adev
)
238 /* Disable pflip interrupts */
239 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
240 amdgpu_irq_put(adev
, &adev
->pageflip_irq
, i
);
244 * dce_v11_0_page_flip - pageflip callback.
246 * @adev: amdgpu_device pointer
247 * @crtc_id: crtc to cleanup pageflip on
248 * @crtc_base: new address of the crtc (GPU MC address)
250 * Triggers the actual pageflip by updating the primary
251 * surface base address.
253 static void dce_v11_0_page_flip(struct amdgpu_device
*adev
,
254 int crtc_id
, u64 crtc_base
, bool async
)
256 struct amdgpu_crtc
*amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
257 struct drm_framebuffer
*fb
= amdgpu_crtc
->base
.primary
->fb
;
260 /* flip immediate for async, default is vsync */
261 tmp
= RREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
262 tmp
= REG_SET_FIELD(tmp
, GRPH_FLIP_CONTROL
,
263 GRPH_SURFACE_UPDATE_IMMEDIATE_EN
, async
? 1 : 0);
264 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
266 WREG32(mmGRPH_PITCH
+ amdgpu_crtc
->crtc_offset
,
267 fb
->pitches
[0] / fb
->format
->cpp
[0]);
268 /* update the scanout addresses */
269 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
270 upper_32_bits(crtc_base
));
271 /* writing to the low address triggers the update */
272 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
273 lower_32_bits(crtc_base
));
275 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
);
278 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device
*adev
, int crtc
,
279 u32
*vbl
, u32
*position
)
281 if ((crtc
< 0) || (crtc
>= adev
->mode_info
.num_crtc
))
284 *vbl
= RREG32(mmCRTC_V_BLANK_START_END
+ crtc_offsets
[crtc
]);
285 *position
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
291 * dce_v11_0_hpd_sense - hpd sense callback.
293 * @adev: amdgpu_device pointer
294 * @hpd: hpd (hotplug detect) pin
296 * Checks if a digital monitor is connected (evergreen+).
297 * Returns true if connected, false if not connected.
299 static bool dce_v11_0_hpd_sense(struct amdgpu_device
*adev
,
300 enum amdgpu_hpd_id hpd
)
302 bool connected
= false;
304 if (hpd
>= adev
->mode_info
.num_hpd
)
307 if (RREG32(mmDC_HPD_INT_STATUS
+ hpd_offsets
[hpd
]) &
308 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
)
315 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
317 * @adev: amdgpu_device pointer
318 * @hpd: hpd (hotplug detect) pin
320 * Set the polarity of the hpd pin (evergreen+).
322 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device
*adev
,
323 enum amdgpu_hpd_id hpd
)
326 bool connected
= dce_v11_0_hpd_sense(adev
, hpd
);
328 if (hpd
>= adev
->mode_info
.num_hpd
)
331 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
333 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_POLARITY
, 0);
335 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_POLARITY
, 1);
336 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
340 * dce_v11_0_hpd_init - hpd setup callback.
342 * @adev: amdgpu_device pointer
344 * Setup the hpd pins used by the card (evergreen+).
345 * Enable the pin, set the polarity, and enable the hpd interrupts.
347 static void dce_v11_0_hpd_init(struct amdgpu_device
*adev
)
349 struct drm_device
*dev
= adev
->ddev
;
350 struct drm_connector
*connector
;
351 struct drm_connector_list_iter iter
;
354 drm_connector_list_iter_begin(dev
, &iter
);
355 drm_for_each_connector_iter(connector
, &iter
) {
356 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
358 if (amdgpu_connector
->hpd
.hpd
>= adev
->mode_info
.num_hpd
)
361 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
||
362 connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
363 /* don't try to enable hpd on eDP or LVDS avoid breaking the
364 * aux dp channel on imac and help (but not completely fix)
365 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
366 * also avoid interrupt storms during dpms.
368 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
]);
369 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 0);
370 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
], tmp
);
374 tmp
= RREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
]);
375 tmp
= REG_SET_FIELD(tmp
, DC_HPD_CONTROL
, DC_HPD_EN
, 1);
376 WREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
], tmp
);
378 tmp
= RREG32(mmDC_HPD_TOGGLE_FILT_CNTL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
]);
379 tmp
= REG_SET_FIELD(tmp
, DC_HPD_TOGGLE_FILT_CNTL
,
380 DC_HPD_CONNECT_INT_DELAY
,
381 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS
);
382 tmp
= REG_SET_FIELD(tmp
, DC_HPD_TOGGLE_FILT_CNTL
,
383 DC_HPD_DISCONNECT_INT_DELAY
,
384 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS
);
385 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
], tmp
);
387 dce_v11_0_hpd_set_polarity(adev
, amdgpu_connector
->hpd
.hpd
);
388 amdgpu_irq_get(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
390 drm_connector_list_iter_end(&iter
);
394 * dce_v11_0_hpd_fini - hpd tear down callback.
396 * @adev: amdgpu_device pointer
398 * Tear down the hpd pins used by the card (evergreen+).
399 * Disable the hpd interrupts.
401 static void dce_v11_0_hpd_fini(struct amdgpu_device
*adev
)
403 struct drm_device
*dev
= adev
->ddev
;
404 struct drm_connector
*connector
;
405 struct drm_connector_list_iter iter
;
408 drm_connector_list_iter_begin(dev
, &iter
);
409 drm_for_each_connector_iter(connector
, &iter
) {
410 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
412 if (amdgpu_connector
->hpd
.hpd
>= adev
->mode_info
.num_hpd
)
415 tmp
= RREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
]);
416 tmp
= REG_SET_FIELD(tmp
, DC_HPD_CONTROL
, DC_HPD_EN
, 0);
417 WREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[amdgpu_connector
->hpd
.hpd
], tmp
);
419 amdgpu_irq_put(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
421 drm_connector_list_iter_end(&iter
);
424 static u32
dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device
*adev
)
426 return mmDC_GPIO_HPD_A
;
429 static bool dce_v11_0_is_display_hung(struct amdgpu_device
*adev
)
435 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
436 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
437 if (REG_GET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
)) {
438 crtc_status
[i
] = RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
439 crtc_hung
|= (1 << i
);
443 for (j
= 0; j
< 10; j
++) {
444 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
445 if (crtc_hung
& (1 << i
)) {
446 tmp
= RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
447 if (tmp
!= crtc_status
[i
])
448 crtc_hung
&= ~(1 << i
);
459 static void dce_v11_0_set_vga_render_state(struct amdgpu_device
*adev
,
464 /* Lockout access through VGA aperture*/
465 tmp
= RREG32(mmVGA_HDP_CONTROL
);
467 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 0);
469 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 1);
470 WREG32(mmVGA_HDP_CONTROL
, tmp
);
472 /* disable VGA render */
473 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
475 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 1);
477 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
478 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
481 static int dce_v11_0_get_num_crtc (struct amdgpu_device
*adev
)
485 switch (adev
->asic_type
) {
506 void dce_v11_0_disable_dce(struct amdgpu_device
*adev
)
508 /*Disable VGA render and enabled crtc, if has DCE engine*/
509 if (amdgpu_atombios_has_dce_engine_info(adev
)) {
513 dce_v11_0_set_vga_render_state(adev
, false);
516 for (i
= 0; i
< dce_v11_0_get_num_crtc(adev
); i
++) {
517 crtc_enabled
= REG_GET_FIELD(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]),
518 CRTC_CONTROL
, CRTC_MASTER_EN
);
520 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
521 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
522 tmp
= REG_SET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
, 0);
523 WREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
524 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
530 static void dce_v11_0_program_fmt(struct drm_encoder
*encoder
)
532 struct drm_device
*dev
= encoder
->dev
;
533 struct amdgpu_device
*adev
= dev
->dev_private
;
534 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
535 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
536 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
539 enum amdgpu_connector_dither dither
= AMDGPU_FMT_DITHER_DISABLE
;
542 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
543 bpc
= amdgpu_connector_get_monitor_bpc(connector
);
544 dither
= amdgpu_connector
->dither
;
547 /* LVDS/eDP FMT is set up by atom */
548 if (amdgpu_encoder
->devices
& ATOM_DEVICE_LCD_SUPPORT
)
551 /* not needed for analog */
552 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
) ||
553 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
))
561 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
562 /* XXX sort out optimal dither settings */
563 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
564 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
565 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
566 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 0);
568 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
569 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 0);
573 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
574 /* XXX sort out optimal dither settings */
575 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
576 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
577 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_RGB_RANDOM_ENABLE
, 1);
578 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
579 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 1);
581 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
582 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 1);
586 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
587 /* XXX sort out optimal dither settings */
588 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
589 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
590 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_RGB_RANDOM_ENABLE
, 1);
591 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
592 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 2);
594 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
595 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 2);
603 WREG32(mmFMT_BIT_DEPTH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
607 /* display watermark setup */
609 * dce_v11_0_line_buffer_adjust - Set up the line buffer
611 * @adev: amdgpu_device pointer
612 * @amdgpu_crtc: the selected display controller
613 * @mode: the current display mode on the selected display
616 * Setup up the line buffer allocation for
617 * the selected display controller (CIK).
618 * Returns the line buffer size in pixels.
620 static u32
dce_v11_0_line_buffer_adjust(struct amdgpu_device
*adev
,
621 struct amdgpu_crtc
*amdgpu_crtc
,
622 struct drm_display_mode
*mode
)
624 u32 tmp
, buffer_alloc
, i
, mem_cfg
;
625 u32 pipe_offset
= amdgpu_crtc
->crtc_id
;
628 * There are 6 line buffers, one for each display controllers.
629 * There are 3 partitions per LB. Select the number of partitions
630 * to enable based on the display width. For display widths larger
631 * than 4096, you need use to use 2 display controllers and combine
632 * them using the stereo blender.
634 if (amdgpu_crtc
->base
.enabled
&& mode
) {
635 if (mode
->crtc_hdisplay
< 1920) {
638 } else if (mode
->crtc_hdisplay
< 2560) {
641 } else if (mode
->crtc_hdisplay
< 4096) {
643 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
645 DRM_DEBUG_KMS("Mode too big for LB!\n");
647 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
654 tmp
= RREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
);
655 tmp
= REG_SET_FIELD(tmp
, LB_MEMORY_CTRL
, LB_MEMORY_CONFIG
, mem_cfg
);
656 WREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
, tmp
);
658 tmp
= RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
);
659 tmp
= REG_SET_FIELD(tmp
, PIPE0_DMIF_BUFFER_CONTROL
, DMIF_BUFFERS_ALLOCATED
, buffer_alloc
);
660 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
, tmp
);
662 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
663 tmp
= RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
);
664 if (REG_GET_FIELD(tmp
, PIPE0_DMIF_BUFFER_CONTROL
, DMIF_BUFFERS_ALLOCATION_COMPLETED
))
669 if (amdgpu_crtc
->base
.enabled
&& mode
) {
681 /* controller not enabled, so no lb used */
686 * cik_get_number_of_dram_channels - get the number of dram channels
688 * @adev: amdgpu_device pointer
690 * Look up the number of video ram channels (CIK).
691 * Used for display watermark bandwidth calculations
692 * Returns the number of dram channels
694 static u32
cik_get_number_of_dram_channels(struct amdgpu_device
*adev
)
696 u32 tmp
= RREG32(mmMC_SHARED_CHMAP
);
698 switch (REG_GET_FIELD(tmp
, MC_SHARED_CHMAP
, NOOFCHAN
)) {
721 struct dce10_wm_params
{
722 u32 dram_channels
; /* number of dram channels */
723 u32 yclk
; /* bandwidth per dram data pin in kHz */
724 u32 sclk
; /* engine clock in kHz */
725 u32 disp_clk
; /* display clock in kHz */
726 u32 src_width
; /* viewport width */
727 u32 active_time
; /* active display time in ns */
728 u32 blank_time
; /* blank time in ns */
729 bool interlaced
; /* mode is interlaced */
730 fixed20_12 vsc
; /* vertical scale ratio */
731 u32 num_heads
; /* number of active crtcs */
732 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
733 u32 lb_size
; /* line buffer allocated to pipe */
734 u32 vtaps
; /* vertical scaler taps */
738 * dce_v11_0_dram_bandwidth - get the dram bandwidth
740 * @wm: watermark calculation data
742 * Calculate the raw dram bandwidth (CIK).
743 * Used for display watermark bandwidth calculations
744 * Returns the dram bandwidth in MBytes/s
746 static u32
dce_v11_0_dram_bandwidth(struct dce10_wm_params
*wm
)
748 /* Calculate raw DRAM Bandwidth */
749 fixed20_12 dram_efficiency
; /* 0.7 */
750 fixed20_12 yclk
, dram_channels
, bandwidth
;
753 a
.full
= dfixed_const(1000);
754 yclk
.full
= dfixed_const(wm
->yclk
);
755 yclk
.full
= dfixed_div(yclk
, a
);
756 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
757 a
.full
= dfixed_const(10);
758 dram_efficiency
.full
= dfixed_const(7);
759 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
760 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
761 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
763 return dfixed_trunc(bandwidth
);
767 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
769 * @wm: watermark calculation data
771 * Calculate the dram bandwidth used for display (CIK).
772 * Used for display watermark bandwidth calculations
773 * Returns the dram bandwidth for display in MBytes/s
775 static u32
dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params
*wm
)
777 /* Calculate DRAM Bandwidth and the part allocated to display. */
778 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
779 fixed20_12 yclk
, dram_channels
, bandwidth
;
782 a
.full
= dfixed_const(1000);
783 yclk
.full
= dfixed_const(wm
->yclk
);
784 yclk
.full
= dfixed_div(yclk
, a
);
785 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
786 a
.full
= dfixed_const(10);
787 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
788 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
789 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
790 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
792 return dfixed_trunc(bandwidth
);
796 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
798 * @wm: watermark calculation data
800 * Calculate the data return bandwidth used for display (CIK).
801 * Used for display watermark bandwidth calculations
802 * Returns the data return bandwidth in MBytes/s
804 static u32
dce_v11_0_data_return_bandwidth(struct dce10_wm_params
*wm
)
806 /* Calculate the display Data return Bandwidth */
807 fixed20_12 return_efficiency
; /* 0.8 */
808 fixed20_12 sclk
, bandwidth
;
811 a
.full
= dfixed_const(1000);
812 sclk
.full
= dfixed_const(wm
->sclk
);
813 sclk
.full
= dfixed_div(sclk
, a
);
814 a
.full
= dfixed_const(10);
815 return_efficiency
.full
= dfixed_const(8);
816 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
817 a
.full
= dfixed_const(32);
818 bandwidth
.full
= dfixed_mul(a
, sclk
);
819 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
821 return dfixed_trunc(bandwidth
);
825 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
827 * @wm: watermark calculation data
829 * Calculate the dmif bandwidth used for display (CIK).
830 * Used for display watermark bandwidth calculations
831 * Returns the dmif bandwidth in MBytes/s
833 static u32
dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params
*wm
)
835 /* Calculate the DMIF Request Bandwidth */
836 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
837 fixed20_12 disp_clk
, bandwidth
;
840 a
.full
= dfixed_const(1000);
841 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
842 disp_clk
.full
= dfixed_div(disp_clk
, a
);
843 a
.full
= dfixed_const(32);
844 b
.full
= dfixed_mul(a
, disp_clk
);
846 a
.full
= dfixed_const(10);
847 disp_clk_request_efficiency
.full
= dfixed_const(8);
848 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
850 bandwidth
.full
= dfixed_mul(b
, disp_clk_request_efficiency
);
852 return dfixed_trunc(bandwidth
);
856 * dce_v11_0_available_bandwidth - get the min available bandwidth
858 * @wm: watermark calculation data
860 * Calculate the min available bandwidth used for display (CIK).
861 * Used for display watermark bandwidth calculations
862 * Returns the min available bandwidth in MBytes/s
864 static u32
dce_v11_0_available_bandwidth(struct dce10_wm_params
*wm
)
866 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
867 u32 dram_bandwidth
= dce_v11_0_dram_bandwidth(wm
);
868 u32 data_return_bandwidth
= dce_v11_0_data_return_bandwidth(wm
);
869 u32 dmif_req_bandwidth
= dce_v11_0_dmif_request_bandwidth(wm
);
871 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
875 * dce_v11_0_average_bandwidth - get the average available bandwidth
877 * @wm: watermark calculation data
879 * Calculate the average available bandwidth used for display (CIK).
880 * Used for display watermark bandwidth calculations
881 * Returns the average available bandwidth in MBytes/s
883 static u32
dce_v11_0_average_bandwidth(struct dce10_wm_params
*wm
)
885 /* Calculate the display mode Average Bandwidth
886 * DisplayMode should contain the source and destination dimensions,
890 fixed20_12 line_time
;
891 fixed20_12 src_width
;
892 fixed20_12 bandwidth
;
895 a
.full
= dfixed_const(1000);
896 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
897 line_time
.full
= dfixed_div(line_time
, a
);
898 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
899 src_width
.full
= dfixed_const(wm
->src_width
);
900 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
901 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
902 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
904 return dfixed_trunc(bandwidth
);
908 * dce_v11_0_latency_watermark - get the latency watermark
910 * @wm: watermark calculation data
912 * Calculate the latency watermark (CIK).
913 * Used for display watermark bandwidth calculations
914 * Returns the latency watermark in ns
916 static u32
dce_v11_0_latency_watermark(struct dce10_wm_params
*wm
)
918 /* First calculate the latency in ns */
919 u32 mc_latency
= 2000; /* 2000 ns. */
920 u32 available_bandwidth
= dce_v11_0_available_bandwidth(wm
);
921 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
922 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
923 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
924 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
925 (wm
->num_heads
* cursor_line_pair_return_time
);
926 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
927 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
928 u32 tmp
, dmif_size
= 12288;
931 if (wm
->num_heads
== 0)
934 a
.full
= dfixed_const(2);
935 b
.full
= dfixed_const(1);
936 if ((wm
->vsc
.full
> a
.full
) ||
937 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
939 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
940 max_src_lines_per_dst_line
= 4;
942 max_src_lines_per_dst_line
= 2;
944 a
.full
= dfixed_const(available_bandwidth
);
945 b
.full
= dfixed_const(wm
->num_heads
);
946 a
.full
= dfixed_div(a
, b
);
947 tmp
= div_u64((u64
) dmif_size
* (u64
) wm
->disp_clk
, mc_latency
+ 512);
948 tmp
= min(dfixed_trunc(a
), tmp
);
950 lb_fill_bw
= min(tmp
, wm
->disp_clk
* wm
->bytes_per_pixel
/ 1000);
952 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
953 b
.full
= dfixed_const(1000);
954 c
.full
= dfixed_const(lb_fill_bw
);
955 b
.full
= dfixed_div(c
, b
);
956 a
.full
= dfixed_div(a
, b
);
957 line_fill_time
= dfixed_trunc(a
);
959 if (line_fill_time
< wm
->active_time
)
962 return latency
+ (line_fill_time
- wm
->active_time
);
967 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
968 * average and available dram bandwidth
970 * @wm: watermark calculation data
972 * Check if the display average bandwidth fits in the display
973 * dram bandwidth (CIK).
974 * Used for display watermark bandwidth calculations
975 * Returns true if the display fits, false if not.
977 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params
*wm
)
979 if (dce_v11_0_average_bandwidth(wm
) <=
980 (dce_v11_0_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
987 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
988 * average and available bandwidth
990 * @wm: watermark calculation data
992 * Check if the display average bandwidth fits in the display
993 * available bandwidth (CIK).
994 * Used for display watermark bandwidth calculations
995 * Returns true if the display fits, false if not.
997 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params
*wm
)
999 if (dce_v11_0_average_bandwidth(wm
) <=
1000 (dce_v11_0_available_bandwidth(wm
) / wm
->num_heads
))
1007 * dce_v11_0_check_latency_hiding - check latency hiding
1009 * @wm: watermark calculation data
1011 * Check latency hiding (CIK).
1012 * Used for display watermark bandwidth calculations
1013 * Returns true if the display fits, false if not.
1015 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params
*wm
)
1017 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
1018 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
1019 u32 latency_tolerant_lines
;
1023 a
.full
= dfixed_const(1);
1024 if (wm
->vsc
.full
> a
.full
)
1025 latency_tolerant_lines
= 1;
1027 if (lb_partitions
<= (wm
->vtaps
+ 1))
1028 latency_tolerant_lines
= 1;
1030 latency_tolerant_lines
= 2;
1033 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
1035 if (dce_v11_0_latency_watermark(wm
) <= latency_hiding
)
1042 * dce_v11_0_program_watermarks - program display watermarks
1044 * @adev: amdgpu_device pointer
1045 * @amdgpu_crtc: the selected display controller
1046 * @lb_size: line buffer size
1047 * @num_heads: number of display controllers in use
1049 * Calculate and program the display watermarks for the
1050 * selected display controller (CIK).
1052 static void dce_v11_0_program_watermarks(struct amdgpu_device
*adev
,
1053 struct amdgpu_crtc
*amdgpu_crtc
,
1054 u32 lb_size
, u32 num_heads
)
1056 struct drm_display_mode
*mode
= &amdgpu_crtc
->base
.mode
;
1057 struct dce10_wm_params wm_low
, wm_high
;
1060 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
1061 u32 tmp
, wm_mask
, lb_vblank_lead_lines
= 0;
1063 if (amdgpu_crtc
->base
.enabled
&& num_heads
&& mode
) {
1064 active_time
= (u32
) div_u64((u64
)mode
->crtc_hdisplay
* 1000000,
1066 line_time
= (u32
) div_u64((u64
)mode
->crtc_htotal
* 1000000,
1068 line_time
= min(line_time
, (u32
)65535);
1070 /* watermark for high clocks */
1071 if (adev
->pm
.dpm_enabled
) {
1073 amdgpu_dpm_get_mclk(adev
, false) * 10;
1075 amdgpu_dpm_get_sclk(adev
, false) * 10;
1077 wm_high
.yclk
= adev
->pm
.current_mclk
* 10;
1078 wm_high
.sclk
= adev
->pm
.current_sclk
* 10;
1081 wm_high
.disp_clk
= mode
->clock
;
1082 wm_high
.src_width
= mode
->crtc_hdisplay
;
1083 wm_high
.active_time
= active_time
;
1084 wm_high
.blank_time
= line_time
- wm_high
.active_time
;
1085 wm_high
.interlaced
= false;
1086 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1087 wm_high
.interlaced
= true;
1088 wm_high
.vsc
= amdgpu_crtc
->vsc
;
1090 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1092 wm_high
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1093 wm_high
.lb_size
= lb_size
;
1094 wm_high
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1095 wm_high
.num_heads
= num_heads
;
1097 /* set for high clocks */
1098 latency_watermark_a
= min(dce_v11_0_latency_watermark(&wm_high
), (u32
)65535);
1100 /* possibly force display priority to high */
1101 /* should really do this at mode validation time... */
1102 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high
) ||
1103 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high
) ||
1104 !dce_v11_0_check_latency_hiding(&wm_high
) ||
1105 (adev
->mode_info
.disp_priority
== 2)) {
1106 DRM_DEBUG_KMS("force priority to high\n");
1109 /* watermark for low clocks */
1110 if (adev
->pm
.dpm_enabled
) {
1112 amdgpu_dpm_get_mclk(adev
, true) * 10;
1114 amdgpu_dpm_get_sclk(adev
, true) * 10;
1116 wm_low
.yclk
= adev
->pm
.current_mclk
* 10;
1117 wm_low
.sclk
= adev
->pm
.current_sclk
* 10;
1120 wm_low
.disp_clk
= mode
->clock
;
1121 wm_low
.src_width
= mode
->crtc_hdisplay
;
1122 wm_low
.active_time
= active_time
;
1123 wm_low
.blank_time
= line_time
- wm_low
.active_time
;
1124 wm_low
.interlaced
= false;
1125 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1126 wm_low
.interlaced
= true;
1127 wm_low
.vsc
= amdgpu_crtc
->vsc
;
1129 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1131 wm_low
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1132 wm_low
.lb_size
= lb_size
;
1133 wm_low
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1134 wm_low
.num_heads
= num_heads
;
1136 /* set for low clocks */
1137 latency_watermark_b
= min(dce_v11_0_latency_watermark(&wm_low
), (u32
)65535);
1139 /* possibly force display priority to high */
1140 /* should really do this at mode validation time... */
1141 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low
) ||
1142 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low
) ||
1143 !dce_v11_0_check_latency_hiding(&wm_low
) ||
1144 (adev
->mode_info
.disp_priority
== 2)) {
1145 DRM_DEBUG_KMS("force priority to high\n");
1147 lb_vblank_lead_lines
= DIV_ROUND_UP(lb_size
, mode
->crtc_hdisplay
);
1151 wm_mask
= RREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1152 tmp
= REG_SET_FIELD(wm_mask
, DPG_WATERMARK_MASK_CONTROL
, URGENCY_WATERMARK_MASK
, 1);
1153 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1154 tmp
= RREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1155 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_LOW_WATERMARK
, latency_watermark_a
);
1156 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_HIGH_WATERMARK
, line_time
);
1157 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1159 tmp
= REG_SET_FIELD(wm_mask
, DPG_WATERMARK_MASK_CONTROL
, URGENCY_WATERMARK_MASK
, 2);
1160 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1161 tmp
= RREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1162 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_LOW_WATERMARK
, latency_watermark_b
);
1163 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_HIGH_WATERMARK
, line_time
);
1164 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1165 /* restore original selection */
1166 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, wm_mask
);
1168 /* save values for DPM */
1169 amdgpu_crtc
->line_time
= line_time
;
1170 amdgpu_crtc
->wm_high
= latency_watermark_a
;
1171 amdgpu_crtc
->wm_low
= latency_watermark_b
;
1172 /* Save number of lines the linebuffer leads before the scanout */
1173 amdgpu_crtc
->lb_vblank_lead_lines
= lb_vblank_lead_lines
;
1177 * dce_v11_0_bandwidth_update - program display watermarks
1179 * @adev: amdgpu_device pointer
1181 * Calculate and program the display watermarks and line
1182 * buffer allocation (CIK).
1184 static void dce_v11_0_bandwidth_update(struct amdgpu_device
*adev
)
1186 struct drm_display_mode
*mode
= NULL
;
1187 u32 num_heads
= 0, lb_size
;
1190 amdgpu_display_update_priority(adev
);
1192 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1193 if (adev
->mode_info
.crtcs
[i
]->base
.enabled
)
1196 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1197 mode
= &adev
->mode_info
.crtcs
[i
]->base
.mode
;
1198 lb_size
= dce_v11_0_line_buffer_adjust(adev
, adev
->mode_info
.crtcs
[i
], mode
);
1199 dce_v11_0_program_watermarks(adev
, adev
->mode_info
.crtcs
[i
],
1200 lb_size
, num_heads
);
1204 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device
*adev
)
1209 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1210 offset
= adev
->mode_info
.audio
.pin
[i
].offset
;
1211 tmp
= RREG32_AUDIO_ENDPT(offset
,
1212 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
);
1214 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
) >>
1215 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
) == 1)
1216 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1218 adev
->mode_info
.audio
.pin
[i
].connected
= true;
1222 static struct amdgpu_audio_pin
*dce_v11_0_audio_get_pin(struct amdgpu_device
*adev
)
1226 dce_v11_0_audio_get_connected_pins(adev
);
1228 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1229 if (adev
->mode_info
.audio
.pin
[i
].connected
)
1230 return &adev
->mode_info
.audio
.pin
[i
];
1232 DRM_ERROR("No connected audio pins found!\n");
1236 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder
*encoder
)
1238 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1239 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1240 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1243 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1246 tmp
= RREG32(mmAFMT_AUDIO_SRC_CONTROL
+ dig
->afmt
->offset
);
1247 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_SRC_CONTROL
, AFMT_AUDIO_SRC_SELECT
, dig
->afmt
->pin
->id
);
1248 WREG32(mmAFMT_AUDIO_SRC_CONTROL
+ dig
->afmt
->offset
, tmp
);
1251 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder
*encoder
,
1252 struct drm_display_mode
*mode
)
1254 struct drm_device
*dev
= encoder
->dev
;
1255 struct amdgpu_device
*adev
= dev
->dev_private
;
1256 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1257 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1258 struct drm_connector
*connector
;
1259 struct drm_connector_list_iter iter
;
1260 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1264 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1267 drm_connector_list_iter_begin(dev
, &iter
);
1268 drm_for_each_connector_iter(connector
, &iter
) {
1269 if (connector
->encoder
== encoder
) {
1270 amdgpu_connector
= to_amdgpu_connector(connector
);
1274 drm_connector_list_iter_end(&iter
);
1276 if (!amdgpu_connector
) {
1277 DRM_ERROR("Couldn't find encoder's connector\n");
1281 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1283 if (connector
->latency_present
[interlace
]) {
1284 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1285 VIDEO_LIPSYNC
, connector
->video_latency
[interlace
]);
1286 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1287 AUDIO_LIPSYNC
, connector
->audio_latency
[interlace
]);
1289 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1291 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1294 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1295 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
, tmp
);
1298 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder
*encoder
)
1300 struct drm_device
*dev
= encoder
->dev
;
1301 struct amdgpu_device
*adev
= dev
->dev_private
;
1302 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1303 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1304 struct drm_connector
*connector
;
1305 struct drm_connector_list_iter iter
;
1306 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1311 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1314 drm_connector_list_iter_begin(dev
, &iter
);
1315 drm_for_each_connector_iter(connector
, &iter
) {
1316 if (connector
->encoder
== encoder
) {
1317 amdgpu_connector
= to_amdgpu_connector(connector
);
1321 drm_connector_list_iter_end(&iter
);
1323 if (!amdgpu_connector
) {
1324 DRM_ERROR("Couldn't find encoder's connector\n");
1328 sad_count
= drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector
), &sadb
);
1329 if (sad_count
< 0) {
1330 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count
);
1334 /* program the speaker allocation */
1335 tmp
= RREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1336 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
);
1337 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1340 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1341 HDMI_CONNECTION
, 1);
1343 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1344 SPEAKER_ALLOCATION
, sadb
[0]);
1346 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1347 SPEAKER_ALLOCATION
, 5); /* stereo */
1348 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1349 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
, tmp
);
1354 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder
*encoder
)
1356 struct drm_device
*dev
= encoder
->dev
;
1357 struct amdgpu_device
*adev
= dev
->dev_private
;
1358 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1359 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1360 struct drm_connector
*connector
;
1361 struct drm_connector_list_iter iter
;
1362 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1363 struct cea_sad
*sads
;
1366 static const u16 eld_reg_to_type
[][2] = {
1367 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
1368 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
1369 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
1370 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
1371 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
1372 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
1373 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
1374 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
1375 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
1376 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
1377 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
1378 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
1381 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1384 drm_connector_list_iter_begin(dev
, &iter
);
1385 drm_for_each_connector_iter(connector
, &iter
) {
1386 if (connector
->encoder
== encoder
) {
1387 amdgpu_connector
= to_amdgpu_connector(connector
);
1391 drm_connector_list_iter_end(&iter
);
1393 if (!amdgpu_connector
) {
1394 DRM_ERROR("Couldn't find encoder's connector\n");
1398 sad_count
= drm_edid_to_sad(amdgpu_connector_edid(connector
), &sads
);
1400 DRM_ERROR("Couldn't read SADs: %d\n", sad_count
);
1405 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
1407 u8 stereo_freqs
= 0;
1408 int max_channels
= -1;
1411 for (j
= 0; j
< sad_count
; j
++) {
1412 struct cea_sad
*sad
= &sads
[j
];
1414 if (sad
->format
== eld_reg_to_type
[i
][1]) {
1415 if (sad
->channels
> max_channels
) {
1416 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1417 MAX_CHANNELS
, sad
->channels
);
1418 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1419 DESCRIPTOR_BYTE_2
, sad
->byte2
);
1420 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1421 SUPPORTED_FREQUENCIES
, sad
->freq
);
1422 max_channels
= sad
->channels
;
1425 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
1426 stereo_freqs
|= sad
->freq
;
1432 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1433 SUPPORTED_FREQUENCIES_STEREO
, stereo_freqs
);
1434 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
, eld_reg_to_type
[i
][0], tmp
);
1440 static void dce_v11_0_audio_enable(struct amdgpu_device
*adev
,
1441 struct amdgpu_audio_pin
*pin
,
1447 WREG32_AUDIO_ENDPT(pin
->offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
,
1448 enable
? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
: 0);
1451 static const u32 pin_offsets
[] =
1453 AUD0_REGISTER_OFFSET
,
1454 AUD1_REGISTER_OFFSET
,
1455 AUD2_REGISTER_OFFSET
,
1456 AUD3_REGISTER_OFFSET
,
1457 AUD4_REGISTER_OFFSET
,
1458 AUD5_REGISTER_OFFSET
,
1459 AUD6_REGISTER_OFFSET
,
1460 AUD7_REGISTER_OFFSET
,
1463 static int dce_v11_0_audio_init(struct amdgpu_device
*adev
)
1470 adev
->mode_info
.audio
.enabled
= true;
1472 switch (adev
->asic_type
) {
1475 adev
->mode_info
.audio
.num_pins
= 7;
1477 case CHIP_POLARIS10
:
1479 adev
->mode_info
.audio
.num_pins
= 8;
1481 case CHIP_POLARIS11
:
1482 case CHIP_POLARIS12
:
1483 adev
->mode_info
.audio
.num_pins
= 6;
1489 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1490 adev
->mode_info
.audio
.pin
[i
].channels
= -1;
1491 adev
->mode_info
.audio
.pin
[i
].rate
= -1;
1492 adev
->mode_info
.audio
.pin
[i
].bits_per_sample
= -1;
1493 adev
->mode_info
.audio
.pin
[i
].status_bits
= 0;
1494 adev
->mode_info
.audio
.pin
[i
].category_code
= 0;
1495 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1496 adev
->mode_info
.audio
.pin
[i
].offset
= pin_offsets
[i
];
1497 adev
->mode_info
.audio
.pin
[i
].id
= i
;
1498 /* disable audio. it will be set up later */
1499 /* XXX remove once we switch to ip funcs */
1500 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1506 static void dce_v11_0_audio_fini(struct amdgpu_device
*adev
)
1513 if (!adev
->mode_info
.audio
.enabled
)
1516 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++)
1517 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1519 adev
->mode_info
.audio
.enabled
= false;
1523 * update the N and CTS parameters for a given pixel clock rate
1525 static void dce_v11_0_afmt_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
)
1527 struct drm_device
*dev
= encoder
->dev
;
1528 struct amdgpu_device
*adev
= dev
->dev_private
;
1529 struct amdgpu_afmt_acr acr
= amdgpu_afmt_acr(clock
);
1530 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1531 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1534 tmp
= RREG32(mmHDMI_ACR_32_0
+ dig
->afmt
->offset
);
1535 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_32_0
, HDMI_ACR_CTS_32
, acr
.cts_32khz
);
1536 WREG32(mmHDMI_ACR_32_0
+ dig
->afmt
->offset
, tmp
);
1537 tmp
= RREG32(mmHDMI_ACR_32_1
+ dig
->afmt
->offset
);
1538 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_32_1
, HDMI_ACR_N_32
, acr
.n_32khz
);
1539 WREG32(mmHDMI_ACR_32_1
+ dig
->afmt
->offset
, tmp
);
1541 tmp
= RREG32(mmHDMI_ACR_44_0
+ dig
->afmt
->offset
);
1542 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_44_0
, HDMI_ACR_CTS_44
, acr
.cts_44_1khz
);
1543 WREG32(mmHDMI_ACR_44_0
+ dig
->afmt
->offset
, tmp
);
1544 tmp
= RREG32(mmHDMI_ACR_44_1
+ dig
->afmt
->offset
);
1545 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_44_1
, HDMI_ACR_N_44
, acr
.n_44_1khz
);
1546 WREG32(mmHDMI_ACR_44_1
+ dig
->afmt
->offset
, tmp
);
1548 tmp
= RREG32(mmHDMI_ACR_48_0
+ dig
->afmt
->offset
);
1549 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_48_0
, HDMI_ACR_CTS_48
, acr
.cts_48khz
);
1550 WREG32(mmHDMI_ACR_48_0
+ dig
->afmt
->offset
, tmp
);
1551 tmp
= RREG32(mmHDMI_ACR_48_1
+ dig
->afmt
->offset
);
1552 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_48_1
, HDMI_ACR_N_48
, acr
.n_48khz
);
1553 WREG32(mmHDMI_ACR_48_1
+ dig
->afmt
->offset
, tmp
);
1558 * build a HDMI Video Info Frame
1560 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder
*encoder
,
1561 void *buffer
, size_t size
)
1563 struct drm_device
*dev
= encoder
->dev
;
1564 struct amdgpu_device
*adev
= dev
->dev_private
;
1565 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1566 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1567 uint8_t *frame
= buffer
+ 3;
1568 uint8_t *header
= buffer
;
1570 WREG32(mmAFMT_AVI_INFO0
+ dig
->afmt
->offset
,
1571 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
1572 WREG32(mmAFMT_AVI_INFO1
+ dig
->afmt
->offset
,
1573 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
1574 WREG32(mmAFMT_AVI_INFO2
+ dig
->afmt
->offset
,
1575 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
1576 WREG32(mmAFMT_AVI_INFO3
+ dig
->afmt
->offset
,
1577 frame
[0xC] | (frame
[0xD] << 8) | (header
[1] << 24));
1580 static void dce_v11_0_audio_set_dto(struct drm_encoder
*encoder
, u32 clock
)
1582 struct drm_device
*dev
= encoder
->dev
;
1583 struct amdgpu_device
*adev
= dev
->dev_private
;
1584 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1585 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1586 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1587 u32 dto_phase
= 24 * 1000;
1588 u32 dto_modulo
= clock
;
1591 if (!dig
|| !dig
->afmt
)
1594 /* XXX two dtos; generally use dto0 for hdmi */
1595 /* Express [24MHz / target pixel clock] as an exact rational
1596 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1597 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1599 tmp
= RREG32(mmDCCG_AUDIO_DTO_SOURCE
);
1600 tmp
= REG_SET_FIELD(tmp
, DCCG_AUDIO_DTO_SOURCE
, DCCG_AUDIO_DTO0_SOURCE_SEL
,
1601 amdgpu_crtc
->crtc_id
);
1602 WREG32(mmDCCG_AUDIO_DTO_SOURCE
, tmp
);
1603 WREG32(mmDCCG_AUDIO_DTO0_PHASE
, dto_phase
);
1604 WREG32(mmDCCG_AUDIO_DTO0_MODULE
, dto_modulo
);
1608 * update the info frames with the data from the current display mode
1610 static void dce_v11_0_afmt_setmode(struct drm_encoder
*encoder
,
1611 struct drm_display_mode
*mode
)
1613 struct drm_device
*dev
= encoder
->dev
;
1614 struct amdgpu_device
*adev
= dev
->dev_private
;
1615 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1616 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1617 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1618 u8 buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_AVI_INFOFRAME_SIZE
];
1619 struct hdmi_avi_infoframe frame
;
1624 if (!dig
|| !dig
->afmt
)
1627 /* Silent, r600_hdmi_enable will raise WARN for us */
1628 if (!dig
->afmt
->enabled
)
1631 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1632 if (encoder
->crtc
) {
1633 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1634 bpc
= amdgpu_crtc
->bpc
;
1637 /* disable audio prior to setting up hw */
1638 dig
->afmt
->pin
= dce_v11_0_audio_get_pin(adev
);
1639 dce_v11_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1641 dce_v11_0_audio_set_dto(encoder
, mode
->clock
);
1643 tmp
= RREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
);
1644 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_NULL_SEND
, 1);
1645 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
); /* send null packets when required */
1647 WREG32(mmAFMT_AUDIO_CRC_CONTROL
+ dig
->afmt
->offset
, 0x1000);
1649 tmp
= RREG32(mmHDMI_CONTROL
+ dig
->afmt
->offset
);
1656 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 0);
1657 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 0);
1658 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1659 connector
->name
, bpc
);
1662 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 1);
1663 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 1);
1664 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1668 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 1);
1669 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 2);
1670 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1674 WREG32(mmHDMI_CONTROL
+ dig
->afmt
->offset
, tmp
);
1676 tmp
= RREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
);
1677 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_NULL_SEND
, 1); /* send null packets when required */
1678 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_GC_SEND
, 1); /* send general control packets */
1679 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_GC_CONT
, 1); /* send general control packets every frame */
1680 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1682 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1683 /* enable audio info frames (frames won't be set until audio is enabled) */
1684 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_SEND
, 1);
1685 /* required for audio info values to be updated */
1686 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_CONT
, 1);
1687 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1689 tmp
= RREG32(mmAFMT_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1690 /* required for audio info values to be updated */
1691 tmp
= REG_SET_FIELD(tmp
, AFMT_INFOFRAME_CONTROL0
, AFMT_AUDIO_INFO_UPDATE
, 1);
1692 WREG32(mmAFMT_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1694 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
);
1695 /* anything other than 0 */
1696 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL1
, HDMI_AUDIO_INFO_LINE
, 2);
1697 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
, tmp
);
1699 WREG32(mmHDMI_GC
+ dig
->afmt
->offset
, 0); /* unset HDMI_GC_AVMUTE */
1701 tmp
= RREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1702 /* set the default audio delay */
1703 tmp
= REG_SET_FIELD(tmp
, HDMI_AUDIO_PACKET_CONTROL
, HDMI_AUDIO_DELAY_EN
, 1);
1704 /* should be suffient for all audio modes and small enough for all hblanks */
1705 tmp
= REG_SET_FIELD(tmp
, HDMI_AUDIO_PACKET_CONTROL
, HDMI_AUDIO_PACKETS_PER_LINE
, 3);
1706 WREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1708 tmp
= RREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1709 /* allow 60958 channel status fields to be updated */
1710 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_PACKET_CONTROL
, AFMT_60958_CS_UPDATE
, 1);
1711 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1713 tmp
= RREG32(mmHDMI_ACR_PACKET_CONTROL
+ dig
->afmt
->offset
);
1715 /* clear SW CTS value */
1716 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_SOURCE
, 0);
1718 /* select SW CTS value */
1719 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_SOURCE
, 1);
1720 /* allow hw to sent ACR packets when required */
1721 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_AUTO_SEND
, 1);
1722 WREG32(mmHDMI_ACR_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1724 dce_v11_0_afmt_update_ACR(encoder
, mode
->clock
);
1726 tmp
= RREG32(mmAFMT_60958_0
+ dig
->afmt
->offset
);
1727 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_0
, AFMT_60958_CS_CHANNEL_NUMBER_L
, 1);
1728 WREG32(mmAFMT_60958_0
+ dig
->afmt
->offset
, tmp
);
1730 tmp
= RREG32(mmAFMT_60958_1
+ dig
->afmt
->offset
);
1731 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_1
, AFMT_60958_CS_CHANNEL_NUMBER_R
, 2);
1732 WREG32(mmAFMT_60958_1
+ dig
->afmt
->offset
, tmp
);
1734 tmp
= RREG32(mmAFMT_60958_2
+ dig
->afmt
->offset
);
1735 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_2
, 3);
1736 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_3
, 4);
1737 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_4
, 5);
1738 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_5
, 6);
1739 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_6
, 7);
1740 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_7
, 8);
1741 WREG32(mmAFMT_60958_2
+ dig
->afmt
->offset
, tmp
);
1743 dce_v11_0_audio_write_speaker_allocation(encoder
);
1745 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2
+ dig
->afmt
->offset
,
1746 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
));
1748 dce_v11_0_afmt_audio_select_pin(encoder
);
1749 dce_v11_0_audio_write_sad_regs(encoder
);
1750 dce_v11_0_audio_write_latency_fields(encoder
, mode
);
1752 err
= drm_hdmi_avi_infoframe_from_display_mode(&frame
, connector
, mode
);
1754 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err
);
1758 err
= hdmi_avi_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1760 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err
);
1764 dce_v11_0_afmt_update_avi_infoframe(encoder
, buffer
, sizeof(buffer
));
1766 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1767 /* enable AVI info frames */
1768 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AVI_INFO_SEND
, 1);
1769 /* required for audio info values to be updated */
1770 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AVI_INFO_CONT
, 1);
1771 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1773 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
);
1774 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL1
, HDMI_AVI_INFO_LINE
, 2);
1775 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
, tmp
);
1777 tmp
= RREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1778 /* send audio packets */
1779 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_PACKET_CONTROL
, AFMT_AUDIO_SAMPLE_SEND
, 1);
1780 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1782 WREG32(mmAFMT_RAMP_CONTROL0
+ dig
->afmt
->offset
, 0x00FFFFFF);
1783 WREG32(mmAFMT_RAMP_CONTROL1
+ dig
->afmt
->offset
, 0x007FFFFF);
1784 WREG32(mmAFMT_RAMP_CONTROL2
+ dig
->afmt
->offset
, 0x00000001);
1785 WREG32(mmAFMT_RAMP_CONTROL3
+ dig
->afmt
->offset
, 0x00000001);
1787 /* enable audio after to setting up hw */
1788 dce_v11_0_audio_enable(adev
, dig
->afmt
->pin
, true);
1791 static void dce_v11_0_afmt_enable(struct drm_encoder
*encoder
, bool enable
)
1793 struct drm_device
*dev
= encoder
->dev
;
1794 struct amdgpu_device
*adev
= dev
->dev_private
;
1795 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1796 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1798 if (!dig
|| !dig
->afmt
)
1801 /* Silent, r600_hdmi_enable will raise WARN for us */
1802 if (enable
&& dig
->afmt
->enabled
)
1804 if (!enable
&& !dig
->afmt
->enabled
)
1807 if (!enable
&& dig
->afmt
->pin
) {
1808 dce_v11_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1809 dig
->afmt
->pin
= NULL
;
1812 dig
->afmt
->enabled
= enable
;
1814 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1815 enable
? "En" : "Dis", dig
->afmt
->offset
, amdgpu_encoder
->encoder_id
);
1818 static int dce_v11_0_afmt_init(struct amdgpu_device
*adev
)
1822 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++)
1823 adev
->mode_info
.afmt
[i
] = NULL
;
1825 /* DCE11 has audio blocks tied to DIG encoders */
1826 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1827 adev
->mode_info
.afmt
[i
] = kzalloc(sizeof(struct amdgpu_afmt
), GFP_KERNEL
);
1828 if (adev
->mode_info
.afmt
[i
]) {
1829 adev
->mode_info
.afmt
[i
]->offset
= dig_offsets
[i
];
1830 adev
->mode_info
.afmt
[i
]->id
= i
;
1833 for (j
= 0; j
< i
; j
++) {
1834 kfree(adev
->mode_info
.afmt
[j
]);
1835 adev
->mode_info
.afmt
[j
] = NULL
;
1843 static void dce_v11_0_afmt_fini(struct amdgpu_device
*adev
)
1847 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1848 kfree(adev
->mode_info
.afmt
[i
]);
1849 adev
->mode_info
.afmt
[i
] = NULL
;
1853 static const u32 vga_control_regs
[6] =
1863 static void dce_v11_0_vga_enable(struct drm_crtc
*crtc
, bool enable
)
1865 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1866 struct drm_device
*dev
= crtc
->dev
;
1867 struct amdgpu_device
*adev
= dev
->dev_private
;
1870 vga_control
= RREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
]) & ~1;
1872 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
| 1);
1874 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
);
1877 static void dce_v11_0_grph_enable(struct drm_crtc
*crtc
, bool enable
)
1879 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1880 struct drm_device
*dev
= crtc
->dev
;
1881 struct amdgpu_device
*adev
= dev
->dev_private
;
1884 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 1);
1886 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 0);
1889 static int dce_v11_0_crtc_do_set_base(struct drm_crtc
*crtc
,
1890 struct drm_framebuffer
*fb
,
1891 int x
, int y
, int atomic
)
1893 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1894 struct drm_device
*dev
= crtc
->dev
;
1895 struct amdgpu_device
*adev
= dev
->dev_private
;
1896 struct drm_framebuffer
*target_fb
;
1897 struct drm_gem_object
*obj
;
1898 struct amdgpu_bo
*abo
;
1899 uint64_t fb_location
, tiling_flags
;
1900 uint32_t fb_format
, fb_pitch_pixels
;
1901 u32 fb_swap
= REG_SET_FIELD(0, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
, ENDIAN_NONE
);
1903 u32 tmp
, viewport_w
, viewport_h
;
1905 bool bypass_lut
= false;
1906 struct drm_format_name_buf format_name
;
1909 if (!atomic
&& !crtc
->primary
->fb
) {
1910 DRM_DEBUG_KMS("No FB bound\n");
1917 target_fb
= crtc
->primary
->fb
;
1919 /* If atomic, assume fb object is pinned & idle & fenced and
1920 * just update base pointers
1922 obj
= target_fb
->obj
[0];
1923 abo
= gem_to_amdgpu_bo(obj
);
1924 r
= amdgpu_bo_reserve(abo
, false);
1925 if (unlikely(r
!= 0))
1929 r
= amdgpu_bo_pin(abo
, AMDGPU_GEM_DOMAIN_VRAM
);
1930 if (unlikely(r
!= 0)) {
1931 amdgpu_bo_unreserve(abo
);
1935 fb_location
= amdgpu_bo_gpu_offset(abo
);
1937 amdgpu_bo_get_tiling_flags(abo
, &tiling_flags
);
1938 amdgpu_bo_unreserve(abo
);
1940 pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1942 switch (target_fb
->format
->format
) {
1944 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 0);
1945 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
1947 case DRM_FORMAT_XRGB4444
:
1948 case DRM_FORMAT_ARGB4444
:
1949 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
1950 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 2);
1952 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1956 case DRM_FORMAT_XRGB1555
:
1957 case DRM_FORMAT_ARGB1555
:
1958 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
1959 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
1961 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1965 case DRM_FORMAT_BGRX5551
:
1966 case DRM_FORMAT_BGRA5551
:
1967 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
1968 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 5);
1970 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1974 case DRM_FORMAT_RGB565
:
1975 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
1976 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 1);
1978 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1982 case DRM_FORMAT_XRGB8888
:
1983 case DRM_FORMAT_ARGB8888
:
1984 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
1985 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
1987 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1991 case DRM_FORMAT_XRGB2101010
:
1992 case DRM_FORMAT_ARGB2101010
:
1993 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
1994 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 1);
1996 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
1999 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2002 case DRM_FORMAT_BGRX1010102
:
2003 case DRM_FORMAT_BGRA1010102
:
2004 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2005 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 4);
2007 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2010 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2013 case DRM_FORMAT_XBGR8888
:
2014 case DRM_FORMAT_ABGR8888
:
2015 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2016 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2017 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_RED_CROSSBAR
, 2);
2018 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_BLUE_CROSSBAR
, 2);
2020 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2025 DRM_ERROR("Unsupported screen format %s\n",
2026 drm_get_format_name(target_fb
->format
->format
, &format_name
));
2030 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_2D_TILED_THIN1
) {
2031 unsigned bankw
, bankh
, mtaspect
, tile_split
, num_banks
;
2033 bankw
= AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
2034 bankh
= AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
2035 mtaspect
= AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
2036 tile_split
= AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
);
2037 num_banks
= AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
2039 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_NUM_BANKS
, num_banks
);
2040 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_ARRAY_MODE
,
2041 ARRAY_2D_TILED_THIN1
);
2042 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_TILE_SPLIT
,
2044 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_BANK_WIDTH
, bankw
);
2045 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_BANK_HEIGHT
, bankh
);
2046 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_MACRO_TILE_ASPECT
,
2048 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_MICRO_TILE_MODE
,
2049 ADDR_SURF_MICRO_TILING_DISPLAY
);
2050 } else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_1D_TILED_THIN1
) {
2051 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_ARRAY_MODE
,
2052 ARRAY_1D_TILED_THIN1
);
2055 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_PIPE_CONFIG
,
2058 dce_v11_0_vga_enable(crtc
, false);
2060 /* Make sure surface address is updated at vertical blank rather than
2063 tmp
= RREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2064 tmp
= REG_SET_FIELD(tmp
, GRPH_FLIP_CONTROL
,
2065 GRPH_SURFACE_UPDATE_H_RETRACE_EN
, 0);
2066 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2068 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2069 upper_32_bits(fb_location
));
2070 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2071 upper_32_bits(fb_location
));
2072 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2073 (u32
)fb_location
& GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
);
2074 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2075 (u32
) fb_location
& GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
);
2076 WREG32(mmGRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, fb_format
);
2077 WREG32(mmGRPH_SWAP_CNTL
+ amdgpu_crtc
->crtc_offset
, fb_swap
);
2080 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2081 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2082 * retain the full precision throughout the pipeline.
2084 tmp
= RREG32(mmGRPH_LUT_10BIT_BYPASS
+ amdgpu_crtc
->crtc_offset
);
2086 tmp
= REG_SET_FIELD(tmp
, GRPH_LUT_10BIT_BYPASS
, GRPH_LUT_10BIT_BYPASS_EN
, 1);
2088 tmp
= REG_SET_FIELD(tmp
, GRPH_LUT_10BIT_BYPASS
, GRPH_LUT_10BIT_BYPASS_EN
, 0);
2089 WREG32(mmGRPH_LUT_10BIT_BYPASS
+ amdgpu_crtc
->crtc_offset
, tmp
);
2092 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2094 WREG32(mmGRPH_SURFACE_OFFSET_X
+ amdgpu_crtc
->crtc_offset
, 0);
2095 WREG32(mmGRPH_SURFACE_OFFSET_Y
+ amdgpu_crtc
->crtc_offset
, 0);
2096 WREG32(mmGRPH_X_START
+ amdgpu_crtc
->crtc_offset
, 0);
2097 WREG32(mmGRPH_Y_START
+ amdgpu_crtc
->crtc_offset
, 0);
2098 WREG32(mmGRPH_X_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->width
);
2099 WREG32(mmGRPH_Y_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->height
);
2101 fb_pitch_pixels
= target_fb
->pitches
[0] / target_fb
->format
->cpp
[0];
2102 WREG32(mmGRPH_PITCH
+ amdgpu_crtc
->crtc_offset
, fb_pitch_pixels
);
2104 dce_v11_0_grph_enable(crtc
, true);
2106 WREG32(mmLB_DESKTOP_HEIGHT
+ amdgpu_crtc
->crtc_offset
,
2111 WREG32(mmVIEWPORT_START
+ amdgpu_crtc
->crtc_offset
,
2113 viewport_w
= crtc
->mode
.hdisplay
;
2114 viewport_h
= (crtc
->mode
.vdisplay
+ 1) & ~1;
2115 WREG32(mmVIEWPORT_SIZE
+ amdgpu_crtc
->crtc_offset
,
2116 (viewport_w
<< 16) | viewport_h
);
2118 /* set pageflip to happen anywhere in vblank interval */
2119 WREG32(mmCRTC_MASTER_UPDATE_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2121 if (!atomic
&& fb
&& fb
!= crtc
->primary
->fb
) {
2122 abo
= gem_to_amdgpu_bo(fb
->obj
[0]);
2123 r
= amdgpu_bo_reserve(abo
, true);
2124 if (unlikely(r
!= 0))
2126 amdgpu_bo_unpin(abo
);
2127 amdgpu_bo_unreserve(abo
);
2130 /* Bytes per pixel may have changed */
2131 dce_v11_0_bandwidth_update(adev
);
2136 static void dce_v11_0_set_interleave(struct drm_crtc
*crtc
,
2137 struct drm_display_mode
*mode
)
2139 struct drm_device
*dev
= crtc
->dev
;
2140 struct amdgpu_device
*adev
= dev
->dev_private
;
2141 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2144 tmp
= RREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
);
2145 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2146 tmp
= REG_SET_FIELD(tmp
, LB_DATA_FORMAT
, INTERLEAVE_EN
, 1);
2148 tmp
= REG_SET_FIELD(tmp
, LB_DATA_FORMAT
, INTERLEAVE_EN
, 0);
2149 WREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
, tmp
);
2152 static void dce_v11_0_crtc_load_lut(struct drm_crtc
*crtc
)
2154 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2155 struct drm_device
*dev
= crtc
->dev
;
2156 struct amdgpu_device
*adev
= dev
->dev_private
;
2161 DRM_DEBUG_KMS("%d\n", amdgpu_crtc
->crtc_id
);
2163 tmp
= RREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2164 tmp
= REG_SET_FIELD(tmp
, INPUT_CSC_CONTROL
, INPUT_CSC_GRPH_MODE
, 0);
2165 WREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2167 tmp
= RREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2168 tmp
= REG_SET_FIELD(tmp
, PRESCALE_GRPH_CONTROL
, GRPH_PRESCALE_BYPASS
, 1);
2169 WREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2171 tmp
= RREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2172 tmp
= REG_SET_FIELD(tmp
, INPUT_GAMMA_CONTROL
, GRPH_INPUT_GAMMA_MODE
, 0);
2173 WREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2175 WREG32(mmDC_LUT_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2177 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0);
2178 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0);
2179 WREG32(mmDC_LUT_BLACK_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0);
2181 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2182 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2183 WREG32(mmDC_LUT_WHITE_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2185 WREG32(mmDC_LUT_RW_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2186 WREG32(mmDC_LUT_WRITE_EN_MASK
+ amdgpu_crtc
->crtc_offset
, 0x00000007);
2188 WREG32(mmDC_LUT_RW_INDEX
+ amdgpu_crtc
->crtc_offset
, 0);
2189 r
= crtc
->gamma_store
;
2190 g
= r
+ crtc
->gamma_size
;
2191 b
= g
+ crtc
->gamma_size
;
2192 for (i
= 0; i
< 256; i
++) {
2193 WREG32(mmDC_LUT_30_COLOR
+ amdgpu_crtc
->crtc_offset
,
2194 ((*r
++ & 0xffc0) << 14) |
2195 ((*g
++ & 0xffc0) << 4) |
2199 tmp
= RREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2200 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, GRPH_DEGAMMA_MODE
, 0);
2201 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, CURSOR_DEGAMMA_MODE
, 0);
2202 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, CURSOR2_DEGAMMA_MODE
, 0);
2203 WREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2205 tmp
= RREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2206 tmp
= REG_SET_FIELD(tmp
, GAMUT_REMAP_CONTROL
, GRPH_GAMUT_REMAP_MODE
, 0);
2207 WREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2209 tmp
= RREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2210 tmp
= REG_SET_FIELD(tmp
, REGAMMA_CONTROL
, GRPH_REGAMMA_MODE
, 0);
2211 WREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2213 tmp
= RREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2214 tmp
= REG_SET_FIELD(tmp
, OUTPUT_CSC_CONTROL
, OUTPUT_CSC_GRPH_MODE
, 0);
2215 WREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2217 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2218 WREG32(mmDENORM_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2219 /* XXX this only needs to be programmed once per crtc at startup,
2220 * not sure where the best place for it is
2222 tmp
= RREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2223 tmp
= REG_SET_FIELD(tmp
, ALPHA_CONTROL
, CURSOR_ALPHA_BLND_ENA
, 1);
2224 WREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2227 static int dce_v11_0_pick_dig_encoder(struct drm_encoder
*encoder
)
2229 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
2230 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
2232 switch (amdgpu_encoder
->encoder_id
) {
2233 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2239 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2245 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2251 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2255 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder
->encoder_id
);
2261 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2265 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2266 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2267 * monitors a dedicated PPLL must be used. If a particular board has
2268 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2269 * as there is no need to program the PLL itself. If we are not able to
2270 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2271 * avoid messing up an existing monitor.
2273 * Asic specific PLL information
2277 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2279 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2282 static u32
dce_v11_0_pick_pll(struct drm_crtc
*crtc
)
2284 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2285 struct drm_device
*dev
= crtc
->dev
;
2286 struct amdgpu_device
*adev
= dev
->dev_private
;
2290 if ((adev
->asic_type
== CHIP_POLARIS10
) ||
2291 (adev
->asic_type
== CHIP_POLARIS11
) ||
2292 (adev
->asic_type
== CHIP_POLARIS12
) ||
2293 (adev
->asic_type
== CHIP_VEGAM
)) {
2294 struct amdgpu_encoder
*amdgpu_encoder
=
2295 to_amdgpu_encoder(amdgpu_crtc
->encoder
);
2296 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
2298 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
)))
2301 switch (amdgpu_encoder
->encoder_id
) {
2302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2304 return ATOM_COMBOPHY_PLL1
;
2306 return ATOM_COMBOPHY_PLL0
;
2308 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2310 return ATOM_COMBOPHY_PLL3
;
2312 return ATOM_COMBOPHY_PLL2
;
2314 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2316 return ATOM_COMBOPHY_PLL5
;
2318 return ATOM_COMBOPHY_PLL4
;
2321 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder
->encoder_id
);
2322 return ATOM_PPLL_INVALID
;
2326 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
))) {
2327 if (adev
->clock
.dp_extclk
)
2328 /* skip PPLL programming if using ext clock */
2329 return ATOM_PPLL_INVALID
;
2331 /* use the same PPLL for all DP monitors */
2332 pll
= amdgpu_pll_get_shared_dp_ppll(crtc
);
2333 if (pll
!= ATOM_PPLL_INVALID
)
2337 /* use the same PPLL for all monitors with the same clock */
2338 pll
= amdgpu_pll_get_shared_nondp_ppll(crtc
);
2339 if (pll
!= ATOM_PPLL_INVALID
)
2343 /* XXX need to determine what plls are available on each DCE11 part */
2344 pll_in_use
= amdgpu_pll_get_use_mask(crtc
);
2345 if (adev
->asic_type
== CHIP_CARRIZO
|| adev
->asic_type
== CHIP_STONEY
) {
2346 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2348 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2350 DRM_ERROR("unable to allocate a PPLL\n");
2351 return ATOM_PPLL_INVALID
;
2353 if (!(pll_in_use
& (1 << ATOM_PPLL2
)))
2355 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2357 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2359 DRM_ERROR("unable to allocate a PPLL\n");
2360 return ATOM_PPLL_INVALID
;
2362 return ATOM_PPLL_INVALID
;
2365 static void dce_v11_0_lock_cursor(struct drm_crtc
*crtc
, bool lock
)
2367 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2368 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2371 cur_lock
= RREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
);
2373 cur_lock
= REG_SET_FIELD(cur_lock
, CUR_UPDATE
, CURSOR_UPDATE_LOCK
, 1);
2375 cur_lock
= REG_SET_FIELD(cur_lock
, CUR_UPDATE
, CURSOR_UPDATE_LOCK
, 0);
2376 WREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
, cur_lock
);
2379 static void dce_v11_0_hide_cursor(struct drm_crtc
*crtc
)
2381 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2382 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2385 tmp
= RREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2386 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_EN
, 0);
2387 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2390 static void dce_v11_0_show_cursor(struct drm_crtc
*crtc
)
2392 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2393 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2396 WREG32(mmCUR_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2397 upper_32_bits(amdgpu_crtc
->cursor_addr
));
2398 WREG32(mmCUR_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2399 lower_32_bits(amdgpu_crtc
->cursor_addr
));
2401 tmp
= RREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2402 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_EN
, 1);
2403 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_MODE
, 2);
2404 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2407 static int dce_v11_0_cursor_move_locked(struct drm_crtc
*crtc
,
2410 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2411 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2412 int xorigin
= 0, yorigin
= 0;
2414 amdgpu_crtc
->cursor_x
= x
;
2415 amdgpu_crtc
->cursor_y
= y
;
2417 /* avivo cursor are offset into the total surface */
2420 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x
, y
, crtc
->x
, crtc
->y
);
2423 xorigin
= min(-x
, amdgpu_crtc
->max_cursor_width
- 1);
2427 yorigin
= min(-y
, amdgpu_crtc
->max_cursor_height
- 1);
2431 WREG32(mmCUR_POSITION
+ amdgpu_crtc
->crtc_offset
, (x
<< 16) | y
);
2432 WREG32(mmCUR_HOT_SPOT
+ amdgpu_crtc
->crtc_offset
, (xorigin
<< 16) | yorigin
);
2433 WREG32(mmCUR_SIZE
+ amdgpu_crtc
->crtc_offset
,
2434 ((amdgpu_crtc
->cursor_width
- 1) << 16) | (amdgpu_crtc
->cursor_height
- 1));
2439 static int dce_v11_0_crtc_cursor_move(struct drm_crtc
*crtc
,
2444 dce_v11_0_lock_cursor(crtc
, true);
2445 ret
= dce_v11_0_cursor_move_locked(crtc
, x
, y
);
2446 dce_v11_0_lock_cursor(crtc
, false);
2451 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc
*crtc
,
2452 struct drm_file
*file_priv
,
2459 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2460 struct drm_gem_object
*obj
;
2461 struct amdgpu_bo
*aobj
;
2465 /* turn off cursor */
2466 dce_v11_0_hide_cursor(crtc
);
2471 if ((width
> amdgpu_crtc
->max_cursor_width
) ||
2472 (height
> amdgpu_crtc
->max_cursor_height
)) {
2473 DRM_ERROR("bad cursor width or height %d x %d\n", width
, height
);
2477 obj
= drm_gem_object_lookup(file_priv
, handle
);
2479 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle
, amdgpu_crtc
->crtc_id
);
2483 aobj
= gem_to_amdgpu_bo(obj
);
2484 ret
= amdgpu_bo_reserve(aobj
, false);
2486 drm_gem_object_put_unlocked(obj
);
2490 ret
= amdgpu_bo_pin(aobj
, AMDGPU_GEM_DOMAIN_VRAM
);
2491 amdgpu_bo_unreserve(aobj
);
2493 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret
);
2494 drm_gem_object_put_unlocked(obj
);
2497 amdgpu_crtc
->cursor_addr
= amdgpu_bo_gpu_offset(aobj
);
2499 dce_v11_0_lock_cursor(crtc
, true);
2501 if (width
!= amdgpu_crtc
->cursor_width
||
2502 height
!= amdgpu_crtc
->cursor_height
||
2503 hot_x
!= amdgpu_crtc
->cursor_hot_x
||
2504 hot_y
!= amdgpu_crtc
->cursor_hot_y
) {
2507 x
= amdgpu_crtc
->cursor_x
+ amdgpu_crtc
->cursor_hot_x
- hot_x
;
2508 y
= amdgpu_crtc
->cursor_y
+ amdgpu_crtc
->cursor_hot_y
- hot_y
;
2510 dce_v11_0_cursor_move_locked(crtc
, x
, y
);
2512 amdgpu_crtc
->cursor_width
= width
;
2513 amdgpu_crtc
->cursor_height
= height
;
2514 amdgpu_crtc
->cursor_hot_x
= hot_x
;
2515 amdgpu_crtc
->cursor_hot_y
= hot_y
;
2518 dce_v11_0_show_cursor(crtc
);
2519 dce_v11_0_lock_cursor(crtc
, false);
2522 if (amdgpu_crtc
->cursor_bo
) {
2523 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2524 ret
= amdgpu_bo_reserve(aobj
, true);
2525 if (likely(ret
== 0)) {
2526 amdgpu_bo_unpin(aobj
);
2527 amdgpu_bo_unreserve(aobj
);
2529 drm_gem_object_put_unlocked(amdgpu_crtc
->cursor_bo
);
2532 amdgpu_crtc
->cursor_bo
= obj
;
2536 static void dce_v11_0_cursor_reset(struct drm_crtc
*crtc
)
2538 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2540 if (amdgpu_crtc
->cursor_bo
) {
2541 dce_v11_0_lock_cursor(crtc
, true);
2543 dce_v11_0_cursor_move_locked(crtc
, amdgpu_crtc
->cursor_x
,
2544 amdgpu_crtc
->cursor_y
);
2546 dce_v11_0_show_cursor(crtc
);
2548 dce_v11_0_lock_cursor(crtc
, false);
2552 static int dce_v11_0_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
2553 u16
*blue
, uint32_t size
,
2554 struct drm_modeset_acquire_ctx
*ctx
)
2556 dce_v11_0_crtc_load_lut(crtc
);
2561 static void dce_v11_0_crtc_destroy(struct drm_crtc
*crtc
)
2563 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2565 drm_crtc_cleanup(crtc
);
2569 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs
= {
2570 .cursor_set2
= dce_v11_0_crtc_cursor_set2
,
2571 .cursor_move
= dce_v11_0_crtc_cursor_move
,
2572 .gamma_set
= dce_v11_0_crtc_gamma_set
,
2573 .set_config
= amdgpu_display_crtc_set_config
,
2574 .destroy
= dce_v11_0_crtc_destroy
,
2575 .page_flip_target
= amdgpu_display_crtc_page_flip_target
,
2578 static void dce_v11_0_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2580 struct drm_device
*dev
= crtc
->dev
;
2581 struct amdgpu_device
*adev
= dev
->dev_private
;
2582 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2586 case DRM_MODE_DPMS_ON
:
2587 amdgpu_crtc
->enabled
= true;
2588 amdgpu_atombios_crtc_enable(crtc
, ATOM_ENABLE
);
2589 dce_v11_0_vga_enable(crtc
, true);
2590 amdgpu_atombios_crtc_blank(crtc
, ATOM_DISABLE
);
2591 dce_v11_0_vga_enable(crtc
, false);
2592 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2593 type
= amdgpu_display_crtc_idx_to_irq_type(adev
,
2594 amdgpu_crtc
->crtc_id
);
2595 amdgpu_irq_update(adev
, &adev
->crtc_irq
, type
);
2596 amdgpu_irq_update(adev
, &adev
->pageflip_irq
, type
);
2597 drm_crtc_vblank_on(crtc
);
2598 dce_v11_0_crtc_load_lut(crtc
);
2600 case DRM_MODE_DPMS_STANDBY
:
2601 case DRM_MODE_DPMS_SUSPEND
:
2602 case DRM_MODE_DPMS_OFF
:
2603 drm_crtc_vblank_off(crtc
);
2604 if (amdgpu_crtc
->enabled
) {
2605 dce_v11_0_vga_enable(crtc
, true);
2606 amdgpu_atombios_crtc_blank(crtc
, ATOM_ENABLE
);
2607 dce_v11_0_vga_enable(crtc
, false);
2609 amdgpu_atombios_crtc_enable(crtc
, ATOM_DISABLE
);
2610 amdgpu_crtc
->enabled
= false;
2613 /* adjust pm to dpms */
2614 amdgpu_pm_compute_clocks(adev
);
2617 static void dce_v11_0_crtc_prepare(struct drm_crtc
*crtc
)
2619 /* disable crtc pair power gating before programming */
2620 amdgpu_atombios_crtc_powergate(crtc
, ATOM_DISABLE
);
2621 amdgpu_atombios_crtc_lock(crtc
, ATOM_ENABLE
);
2622 dce_v11_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2625 static void dce_v11_0_crtc_commit(struct drm_crtc
*crtc
)
2627 dce_v11_0_crtc_dpms(crtc
, DRM_MODE_DPMS_ON
);
2628 amdgpu_atombios_crtc_lock(crtc
, ATOM_DISABLE
);
2631 static void dce_v11_0_crtc_disable(struct drm_crtc
*crtc
)
2633 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2634 struct drm_device
*dev
= crtc
->dev
;
2635 struct amdgpu_device
*adev
= dev
->dev_private
;
2636 struct amdgpu_atom_ss ss
;
2639 dce_v11_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2640 if (crtc
->primary
->fb
) {
2642 struct amdgpu_bo
*abo
;
2644 abo
= gem_to_amdgpu_bo(crtc
->primary
->fb
->obj
[0]);
2645 r
= amdgpu_bo_reserve(abo
, true);
2647 DRM_ERROR("failed to reserve abo before unpin\n");
2649 amdgpu_bo_unpin(abo
);
2650 amdgpu_bo_unreserve(abo
);
2653 /* disable the GRPH */
2654 dce_v11_0_grph_enable(crtc
, false);
2656 amdgpu_atombios_crtc_powergate(crtc
, ATOM_ENABLE
);
2658 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2659 if (adev
->mode_info
.crtcs
[i
] &&
2660 adev
->mode_info
.crtcs
[i
]->enabled
&&
2661 i
!= amdgpu_crtc
->crtc_id
&&
2662 amdgpu_crtc
->pll_id
== adev
->mode_info
.crtcs
[i
]->pll_id
) {
2663 /* one other crtc is using this pll don't turn
2670 switch (amdgpu_crtc
->pll_id
) {
2674 /* disable the ppll */
2675 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
->pll_id
,
2676 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2678 case ATOM_COMBOPHY_PLL0
:
2679 case ATOM_COMBOPHY_PLL1
:
2680 case ATOM_COMBOPHY_PLL2
:
2681 case ATOM_COMBOPHY_PLL3
:
2682 case ATOM_COMBOPHY_PLL4
:
2683 case ATOM_COMBOPHY_PLL5
:
2684 /* disable the ppll */
2685 amdgpu_atombios_crtc_program_pll(crtc
, ATOM_CRTC_INVALID
, amdgpu_crtc
->pll_id
,
2686 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2692 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2693 amdgpu_crtc
->adjusted_clock
= 0;
2694 amdgpu_crtc
->encoder
= NULL
;
2695 amdgpu_crtc
->connector
= NULL
;
2698 static int dce_v11_0_crtc_mode_set(struct drm_crtc
*crtc
,
2699 struct drm_display_mode
*mode
,
2700 struct drm_display_mode
*adjusted_mode
,
2701 int x
, int y
, struct drm_framebuffer
*old_fb
)
2703 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2704 struct drm_device
*dev
= crtc
->dev
;
2705 struct amdgpu_device
*adev
= dev
->dev_private
;
2707 if (!amdgpu_crtc
->adjusted_clock
)
2710 if ((adev
->asic_type
== CHIP_POLARIS10
) ||
2711 (adev
->asic_type
== CHIP_POLARIS11
) ||
2712 (adev
->asic_type
== CHIP_POLARIS12
) ||
2713 (adev
->asic_type
== CHIP_VEGAM
)) {
2714 struct amdgpu_encoder
*amdgpu_encoder
=
2715 to_amdgpu_encoder(amdgpu_crtc
->encoder
);
2717 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
);
2719 /* SetPixelClock calculates the plls and ss values now */
2720 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
,
2721 amdgpu_crtc
->pll_id
,
2722 encoder_mode
, amdgpu_encoder
->encoder_id
,
2723 adjusted_mode
->clock
, 0, 0, 0, 0,
2724 amdgpu_crtc
->bpc
, amdgpu_crtc
->ss_enabled
, &amdgpu_crtc
->ss
);
2726 amdgpu_atombios_crtc_set_pll(crtc
, adjusted_mode
);
2728 amdgpu_atombios_crtc_set_dtd_timing(crtc
, adjusted_mode
);
2729 dce_v11_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2730 amdgpu_atombios_crtc_overscan_setup(crtc
, mode
, adjusted_mode
);
2731 amdgpu_atombios_crtc_scaler_setup(crtc
);
2732 dce_v11_0_cursor_reset(crtc
);
2733 /* update the hw version fpr dpm */
2734 amdgpu_crtc
->hw_mode
= *adjusted_mode
;
2739 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc
*crtc
,
2740 const struct drm_display_mode
*mode
,
2741 struct drm_display_mode
*adjusted_mode
)
2743 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2744 struct drm_device
*dev
= crtc
->dev
;
2745 struct drm_encoder
*encoder
;
2747 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2748 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2749 if (encoder
->crtc
== crtc
) {
2750 amdgpu_crtc
->encoder
= encoder
;
2751 amdgpu_crtc
->connector
= amdgpu_get_connector_for_encoder(encoder
);
2755 if ((amdgpu_crtc
->encoder
== NULL
) || (amdgpu_crtc
->connector
== NULL
)) {
2756 amdgpu_crtc
->encoder
= NULL
;
2757 amdgpu_crtc
->connector
= NULL
;
2760 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc
, mode
, adjusted_mode
))
2762 if (amdgpu_atombios_crtc_prepare_pll(crtc
, adjusted_mode
))
2765 amdgpu_crtc
->pll_id
= dce_v11_0_pick_pll(crtc
);
2766 /* if we can't get a PPLL for a non-DP encoder, fail */
2767 if ((amdgpu_crtc
->pll_id
== ATOM_PPLL_INVALID
) &&
2768 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
)))
2774 static int dce_v11_0_crtc_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2775 struct drm_framebuffer
*old_fb
)
2777 return dce_v11_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2780 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc
*crtc
,
2781 struct drm_framebuffer
*fb
,
2782 int x
, int y
, enum mode_set_atomic state
)
2784 return dce_v11_0_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
2787 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs
= {
2788 .dpms
= dce_v11_0_crtc_dpms
,
2789 .mode_fixup
= dce_v11_0_crtc_mode_fixup
,
2790 .mode_set
= dce_v11_0_crtc_mode_set
,
2791 .mode_set_base
= dce_v11_0_crtc_set_base
,
2792 .mode_set_base_atomic
= dce_v11_0_crtc_set_base_atomic
,
2793 .prepare
= dce_v11_0_crtc_prepare
,
2794 .commit
= dce_v11_0_crtc_commit
,
2795 .disable
= dce_v11_0_crtc_disable
,
2798 static int dce_v11_0_crtc_init(struct amdgpu_device
*adev
, int index
)
2800 struct amdgpu_crtc
*amdgpu_crtc
;
2802 amdgpu_crtc
= kzalloc(sizeof(struct amdgpu_crtc
) +
2803 (AMDGPUFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
2804 if (amdgpu_crtc
== NULL
)
2807 drm_crtc_init(adev
->ddev
, &amdgpu_crtc
->base
, &dce_v11_0_crtc_funcs
);
2809 drm_mode_crtc_set_gamma_size(&amdgpu_crtc
->base
, 256);
2810 amdgpu_crtc
->crtc_id
= index
;
2811 adev
->mode_info
.crtcs
[index
] = amdgpu_crtc
;
2813 amdgpu_crtc
->max_cursor_width
= 128;
2814 amdgpu_crtc
->max_cursor_height
= 128;
2815 adev
->ddev
->mode_config
.cursor_width
= amdgpu_crtc
->max_cursor_width
;
2816 adev
->ddev
->mode_config
.cursor_height
= amdgpu_crtc
->max_cursor_height
;
2818 switch (amdgpu_crtc
->crtc_id
) {
2821 amdgpu_crtc
->crtc_offset
= CRTC0_REGISTER_OFFSET
;
2824 amdgpu_crtc
->crtc_offset
= CRTC1_REGISTER_OFFSET
;
2827 amdgpu_crtc
->crtc_offset
= CRTC2_REGISTER_OFFSET
;
2830 amdgpu_crtc
->crtc_offset
= CRTC3_REGISTER_OFFSET
;
2833 amdgpu_crtc
->crtc_offset
= CRTC4_REGISTER_OFFSET
;
2836 amdgpu_crtc
->crtc_offset
= CRTC5_REGISTER_OFFSET
;
2840 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2841 amdgpu_crtc
->adjusted_clock
= 0;
2842 amdgpu_crtc
->encoder
= NULL
;
2843 amdgpu_crtc
->connector
= NULL
;
2844 drm_crtc_helper_add(&amdgpu_crtc
->base
, &dce_v11_0_crtc_helper_funcs
);
2849 static int dce_v11_0_early_init(void *handle
)
2851 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2853 adev
->audio_endpt_rreg
= &dce_v11_0_audio_endpt_rreg
;
2854 adev
->audio_endpt_wreg
= &dce_v11_0_audio_endpt_wreg
;
2856 dce_v11_0_set_display_funcs(adev
);
2858 adev
->mode_info
.num_crtc
= dce_v11_0_get_num_crtc(adev
);
2860 switch (adev
->asic_type
) {
2862 adev
->mode_info
.num_hpd
= 6;
2863 adev
->mode_info
.num_dig
= 9;
2866 adev
->mode_info
.num_hpd
= 6;
2867 adev
->mode_info
.num_dig
= 9;
2869 case CHIP_POLARIS10
:
2871 adev
->mode_info
.num_hpd
= 6;
2872 adev
->mode_info
.num_dig
= 6;
2874 case CHIP_POLARIS11
:
2875 case CHIP_POLARIS12
:
2876 adev
->mode_info
.num_hpd
= 5;
2877 adev
->mode_info
.num_dig
= 5;
2880 /* FIXME: not supported yet */
2884 dce_v11_0_set_irq_funcs(adev
);
2889 static int dce_v11_0_sw_init(void *handle
)
2892 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2894 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2895 r
= amdgpu_irq_add_id(adev
, AMDGPU_IRQ_CLIENTID_LEGACY
, i
+ 1, &adev
->crtc_irq
);
2900 for (i
= VISLANDS30_IV_SRCID_D1_GRPH_PFLIP
; i
< 20; i
+= 2) {
2901 r
= amdgpu_irq_add_id(adev
, AMDGPU_IRQ_CLIENTID_LEGACY
, i
, &adev
->pageflip_irq
);
2907 r
= amdgpu_irq_add_id(adev
, AMDGPU_IRQ_CLIENTID_LEGACY
, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A
, &adev
->hpd_irq
);
2911 adev
->ddev
->mode_config
.funcs
= &amdgpu_mode_funcs
;
2913 adev
->ddev
->mode_config
.async_page_flip
= true;
2915 adev
->ddev
->mode_config
.max_width
= 16384;
2916 adev
->ddev
->mode_config
.max_height
= 16384;
2918 adev
->ddev
->mode_config
.preferred_depth
= 24;
2919 adev
->ddev
->mode_config
.prefer_shadow
= 1;
2921 adev
->ddev
->mode_config
.fb_base
= adev
->gmc
.aper_base
;
2923 r
= amdgpu_display_modeset_create_props(adev
);
2927 adev
->ddev
->mode_config
.max_width
= 16384;
2928 adev
->ddev
->mode_config
.max_height
= 16384;
2931 /* allocate crtcs */
2932 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2933 r
= dce_v11_0_crtc_init(adev
, i
);
2938 if (amdgpu_atombios_get_connector_info_from_object_table(adev
))
2939 amdgpu_display_print_display_setup(adev
->ddev
);
2944 r
= dce_v11_0_afmt_init(adev
);
2948 r
= dce_v11_0_audio_init(adev
);
2952 drm_kms_helper_poll_init(adev
->ddev
);
2954 adev
->mode_info
.mode_config_initialized
= true;
2958 static int dce_v11_0_sw_fini(void *handle
)
2960 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2962 kfree(adev
->mode_info
.bios_hardcoded_edid
);
2964 drm_kms_helper_poll_fini(adev
->ddev
);
2966 dce_v11_0_audio_fini(adev
);
2968 dce_v11_0_afmt_fini(adev
);
2970 drm_mode_config_cleanup(adev
->ddev
);
2971 adev
->mode_info
.mode_config_initialized
= false;
2976 static int dce_v11_0_hw_init(void *handle
)
2979 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2981 dce_v11_0_init_golden_registers(adev
);
2983 /* disable vga render */
2984 dce_v11_0_set_vga_render_state(adev
, false);
2985 /* init dig PHYs, disp eng pll */
2986 amdgpu_atombios_crtc_powergate_init(adev
);
2987 amdgpu_atombios_encoder_init_dig(adev
);
2988 if ((adev
->asic_type
== CHIP_POLARIS10
) ||
2989 (adev
->asic_type
== CHIP_POLARIS11
) ||
2990 (adev
->asic_type
== CHIP_POLARIS12
) ||
2991 (adev
->asic_type
== CHIP_VEGAM
)) {
2992 amdgpu_atombios_crtc_set_dce_clock(adev
, adev
->clock
.default_dispclk
,
2993 DCE_CLOCK_TYPE_DISPCLK
, ATOM_GCK_DFS
);
2994 amdgpu_atombios_crtc_set_dce_clock(adev
, 0,
2995 DCE_CLOCK_TYPE_DPREFCLK
, ATOM_GCK_DFS
);
2997 amdgpu_atombios_crtc_set_disp_eng_pll(adev
, adev
->clock
.default_dispclk
);
3000 /* initialize hpd */
3001 dce_v11_0_hpd_init(adev
);
3003 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
3004 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
3007 dce_v11_0_pageflip_interrupt_init(adev
);
3012 static int dce_v11_0_hw_fini(void *handle
)
3015 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3017 dce_v11_0_hpd_fini(adev
);
3019 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
3020 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
3023 dce_v11_0_pageflip_interrupt_fini(adev
);
3028 static int dce_v11_0_suspend(void *handle
)
3030 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3032 adev
->mode_info
.bl_level
=
3033 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev
);
3035 return dce_v11_0_hw_fini(handle
);
3038 static int dce_v11_0_resume(void *handle
)
3040 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3043 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev
,
3044 adev
->mode_info
.bl_level
);
3046 ret
= dce_v11_0_hw_init(handle
);
3048 /* turn on the BL */
3049 if (adev
->mode_info
.bl_encoder
) {
3050 u8 bl_level
= amdgpu_display_backlight_get_level(adev
,
3051 adev
->mode_info
.bl_encoder
);
3052 amdgpu_display_backlight_set_level(adev
, adev
->mode_info
.bl_encoder
,
3059 static bool dce_v11_0_is_idle(void *handle
)
3064 static int dce_v11_0_wait_for_idle(void *handle
)
3069 static int dce_v11_0_soft_reset(void *handle
)
3071 u32 srbm_soft_reset
= 0, tmp
;
3072 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3074 if (dce_v11_0_is_display_hung(adev
))
3075 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK
;
3077 if (srbm_soft_reset
) {
3078 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3079 tmp
|= srbm_soft_reset
;
3080 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
3081 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3082 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3086 tmp
&= ~srbm_soft_reset
;
3087 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3088 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3090 /* Wait a little for things to settle down */
3096 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device
*adev
,
3098 enum amdgpu_interrupt_state state
)
3100 u32 lb_interrupt_mask
;
3102 if (crtc
>= adev
->mode_info
.num_crtc
) {
3103 DRM_DEBUG("invalid crtc %d\n", crtc
);
3108 case AMDGPU_IRQ_STATE_DISABLE
:
3109 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3110 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3111 VBLANK_INTERRUPT_MASK
, 0);
3112 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3114 case AMDGPU_IRQ_STATE_ENABLE
:
3115 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3116 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3117 VBLANK_INTERRUPT_MASK
, 1);
3118 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3125 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device
*adev
,
3127 enum amdgpu_interrupt_state state
)
3129 u32 lb_interrupt_mask
;
3131 if (crtc
>= adev
->mode_info
.num_crtc
) {
3132 DRM_DEBUG("invalid crtc %d\n", crtc
);
3137 case AMDGPU_IRQ_STATE_DISABLE
:
3138 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3139 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3140 VLINE_INTERRUPT_MASK
, 0);
3141 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3143 case AMDGPU_IRQ_STATE_ENABLE
:
3144 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3145 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3146 VLINE_INTERRUPT_MASK
, 1);
3147 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3154 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device
*adev
,
3155 struct amdgpu_irq_src
*source
,
3157 enum amdgpu_interrupt_state state
)
3161 if (hpd
>= adev
->mode_info
.num_hpd
) {
3162 DRM_DEBUG("invalid hdp %d\n", hpd
);
3167 case AMDGPU_IRQ_STATE_DISABLE
:
3168 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3169 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 0);
3170 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3172 case AMDGPU_IRQ_STATE_ENABLE
:
3173 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3174 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 1);
3175 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3184 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device
*adev
,
3185 struct amdgpu_irq_src
*source
,
3187 enum amdgpu_interrupt_state state
)
3190 case AMDGPU_CRTC_IRQ_VBLANK1
:
3191 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 0, state
);
3193 case AMDGPU_CRTC_IRQ_VBLANK2
:
3194 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 1, state
);
3196 case AMDGPU_CRTC_IRQ_VBLANK3
:
3197 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 2, state
);
3199 case AMDGPU_CRTC_IRQ_VBLANK4
:
3200 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 3, state
);
3202 case AMDGPU_CRTC_IRQ_VBLANK5
:
3203 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 4, state
);
3205 case AMDGPU_CRTC_IRQ_VBLANK6
:
3206 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 5, state
);
3208 case AMDGPU_CRTC_IRQ_VLINE1
:
3209 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 0, state
);
3211 case AMDGPU_CRTC_IRQ_VLINE2
:
3212 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 1, state
);
3214 case AMDGPU_CRTC_IRQ_VLINE3
:
3215 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 2, state
);
3217 case AMDGPU_CRTC_IRQ_VLINE4
:
3218 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 3, state
);
3220 case AMDGPU_CRTC_IRQ_VLINE5
:
3221 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 4, state
);
3223 case AMDGPU_CRTC_IRQ_VLINE6
:
3224 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 5, state
);
3232 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device
*adev
,
3233 struct amdgpu_irq_src
*src
,
3235 enum amdgpu_interrupt_state state
)
3239 if (type
>= adev
->mode_info
.num_crtc
) {
3240 DRM_ERROR("invalid pageflip crtc %d\n", type
);
3244 reg
= RREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
]);
3245 if (state
== AMDGPU_IRQ_STATE_DISABLE
)
3246 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3247 reg
& ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3249 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3250 reg
| GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3255 static int dce_v11_0_pageflip_irq(struct amdgpu_device
*adev
,
3256 struct amdgpu_irq_src
*source
,
3257 struct amdgpu_iv_entry
*entry
)
3259 unsigned long flags
;
3261 struct amdgpu_crtc
*amdgpu_crtc
;
3262 struct amdgpu_flip_work
*works
;
3264 crtc_id
= (entry
->src_id
- 8) >> 1;
3265 amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
3267 if (crtc_id
>= adev
->mode_info
.num_crtc
) {
3268 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id
);
3272 if (RREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
]) &
3273 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
)
3274 WREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
],
3275 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
);
3277 /* IRQ could occur when in initial stage */
3278 if(amdgpu_crtc
== NULL
)
3281 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
3282 works
= amdgpu_crtc
->pflip_works
;
3283 if (amdgpu_crtc
->pflip_status
!= AMDGPU_FLIP_SUBMITTED
){
3284 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3285 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3286 amdgpu_crtc
->pflip_status
,
3287 AMDGPU_FLIP_SUBMITTED
);
3288 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3292 /* page flip completed. clean up */
3293 amdgpu_crtc
->pflip_status
= AMDGPU_FLIP_NONE
;
3294 amdgpu_crtc
->pflip_works
= NULL
;
3296 /* wakeup usersapce */
3298 drm_crtc_send_vblank_event(&amdgpu_crtc
->base
, works
->event
);
3300 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3302 drm_crtc_vblank_put(&amdgpu_crtc
->base
);
3303 schedule_work(&works
->unpin_work
);
3308 static void dce_v11_0_hpd_int_ack(struct amdgpu_device
*adev
,
3313 if (hpd
>= adev
->mode_info
.num_hpd
) {
3314 DRM_DEBUG("invalid hdp %d\n", hpd
);
3318 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3319 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_ACK
, 1);
3320 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3323 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device
*adev
,
3328 if (crtc
< 0 || crtc
>= adev
->mode_info
.num_crtc
) {
3329 DRM_DEBUG("invalid crtc %d\n", crtc
);
3333 tmp
= RREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
]);
3334 tmp
= REG_SET_FIELD(tmp
, LB_VBLANK_STATUS
, VBLANK_ACK
, 1);
3335 WREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
], tmp
);
3338 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device
*adev
,
3343 if (crtc
< 0 || crtc
>= adev
->mode_info
.num_crtc
) {
3344 DRM_DEBUG("invalid crtc %d\n", crtc
);
3348 tmp
= RREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
]);
3349 tmp
= REG_SET_FIELD(tmp
, LB_VLINE_STATUS
, VLINE_ACK
, 1);
3350 WREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
], tmp
);
3353 static int dce_v11_0_crtc_irq(struct amdgpu_device
*adev
,
3354 struct amdgpu_irq_src
*source
,
3355 struct amdgpu_iv_entry
*entry
)
3357 unsigned crtc
= entry
->src_id
- 1;
3358 uint32_t disp_int
= RREG32(interrupt_status_offsets
[crtc
].reg
);
3359 unsigned int irq_type
= amdgpu_display_crtc_idx_to_irq_type(adev
,
3362 switch (entry
->src_data
[0]) {
3363 case 0: /* vblank */
3364 if (disp_int
& interrupt_status_offsets
[crtc
].vblank
)
3365 dce_v11_0_crtc_vblank_int_ack(adev
, crtc
);
3367 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3369 if (amdgpu_irq_enabled(adev
, source
, irq_type
)) {
3370 drm_handle_vblank(adev
->ddev
, crtc
);
3372 DRM_DEBUG("IH: D%d vblank\n", crtc
+ 1);
3376 if (disp_int
& interrupt_status_offsets
[crtc
].vline
)
3377 dce_v11_0_crtc_vline_int_ack(adev
, crtc
);
3379 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3381 DRM_DEBUG("IH: D%d vline\n", crtc
+ 1);
3385 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
[0]);
3392 static int dce_v11_0_hpd_irq(struct amdgpu_device
*adev
,
3393 struct amdgpu_irq_src
*source
,
3394 struct amdgpu_iv_entry
*entry
)
3396 uint32_t disp_int
, mask
;
3399 if (entry
->src_data
[0] >= adev
->mode_info
.num_hpd
) {
3400 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
[0]);
3404 hpd
= entry
->src_data
[0];
3405 disp_int
= RREG32(interrupt_status_offsets
[hpd
].reg
);
3406 mask
= interrupt_status_offsets
[hpd
].hpd
;
3408 if (disp_int
& mask
) {
3409 dce_v11_0_hpd_int_ack(adev
, hpd
);
3410 schedule_work(&adev
->hotplug_work
);
3411 DRM_DEBUG("IH: HPD%d\n", hpd
+ 1);
3417 static int dce_v11_0_set_clockgating_state(void *handle
,
3418 enum amd_clockgating_state state
)
3423 static int dce_v11_0_set_powergating_state(void *handle
,
3424 enum amd_powergating_state state
)
3429 static const struct amd_ip_funcs dce_v11_0_ip_funcs
= {
3430 .name
= "dce_v11_0",
3431 .early_init
= dce_v11_0_early_init
,
3433 .sw_init
= dce_v11_0_sw_init
,
3434 .sw_fini
= dce_v11_0_sw_fini
,
3435 .hw_init
= dce_v11_0_hw_init
,
3436 .hw_fini
= dce_v11_0_hw_fini
,
3437 .suspend
= dce_v11_0_suspend
,
3438 .resume
= dce_v11_0_resume
,
3439 .is_idle
= dce_v11_0_is_idle
,
3440 .wait_for_idle
= dce_v11_0_wait_for_idle
,
3441 .soft_reset
= dce_v11_0_soft_reset
,
3442 .set_clockgating_state
= dce_v11_0_set_clockgating_state
,
3443 .set_powergating_state
= dce_v11_0_set_powergating_state
,
3447 dce_v11_0_encoder_mode_set(struct drm_encoder
*encoder
,
3448 struct drm_display_mode
*mode
,
3449 struct drm_display_mode
*adjusted_mode
)
3451 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3453 amdgpu_encoder
->pixel_clock
= adjusted_mode
->clock
;
3455 /* need to call this here rather than in prepare() since we need some crtc info */
3456 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3458 /* set scaler clears this on some chips */
3459 dce_v11_0_set_interleave(encoder
->crtc
, mode
);
3461 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
3462 dce_v11_0_afmt_enable(encoder
, true);
3463 dce_v11_0_afmt_setmode(encoder
, adjusted_mode
);
3467 static void dce_v11_0_encoder_prepare(struct drm_encoder
*encoder
)
3469 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
3470 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3471 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
3473 if ((amdgpu_encoder
->active_device
&
3474 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
3475 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) !=
3476 ENCODER_OBJECT_ID_NONE
)) {
3477 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
3479 dig
->dig_encoder
= dce_v11_0_pick_dig_encoder(encoder
);
3480 if (amdgpu_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
)
3481 dig
->afmt
= adev
->mode_info
.afmt
[dig
->dig_encoder
];
3485 amdgpu_atombios_scratch_regs_lock(adev
, true);
3488 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
3490 /* select the clock/data port if it uses a router */
3491 if (amdgpu_connector
->router
.cd_valid
)
3492 amdgpu_i2c_router_select_cd_port(amdgpu_connector
);
3494 /* turn eDP panel on for mode set */
3495 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3496 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
3497 ATOM_TRANSMITTER_ACTION_POWER_ON
);
3500 /* this is needed for the pll/ss setup to work correctly in some cases */
3501 amdgpu_atombios_encoder_set_crtc_source(encoder
);
3502 /* set up the FMT blocks */
3503 dce_v11_0_program_fmt(encoder
);
3506 static void dce_v11_0_encoder_commit(struct drm_encoder
*encoder
)
3508 struct drm_device
*dev
= encoder
->dev
;
3509 struct amdgpu_device
*adev
= dev
->dev_private
;
3511 /* need to call this here as we need the crtc set up */
3512 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
3513 amdgpu_atombios_scratch_regs_lock(adev
, false);
3516 static void dce_v11_0_encoder_disable(struct drm_encoder
*encoder
)
3518 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3519 struct amdgpu_encoder_atom_dig
*dig
;
3521 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3523 if (amdgpu_atombios_encoder_is_digital(encoder
)) {
3524 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
3525 dce_v11_0_afmt_enable(encoder
, false);
3526 dig
= amdgpu_encoder
->enc_priv
;
3527 dig
->dig_encoder
= -1;
3529 amdgpu_encoder
->active_device
= 0;
3532 /* these are handled by the primary encoders */
3533 static void dce_v11_0_ext_prepare(struct drm_encoder
*encoder
)
3538 static void dce_v11_0_ext_commit(struct drm_encoder
*encoder
)
3544 dce_v11_0_ext_mode_set(struct drm_encoder
*encoder
,
3545 struct drm_display_mode
*mode
,
3546 struct drm_display_mode
*adjusted_mode
)
3551 static void dce_v11_0_ext_disable(struct drm_encoder
*encoder
)
3557 dce_v11_0_ext_dpms(struct drm_encoder
*encoder
, int mode
)
3562 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs
= {
3563 .dpms
= dce_v11_0_ext_dpms
,
3564 .prepare
= dce_v11_0_ext_prepare
,
3565 .mode_set
= dce_v11_0_ext_mode_set
,
3566 .commit
= dce_v11_0_ext_commit
,
3567 .disable
= dce_v11_0_ext_disable
,
3568 /* no detect for TMDS/LVDS yet */
3571 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs
= {
3572 .dpms
= amdgpu_atombios_encoder_dpms
,
3573 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3574 .prepare
= dce_v11_0_encoder_prepare
,
3575 .mode_set
= dce_v11_0_encoder_mode_set
,
3576 .commit
= dce_v11_0_encoder_commit
,
3577 .disable
= dce_v11_0_encoder_disable
,
3578 .detect
= amdgpu_atombios_encoder_dig_detect
,
3581 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs
= {
3582 .dpms
= amdgpu_atombios_encoder_dpms
,
3583 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3584 .prepare
= dce_v11_0_encoder_prepare
,
3585 .mode_set
= dce_v11_0_encoder_mode_set
,
3586 .commit
= dce_v11_0_encoder_commit
,
3587 .detect
= amdgpu_atombios_encoder_dac_detect
,
3590 static void dce_v11_0_encoder_destroy(struct drm_encoder
*encoder
)
3592 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3593 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3594 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder
);
3595 kfree(amdgpu_encoder
->enc_priv
);
3596 drm_encoder_cleanup(encoder
);
3597 kfree(amdgpu_encoder
);
3600 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs
= {
3601 .destroy
= dce_v11_0_encoder_destroy
,
3604 static void dce_v11_0_encoder_add(struct amdgpu_device
*adev
,
3605 uint32_t encoder_enum
,
3606 uint32_t supported_device
,
3609 struct drm_device
*dev
= adev
->ddev
;
3610 struct drm_encoder
*encoder
;
3611 struct amdgpu_encoder
*amdgpu_encoder
;
3613 /* see if we already added it */
3614 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3615 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3616 if (amdgpu_encoder
->encoder_enum
== encoder_enum
) {
3617 amdgpu_encoder
->devices
|= supported_device
;
3624 amdgpu_encoder
= kzalloc(sizeof(struct amdgpu_encoder
), GFP_KERNEL
);
3625 if (!amdgpu_encoder
)
3628 encoder
= &amdgpu_encoder
->base
;
3629 switch (adev
->mode_info
.num_crtc
) {
3631 encoder
->possible_crtcs
= 0x1;
3635 encoder
->possible_crtcs
= 0x3;
3638 encoder
->possible_crtcs
= 0x7;
3641 encoder
->possible_crtcs
= 0xf;
3644 encoder
->possible_crtcs
= 0x1f;
3647 encoder
->possible_crtcs
= 0x3f;
3651 amdgpu_encoder
->enc_priv
= NULL
;
3653 amdgpu_encoder
->encoder_enum
= encoder_enum
;
3654 amdgpu_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
3655 amdgpu_encoder
->devices
= supported_device
;
3656 amdgpu_encoder
->rmx_type
= RMX_OFF
;
3657 amdgpu_encoder
->underscan_type
= UNDERSCAN_OFF
;
3658 amdgpu_encoder
->is_ext_encoder
= false;
3659 amdgpu_encoder
->caps
= caps
;
3661 switch (amdgpu_encoder
->encoder_id
) {
3662 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
3663 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
3664 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3665 DRM_MODE_ENCODER_DAC
, NULL
);
3666 drm_encoder_helper_add(encoder
, &dce_v11_0_dac_helper_funcs
);
3668 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
3669 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
3670 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
3671 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
3672 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
3673 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3674 amdgpu_encoder
->rmx_type
= RMX_FULL
;
3675 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3676 DRM_MODE_ENCODER_LVDS
, NULL
);
3677 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder
);
3678 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3679 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3680 DRM_MODE_ENCODER_DAC
, NULL
);
3681 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3683 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3684 DRM_MODE_ENCODER_TMDS
, NULL
);
3685 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3687 drm_encoder_helper_add(encoder
, &dce_v11_0_dig_helper_funcs
);
3689 case ENCODER_OBJECT_ID_SI170B
:
3690 case ENCODER_OBJECT_ID_CH7303
:
3691 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
3692 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
3693 case ENCODER_OBJECT_ID_TITFP513
:
3694 case ENCODER_OBJECT_ID_VT1623
:
3695 case ENCODER_OBJECT_ID_HDMI_SI1930
:
3696 case ENCODER_OBJECT_ID_TRAVIS
:
3697 case ENCODER_OBJECT_ID_NUTMEG
:
3698 /* these are handled by the primary encoders */
3699 amdgpu_encoder
->is_ext_encoder
= true;
3700 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3701 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3702 DRM_MODE_ENCODER_LVDS
, NULL
);
3703 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
3704 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3705 DRM_MODE_ENCODER_DAC
, NULL
);
3707 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3708 DRM_MODE_ENCODER_TMDS
, NULL
);
3709 drm_encoder_helper_add(encoder
, &dce_v11_0_ext_helper_funcs
);
3714 static const struct amdgpu_display_funcs dce_v11_0_display_funcs
= {
3715 .bandwidth_update
= &dce_v11_0_bandwidth_update
,
3716 .vblank_get_counter
= &dce_v11_0_vblank_get_counter
,
3717 .backlight_set_level
= &amdgpu_atombios_encoder_set_backlight_level
,
3718 .backlight_get_level
= &amdgpu_atombios_encoder_get_backlight_level
,
3719 .hpd_sense
= &dce_v11_0_hpd_sense
,
3720 .hpd_set_polarity
= &dce_v11_0_hpd_set_polarity
,
3721 .hpd_get_gpio_reg
= &dce_v11_0_hpd_get_gpio_reg
,
3722 .page_flip
= &dce_v11_0_page_flip
,
3723 .page_flip_get_scanoutpos
= &dce_v11_0_crtc_get_scanoutpos
,
3724 .add_encoder
= &dce_v11_0_encoder_add
,
3725 .add_connector
= &amdgpu_connector_add
,
3728 static void dce_v11_0_set_display_funcs(struct amdgpu_device
*adev
)
3730 adev
->mode_info
.funcs
= &dce_v11_0_display_funcs
;
3733 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs
= {
3734 .set
= dce_v11_0_set_crtc_irq_state
,
3735 .process
= dce_v11_0_crtc_irq
,
3738 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs
= {
3739 .set
= dce_v11_0_set_pageflip_irq_state
,
3740 .process
= dce_v11_0_pageflip_irq
,
3743 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs
= {
3744 .set
= dce_v11_0_set_hpd_irq_state
,
3745 .process
= dce_v11_0_hpd_irq
,
3748 static void dce_v11_0_set_irq_funcs(struct amdgpu_device
*adev
)
3750 if (adev
->mode_info
.num_crtc
> 0)
3751 adev
->crtc_irq
.num_types
= AMDGPU_CRTC_IRQ_VLINE1
+ adev
->mode_info
.num_crtc
;
3753 adev
->crtc_irq
.num_types
= 0;
3754 adev
->crtc_irq
.funcs
= &dce_v11_0_crtc_irq_funcs
;
3756 adev
->pageflip_irq
.num_types
= adev
->mode_info
.num_crtc
;
3757 adev
->pageflip_irq
.funcs
= &dce_v11_0_pageflip_irq_funcs
;
3759 adev
->hpd_irq
.num_types
= adev
->mode_info
.num_hpd
;
3760 adev
->hpd_irq
.funcs
= &dce_v11_0_hpd_irq_funcs
;
3763 const struct amdgpu_ip_block_version dce_v11_0_ip_block
=
3765 .type
= AMD_IP_BLOCK_TYPE_DCE
,
3769 .funcs
= &dce_v11_0_ip_funcs
,
3772 const struct amdgpu_ip_block_version dce_v11_2_ip_block
=
3774 .type
= AMD_IP_BLOCK_TYPE_DCE
,
3778 .funcs
= &dce_v11_0_ip_funcs
,