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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / amdgpu / dce_v8_0.c
blobf06c9022c1fd38b5a3c128cc3d481eab4f04366a
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <drm/drm_fourcc.h>
25 #include <drm/drm_vblank.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_i2c.h"
30 #include "cikd.h"
31 #include "atom.h"
32 #include "amdgpu_atombios.h"
33 #include "atombios_crtc.h"
34 #include "atombios_encoders.h"
35 #include "amdgpu_pll.h"
36 #include "amdgpu_connectors.h"
37 #include "amdgpu_display.h"
38 #include "dce_v8_0.h"
39
40 #include "dce/dce_8_0_d.h"
41 #include "dce/dce_8_0_sh_mask.h"
42
43 #include "gca/gfx_7_2_enum.h"
44
45 #include "gmc/gmc_7_1_d.h"
46 #include "gmc/gmc_7_1_sh_mask.h"
47
48 #include "oss/oss_2_0_d.h"
49 #include "oss/oss_2_0_sh_mask.h"
50
51 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
52 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
53
54 static const u32 crtc_offsets[6] =
55 {
56 CRTC0_REGISTER_OFFSET,
57 CRTC1_REGISTER_OFFSET,
58 CRTC2_REGISTER_OFFSET,
59 CRTC3_REGISTER_OFFSET,
60 CRTC4_REGISTER_OFFSET,
61 CRTC5_REGISTER_OFFSET
62 };
63
64 static const u32 hpd_offsets[] =
65 {
66 HPD0_REGISTER_OFFSET,
67 HPD1_REGISTER_OFFSET,
68 HPD2_REGISTER_OFFSET,
69 HPD3_REGISTER_OFFSET,
70 HPD4_REGISTER_OFFSET,
71 HPD5_REGISTER_OFFSET
72 };
73
74 static const uint32_t dig_offsets[] = {
75 CRTC0_REGISTER_OFFSET,
76 CRTC1_REGISTER_OFFSET,
77 CRTC2_REGISTER_OFFSET,
78 CRTC3_REGISTER_OFFSET,
79 CRTC4_REGISTER_OFFSET,
80 CRTC5_REGISTER_OFFSET,
81 (0x13830 - 0x7030) >> 2,
82 };
83
84 static const struct {
85 uint32_t reg;
86 uint32_t vblank;
87 uint32_t vline;
88 uint32_t hpd;
89
90 } interrupt_status_offsets[6] = { {
91 .reg = mmDISP_INTERRUPT_STATUS,
92 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
95 }, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
100 }, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
105 }, {
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
110 }, {
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
115 }, {
116 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
117 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
118 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
119 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
120 } };
121
122 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
123 u32 block_offset, u32 reg)
124 {
125 unsigned long flags;
126 u32 r;
127
128 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
129 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
130 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
131 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
132
133 return r;
134 }
135
136 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
137 u32 block_offset, u32 reg, u32 v)
138 {
139 unsigned long flags;
140
141 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
142 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
143 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
144 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
145 }
146
147 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
148 {
149 if (crtc >= adev->mode_info.num_crtc)
150 return 0;
151 else
152 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
153 }
154
155 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
156 {
157 unsigned i;
158
159 /* Enable pflip interrupts */
160 for (i = 0; i < adev->mode_info.num_crtc; i++)
161 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
162 }
163
164 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
165 {
166 unsigned i;
167
168 /* Disable pflip interrupts */
169 for (i = 0; i < adev->mode_info.num_crtc; i++)
170 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
171 }
172
173 /**
174 * dce_v8_0_page_flip - pageflip callback.
175 *
176 * @adev: amdgpu_device pointer
177 * @crtc_id: crtc to cleanup pageflip on
178 * @crtc_base: new address of the crtc (GPU MC address)
179 *
180 * Triggers the actual pageflip by updating the primary
181 * surface base address.
182 */
183 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
184 int crtc_id, u64 crtc_base, bool async)
185 {
186 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
187 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
188
189 /* flip at hsync for async, default is vsync */
190 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
191 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
192 /* update pitch */
193 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
194 fb->pitches[0] / fb->format->cpp[0]);
195 /* update the primary scanout addresses */
196 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
197 upper_32_bits(crtc_base));
198 /* writing to the low address triggers the update */
199 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
200 lower_32_bits(crtc_base));
201 /* post the write */
202 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
203 }
204
205 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
206 u32 *vbl, u32 *position)
207 {
208 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
209 return -EINVAL;
210
211 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
212 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
213
214 return 0;
215 }
216
217 /**
218 * dce_v8_0_hpd_sense - hpd sense callback.
219 *
220 * @adev: amdgpu_device pointer
221 * @hpd: hpd (hotplug detect) pin
222 *
223 * Checks if a digital monitor is connected (evergreen+).
224 * Returns true if connected, false if not connected.
225 */
226 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
227 enum amdgpu_hpd_id hpd)
228 {
229 bool connected = false;
230
231 if (hpd >= adev->mode_info.num_hpd)
232 return connected;
233
234 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
235 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
236 connected = true;
237
238 return connected;
239 }
240
241 /**
242 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
243 *
244 * @adev: amdgpu_device pointer
245 * @hpd: hpd (hotplug detect) pin
246 *
247 * Set the polarity of the hpd pin (evergreen+).
248 */
249 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
250 enum amdgpu_hpd_id hpd)
251 {
252 u32 tmp;
253 bool connected = dce_v8_0_hpd_sense(adev, hpd);
254
255 if (hpd >= adev->mode_info.num_hpd)
256 return;
257
258 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
259 if (connected)
260 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
261 else
262 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
263 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
264 }
265
266 /**
267 * dce_v8_0_hpd_init - hpd setup callback.
268 *
269 * @adev: amdgpu_device pointer
270 *
271 * Setup the hpd pins used by the card (evergreen+).
272 * Enable the pin, set the polarity, and enable the hpd interrupts.
273 */
274 static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
275 {
276 struct drm_device *dev = adev->ddev;
277 struct drm_connector *connector;
278 struct drm_connector_list_iter iter;
279 u32 tmp;
280
281 drm_connector_list_iter_begin(dev, &iter);
282 drm_for_each_connector_iter(connector, &iter) {
283 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
284
285 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
286 continue;
287
288 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
289 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
290 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
291
292 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
293 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
294 /* don't try to enable hpd on eDP or LVDS avoid breaking the
295 * aux dp channel on imac and help (but not completely fix)
296 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
297 * also avoid interrupt storms during dpms.
298 */
299 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
300 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
301 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
302 continue;
303 }
304
305 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
306 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
307 }
308 drm_connector_list_iter_end(&iter);
309 }
310
311 /**
312 * dce_v8_0_hpd_fini - hpd tear down callback.
313 *
314 * @adev: amdgpu_device pointer
315 *
316 * Tear down the hpd pins used by the card (evergreen+).
317 * Disable the hpd interrupts.
318 */
319 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
320 {
321 struct drm_device *dev = adev->ddev;
322 struct drm_connector *connector;
323 struct drm_connector_list_iter iter;
324 u32 tmp;
325
326 drm_connector_list_iter_begin(dev, &iter);
327 drm_for_each_connector_iter(connector, &iter) {
328 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
329
330 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
331 continue;
332
333 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
334 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
335 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
336
337 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
338 }
339 drm_connector_list_iter_end(&iter);
340 }
341
342 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
343 {
344 return mmDC_GPIO_HPD_A;
345 }
346
347 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
348 {
349 u32 crtc_hung = 0;
350 u32 crtc_status[6];
351 u32 i, j, tmp;
352
353 for (i = 0; i < adev->mode_info.num_crtc; i++) {
354 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
355 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
356 crtc_hung |= (1 << i);
357 }
358 }
359
360 for (j = 0; j < 10; j++) {
361 for (i = 0; i < adev->mode_info.num_crtc; i++) {
362 if (crtc_hung & (1 << i)) {
363 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
364 if (tmp != crtc_status[i])
365 crtc_hung &= ~(1 << i);
366 }
367 }
368 if (crtc_hung == 0)
369 return false;
370 udelay(100);
371 }
372
373 return true;
374 }
375
376 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
377 bool render)
378 {
379 u32 tmp;
380
381 /* Lockout access through VGA aperture*/
382 tmp = RREG32(mmVGA_HDP_CONTROL);
383 if (render)
384 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
385 else
386 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
387 WREG32(mmVGA_HDP_CONTROL, tmp);
388
389 /* disable VGA render */
390 tmp = RREG32(mmVGA_RENDER_CONTROL);
391 if (render)
392 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
393 else
394 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
395 WREG32(mmVGA_RENDER_CONTROL, tmp);
396 }
397
398 static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
399 {
400 int num_crtc = 0;
401
402 switch (adev->asic_type) {
403 case CHIP_BONAIRE:
404 case CHIP_HAWAII:
405 num_crtc = 6;
406 break;
407 case CHIP_KAVERI:
408 num_crtc = 4;
409 break;
410 case CHIP_KABINI:
411 case CHIP_MULLINS:
412 num_crtc = 2;
413 break;
414 default:
415 num_crtc = 0;
416 }
417 return num_crtc;
418 }
419
420 void dce_v8_0_disable_dce(struct amdgpu_device *adev)
421 {
422 /*Disable VGA render and enabled crtc, if has DCE engine*/
423 if (amdgpu_atombios_has_dce_engine_info(adev)) {
424 u32 tmp;
425 int crtc_enabled, i;
426
427 dce_v8_0_set_vga_render_state(adev, false);
428
429 /*Disable crtc*/
430 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
431 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
432 CRTC_CONTROL, CRTC_MASTER_EN);
433 if (crtc_enabled) {
434 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
435 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
436 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
437 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
438 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
439 }
440 }
441 }
442 }
443
444 static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
445 {
446 struct drm_device *dev = encoder->dev;
447 struct amdgpu_device *adev = dev->dev_private;
448 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
449 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
450 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
451 int bpc = 0;
452 u32 tmp = 0;
453 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
454
455 if (connector) {
456 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
457 bpc = amdgpu_connector_get_monitor_bpc(connector);
458 dither = amdgpu_connector->dither;
459 }
460
461 /* LVDS/eDP FMT is set up by atom */
462 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
463 return;
464
465 /* not needed for analog */
466 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
467 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
468 return;
469
470 if (bpc == 0)
471 return;
472
473 switch (bpc) {
474 case 6:
475 if (dither == AMDGPU_FMT_DITHER_ENABLE)
476 /* XXX sort out optimal dither settings */
477 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
478 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
479 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
480 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
481 else
482 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
483 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
484 break;
485 case 8:
486 if (dither == AMDGPU_FMT_DITHER_ENABLE)
487 /* XXX sort out optimal dither settings */
488 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
489 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
490 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
491 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
492 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
493 else
494 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
495 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
496 break;
497 case 10:
498 if (dither == AMDGPU_FMT_DITHER_ENABLE)
499 /* XXX sort out optimal dither settings */
500 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
501 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
502 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
503 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
504 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
505 else
506 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
507 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
508 break;
509 default:
510 /* not needed */
511 break;
512 }
513
514 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
515 }
516
517
518 /* display watermark setup */
519 /**
520 * dce_v8_0_line_buffer_adjust - Set up the line buffer
521 *
522 * @adev: amdgpu_device pointer
523 * @amdgpu_crtc: the selected display controller
524 * @mode: the current display mode on the selected display
525 * controller
526 *
527 * Setup up the line buffer allocation for
528 * the selected display controller (CIK).
529 * Returns the line buffer size in pixels.
530 */
531 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
532 struct amdgpu_crtc *amdgpu_crtc,
533 struct drm_display_mode *mode)
534 {
535 u32 tmp, buffer_alloc, i;
536 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
537 /*
538 * Line Buffer Setup
539 * There are 6 line buffers, one for each display controllers.
540 * There are 3 partitions per LB. Select the number of partitions
541 * to enable based on the display width. For display widths larger
542 * than 4096, you need use to use 2 display controllers and combine
543 * them using the stereo blender.
544 */
545 if (amdgpu_crtc->base.enabled && mode) {
546 if (mode->crtc_hdisplay < 1920) {
547 tmp = 1;
548 buffer_alloc = 2;
549 } else if (mode->crtc_hdisplay < 2560) {
550 tmp = 2;
551 buffer_alloc = 2;
552 } else if (mode->crtc_hdisplay < 4096) {
553 tmp = 0;
554 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
555 } else {
556 DRM_DEBUG_KMS("Mode too big for LB!\n");
557 tmp = 0;
558 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
559 }
560 } else {
561 tmp = 1;
562 buffer_alloc = 0;
563 }
564
565 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
566 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
567 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
568
569 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
570 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
571 for (i = 0; i < adev->usec_timeout; i++) {
572 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
573 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
574 break;
575 udelay(1);
576 }
577
578 if (amdgpu_crtc->base.enabled && mode) {
579 switch (tmp) {
580 case 0:
581 default:
582 return 4096 * 2;
583 case 1:
584 return 1920 * 2;
585 case 2:
586 return 2560 * 2;
587 }
588 }
589
590 /* controller not enabled, so no lb used */
591 return 0;
592 }
593
594 /**
595 * cik_get_number_of_dram_channels - get the number of dram channels
596 *
597 * @adev: amdgpu_device pointer
598 *
599 * Look up the number of video ram channels (CIK).
600 * Used for display watermark bandwidth calculations
601 * Returns the number of dram channels
602 */
603 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
604 {
605 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
606
607 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
608 case 0:
609 default:
610 return 1;
611 case 1:
612 return 2;
613 case 2:
614 return 4;
615 case 3:
616 return 8;
617 case 4:
618 return 3;
619 case 5:
620 return 6;
621 case 6:
622 return 10;
623 case 7:
624 return 12;
625 case 8:
626 return 16;
627 }
628 }
629
630 struct dce8_wm_params {
631 u32 dram_channels; /* number of dram channels */
632 u32 yclk; /* bandwidth per dram data pin in kHz */
633 u32 sclk; /* engine clock in kHz */
634 u32 disp_clk; /* display clock in kHz */
635 u32 src_width; /* viewport width */
636 u32 active_time; /* active display time in ns */
637 u32 blank_time; /* blank time in ns */
638 bool interlaced; /* mode is interlaced */
639 fixed20_12 vsc; /* vertical scale ratio */
640 u32 num_heads; /* number of active crtcs */
641 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
642 u32 lb_size; /* line buffer allocated to pipe */
643 u32 vtaps; /* vertical scaler taps */
644 };
645
646 /**
647 * dce_v8_0_dram_bandwidth - get the dram bandwidth
648 *
649 * @wm: watermark calculation data
650 *
651 * Calculate the raw dram bandwidth (CIK).
652 * Used for display watermark bandwidth calculations
653 * Returns the dram bandwidth in MBytes/s
654 */
655 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
656 {
657 /* Calculate raw DRAM Bandwidth */
658 fixed20_12 dram_efficiency; /* 0.7 */
659 fixed20_12 yclk, dram_channels, bandwidth;
660 fixed20_12 a;
661
662 a.full = dfixed_const(1000);
663 yclk.full = dfixed_const(wm->yclk);
664 yclk.full = dfixed_div(yclk, a);
665 dram_channels.full = dfixed_const(wm->dram_channels * 4);
666 a.full = dfixed_const(10);
667 dram_efficiency.full = dfixed_const(7);
668 dram_efficiency.full = dfixed_div(dram_efficiency, a);
669 bandwidth.full = dfixed_mul(dram_channels, yclk);
670 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
671
672 return dfixed_trunc(bandwidth);
673 }
674
675 /**
676 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
677 *
678 * @wm: watermark calculation data
679 *
680 * Calculate the dram bandwidth used for display (CIK).
681 * Used for display watermark bandwidth calculations
682 * Returns the dram bandwidth for display in MBytes/s
683 */
684 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
685 {
686 /* Calculate DRAM Bandwidth and the part allocated to display. */
687 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
688 fixed20_12 yclk, dram_channels, bandwidth;
689 fixed20_12 a;
690
691 a.full = dfixed_const(1000);
692 yclk.full = dfixed_const(wm->yclk);
693 yclk.full = dfixed_div(yclk, a);
694 dram_channels.full = dfixed_const(wm->dram_channels * 4);
695 a.full = dfixed_const(10);
696 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
697 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
698 bandwidth.full = dfixed_mul(dram_channels, yclk);
699 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
700
701 return dfixed_trunc(bandwidth);
702 }
703
704 /**
705 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
706 *
707 * @wm: watermark calculation data
708 *
709 * Calculate the data return bandwidth used for display (CIK).
710 * Used for display watermark bandwidth calculations
711 * Returns the data return bandwidth in MBytes/s
712 */
713 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
714 {
715 /* Calculate the display Data return Bandwidth */
716 fixed20_12 return_efficiency; /* 0.8 */
717 fixed20_12 sclk, bandwidth;
718 fixed20_12 a;
719
720 a.full = dfixed_const(1000);
721 sclk.full = dfixed_const(wm->sclk);
722 sclk.full = dfixed_div(sclk, a);
723 a.full = dfixed_const(10);
724 return_efficiency.full = dfixed_const(8);
725 return_efficiency.full = dfixed_div(return_efficiency, a);
726 a.full = dfixed_const(32);
727 bandwidth.full = dfixed_mul(a, sclk);
728 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
729
730 return dfixed_trunc(bandwidth);
731 }
732
733 /**
734 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
735 *
736 * @wm: watermark calculation data
737 *
738 * Calculate the dmif bandwidth used for display (CIK).
739 * Used for display watermark bandwidth calculations
740 * Returns the dmif bandwidth in MBytes/s
741 */
742 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
743 {
744 /* Calculate the DMIF Request Bandwidth */
745 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
746 fixed20_12 disp_clk, bandwidth;
747 fixed20_12 a, b;
748
749 a.full = dfixed_const(1000);
750 disp_clk.full = dfixed_const(wm->disp_clk);
751 disp_clk.full = dfixed_div(disp_clk, a);
752 a.full = dfixed_const(32);
753 b.full = dfixed_mul(a, disp_clk);
754
755 a.full = dfixed_const(10);
756 disp_clk_request_efficiency.full = dfixed_const(8);
757 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
758
759 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
760
761 return dfixed_trunc(bandwidth);
762 }
763
764 /**
765 * dce_v8_0_available_bandwidth - get the min available bandwidth
766 *
767 * @wm: watermark calculation data
768 *
769 * Calculate the min available bandwidth used for display (CIK).
770 * Used for display watermark bandwidth calculations
771 * Returns the min available bandwidth in MBytes/s
772 */
773 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
774 {
775 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
776 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
777 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
778 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
779
780 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
781 }
782
783 /**
784 * dce_v8_0_average_bandwidth - get the average available bandwidth
785 *
786 * @wm: watermark calculation data
787 *
788 * Calculate the average available bandwidth used for display (CIK).
789 * Used for display watermark bandwidth calculations
790 * Returns the average available bandwidth in MBytes/s
791 */
792 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
793 {
794 /* Calculate the display mode Average Bandwidth
795 * DisplayMode should contain the source and destination dimensions,
796 * timing, etc.
797 */
798 fixed20_12 bpp;
799 fixed20_12 line_time;
800 fixed20_12 src_width;
801 fixed20_12 bandwidth;
802 fixed20_12 a;
803
804 a.full = dfixed_const(1000);
805 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
806 line_time.full = dfixed_div(line_time, a);
807 bpp.full = dfixed_const(wm->bytes_per_pixel);
808 src_width.full = dfixed_const(wm->src_width);
809 bandwidth.full = dfixed_mul(src_width, bpp);
810 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
811 bandwidth.full = dfixed_div(bandwidth, line_time);
812
813 return dfixed_trunc(bandwidth);
814 }
815
816 /**
817 * dce_v8_0_latency_watermark - get the latency watermark
818 *
819 * @wm: watermark calculation data
820 *
821 * Calculate the latency watermark (CIK).
822 * Used for display watermark bandwidth calculations
823 * Returns the latency watermark in ns
824 */
825 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
826 {
827 /* First calculate the latency in ns */
828 u32 mc_latency = 2000; /* 2000 ns. */
829 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
830 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
831 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
832 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
833 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
834 (wm->num_heads * cursor_line_pair_return_time);
835 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
836 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
837 u32 tmp, dmif_size = 12288;
838 fixed20_12 a, b, c;
839
840 if (wm->num_heads == 0)
841 return 0;
842
843 a.full = dfixed_const(2);
844 b.full = dfixed_const(1);
845 if ((wm->vsc.full > a.full) ||
846 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
847 (wm->vtaps >= 5) ||
848 ((wm->vsc.full >= a.full) && wm->interlaced))
849 max_src_lines_per_dst_line = 4;
850 else
851 max_src_lines_per_dst_line = 2;
852
853 a.full = dfixed_const(available_bandwidth);
854 b.full = dfixed_const(wm->num_heads);
855 a.full = dfixed_div(a, b);
856 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
857 tmp = min(dfixed_trunc(a), tmp);
858
859 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
860
861 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
862 b.full = dfixed_const(1000);
863 c.full = dfixed_const(lb_fill_bw);
864 b.full = dfixed_div(c, b);
865 a.full = dfixed_div(a, b);
866 line_fill_time = dfixed_trunc(a);
867
868 if (line_fill_time < wm->active_time)
869 return latency;
870 else
871 return latency + (line_fill_time - wm->active_time);
872
873 }
874
875 /**
876 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
877 * average and available dram bandwidth
878 *
879 * @wm: watermark calculation data
880 *
881 * Check if the display average bandwidth fits in the display
882 * dram bandwidth (CIK).
883 * Used for display watermark bandwidth calculations
884 * Returns true if the display fits, false if not.
885 */
886 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
887 {
888 if (dce_v8_0_average_bandwidth(wm) <=
889 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
890 return true;
891 else
892 return false;
893 }
894
895 /**
896 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
897 * average and available bandwidth
898 *
899 * @wm: watermark calculation data
900 *
901 * Check if the display average bandwidth fits in the display
902 * available bandwidth (CIK).
903 * Used for display watermark bandwidth calculations
904 * Returns true if the display fits, false if not.
905 */
906 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
907 {
908 if (dce_v8_0_average_bandwidth(wm) <=
909 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
910 return true;
911 else
912 return false;
913 }
914
915 /**
916 * dce_v8_0_check_latency_hiding - check latency hiding
917 *
918 * @wm: watermark calculation data
919 *
920 * Check latency hiding (CIK).
921 * Used for display watermark bandwidth calculations
922 * Returns true if the display fits, false if not.
923 */
924 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
925 {
926 u32 lb_partitions = wm->lb_size / wm->src_width;
927 u32 line_time = wm->active_time + wm->blank_time;
928 u32 latency_tolerant_lines;
929 u32 latency_hiding;
930 fixed20_12 a;
931
932 a.full = dfixed_const(1);
933 if (wm->vsc.full > a.full)
934 latency_tolerant_lines = 1;
935 else {
936 if (lb_partitions <= (wm->vtaps + 1))
937 latency_tolerant_lines = 1;
938 else
939 latency_tolerant_lines = 2;
940 }
941
942 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
943
944 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
945 return true;
946 else
947 return false;
948 }
949
950 /**
951 * dce_v8_0_program_watermarks - program display watermarks
952 *
953 * @adev: amdgpu_device pointer
954 * @amdgpu_crtc: the selected display controller
955 * @lb_size: line buffer size
956 * @num_heads: number of display controllers in use
957 *
958 * Calculate and program the display watermarks for the
959 * selected display controller (CIK).
960 */
961 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
962 struct amdgpu_crtc *amdgpu_crtc,
963 u32 lb_size, u32 num_heads)
964 {
965 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
966 struct dce8_wm_params wm_low, wm_high;
967 u32 active_time;
968 u32 line_time = 0;
969 u32 latency_watermark_a = 0, latency_watermark_b = 0;
970 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
971
972 if (amdgpu_crtc->base.enabled && num_heads && mode) {
973 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
974 (u32)mode->clock);
975 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
976 (u32)mode->clock);
977 line_time = min(line_time, (u32)65535);
978
979 /* watermark for high clocks */
980 if (adev->pm.dpm_enabled) {
981 wm_high.yclk =
982 amdgpu_dpm_get_mclk(adev, false) * 10;
983 wm_high.sclk =
984 amdgpu_dpm_get_sclk(adev, false) * 10;
985 } else {
986 wm_high.yclk = adev->pm.current_mclk * 10;
987 wm_high.sclk = adev->pm.current_sclk * 10;
988 }
989
990 wm_high.disp_clk = mode->clock;
991 wm_high.src_width = mode->crtc_hdisplay;
992 wm_high.active_time = active_time;
993 wm_high.blank_time = line_time - wm_high.active_time;
994 wm_high.interlaced = false;
995 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
996 wm_high.interlaced = true;
997 wm_high.vsc = amdgpu_crtc->vsc;
998 wm_high.vtaps = 1;
999 if (amdgpu_crtc->rmx_type != RMX_OFF)
1000 wm_high.vtaps = 2;
1001 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1002 wm_high.lb_size = lb_size;
1003 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1004 wm_high.num_heads = num_heads;
1005
1006 /* set for high clocks */
1007 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1008
1009 /* possibly force display priority to high */
1010 /* should really do this at mode validation time... */
1011 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1012 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1013 !dce_v8_0_check_latency_hiding(&wm_high) ||
1014 (adev->mode_info.disp_priority == 2)) {
1015 DRM_DEBUG_KMS("force priority to high\n");
1016 }
1017
1018 /* watermark for low clocks */
1019 if (adev->pm.dpm_enabled) {
1020 wm_low.yclk =
1021 amdgpu_dpm_get_mclk(adev, true) * 10;
1022 wm_low.sclk =
1023 amdgpu_dpm_get_sclk(adev, true) * 10;
1024 } else {
1025 wm_low.yclk = adev->pm.current_mclk * 10;
1026 wm_low.sclk = adev->pm.current_sclk * 10;
1027 }
1028
1029 wm_low.disp_clk = mode->clock;
1030 wm_low.src_width = mode->crtc_hdisplay;
1031 wm_low.active_time = active_time;
1032 wm_low.blank_time = line_time - wm_low.active_time;
1033 wm_low.interlaced = false;
1034 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1035 wm_low.interlaced = true;
1036 wm_low.vsc = amdgpu_crtc->vsc;
1037 wm_low.vtaps = 1;
1038 if (amdgpu_crtc->rmx_type != RMX_OFF)
1039 wm_low.vtaps = 2;
1040 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1041 wm_low.lb_size = lb_size;
1042 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1043 wm_low.num_heads = num_heads;
1044
1045 /* set for low clocks */
1046 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1047
1048 /* possibly force display priority to high */
1049 /* should really do this at mode validation time... */
1050 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1051 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1052 !dce_v8_0_check_latency_hiding(&wm_low) ||
1053 (adev->mode_info.disp_priority == 2)) {
1054 DRM_DEBUG_KMS("force priority to high\n");
1055 }
1056 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1057 }
1058
1059 /* select wm A */
1060 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1061 tmp = wm_mask;
1062 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1063 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1064 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1065 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1066 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1067 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1068 /* select wm B */
1069 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1070 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1071 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1072 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1073 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1074 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1075 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1076 /* restore original selection */
1077 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1078
1079 /* save values for DPM */
1080 amdgpu_crtc->line_time = line_time;
1081 amdgpu_crtc->wm_high = latency_watermark_a;
1082 amdgpu_crtc->wm_low = latency_watermark_b;
1083 /* Save number of lines the linebuffer leads before the scanout */
1084 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1085 }
1086
1087 /**
1088 * dce_v8_0_bandwidth_update - program display watermarks
1089 *
1090 * @adev: amdgpu_device pointer
1091 *
1092 * Calculate and program the display watermarks and line
1093 * buffer allocation (CIK).
1094 */
1095 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1096 {
1097 struct drm_display_mode *mode = NULL;
1098 u32 num_heads = 0, lb_size;
1099 int i;
1100
1101 amdgpu_display_update_priority(adev);
1102
1103 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1104 if (adev->mode_info.crtcs[i]->base.enabled)
1105 num_heads++;
1106 }
1107 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1108 mode = &adev->mode_info.crtcs[i]->base.mode;
1109 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1110 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1111 lb_size, num_heads);
1112 }
1113 }
1114
1115 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1116 {
1117 int i;
1118 u32 offset, tmp;
1119
1120 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1121 offset = adev->mode_info.audio.pin[i].offset;
1122 tmp = RREG32_AUDIO_ENDPT(offset,
1123 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1124 if (((tmp &
1125 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1126 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1127 adev->mode_info.audio.pin[i].connected = false;
1128 else
1129 adev->mode_info.audio.pin[i].connected = true;
1130 }
1131 }
1132
1133 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1134 {
1135 int i;
1136
1137 dce_v8_0_audio_get_connected_pins(adev);
1138
1139 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1140 if (adev->mode_info.audio.pin[i].connected)
1141 return &adev->mode_info.audio.pin[i];
1142 }
1143 DRM_ERROR("No connected audio pins found!\n");
1144 return NULL;
1145 }
1146
1147 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1148 {
1149 struct amdgpu_device *adev = encoder->dev->dev_private;
1150 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1151 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1152 u32 offset;
1153
1154 if (!dig || !dig->afmt || !dig->afmt->pin)
1155 return;
1156
1157 offset = dig->afmt->offset;
1158
1159 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1160 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1161 }
1162
1163 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1164 struct drm_display_mode *mode)
1165 {
1166 struct drm_device *dev = encoder->dev;
1167 struct amdgpu_device *adev = dev->dev_private;
1168 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1169 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1170 struct drm_connector *connector;
1171 struct drm_connector_list_iter iter;
1172 struct amdgpu_connector *amdgpu_connector = NULL;
1173 u32 tmp = 0, offset;
1174
1175 if (!dig || !dig->afmt || !dig->afmt->pin)
1176 return;
1177
1178 offset = dig->afmt->pin->offset;
1179
1180 drm_connector_list_iter_begin(dev, &iter);
1181 drm_for_each_connector_iter(connector, &iter) {
1182 if (connector->encoder == encoder) {
1183 amdgpu_connector = to_amdgpu_connector(connector);
1184 break;
1185 }
1186 }
1187 drm_connector_list_iter_end(&iter);
1188
1189 if (!amdgpu_connector) {
1190 DRM_ERROR("Couldn't find encoder's connector\n");
1191 return;
1192 }
1193
1194 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1195 if (connector->latency_present[1])
1196 tmp =
1197 (connector->video_latency[1] <<
1198 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1199 (connector->audio_latency[1] <<
1200 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1201 else
1202 tmp =
1203 (0 <<
1204 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1205 (0 <<
1206 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1207 } else {
1208 if (connector->latency_present[0])
1209 tmp =
1210 (connector->video_latency[0] <<
1211 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1212 (connector->audio_latency[0] <<
1213 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1214 else
1215 tmp =
1216 (0 <<
1217 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1218 (0 <<
1219 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1220
1221 }
1222 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1223 }
1224
1225 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1226 {
1227 struct drm_device *dev = encoder->dev;
1228 struct amdgpu_device *adev = dev->dev_private;
1229 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1230 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1231 struct drm_connector *connector;
1232 struct drm_connector_list_iter iter;
1233 struct amdgpu_connector *amdgpu_connector = NULL;
1234 u32 offset, tmp;
1235 u8 *sadb = NULL;
1236 int sad_count;
1237
1238 if (!dig || !dig->afmt || !dig->afmt->pin)
1239 return;
1240
1241 offset = dig->afmt->pin->offset;
1242
1243 drm_connector_list_iter_begin(dev, &iter);
1244 drm_for_each_connector_iter(connector, &iter) {
1245 if (connector->encoder == encoder) {
1246 amdgpu_connector = to_amdgpu_connector(connector);
1247 break;
1248 }
1249 }
1250 drm_connector_list_iter_end(&iter);
1251
1252 if (!amdgpu_connector) {
1253 DRM_ERROR("Couldn't find encoder's connector\n");
1254 return;
1255 }
1256
1257 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1258 if (sad_count < 0) {
1259 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1260 sad_count = 0;
1261 }
1262
1263 /* program the speaker allocation */
1264 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1265 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1266 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1267 /* set HDMI mode */
1268 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1269 if (sad_count)
1270 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1271 else
1272 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1273 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1274
1275 kfree(sadb);
1276 }
1277
1278 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1279 {
1280 struct drm_device *dev = encoder->dev;
1281 struct amdgpu_device *adev = dev->dev_private;
1282 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1283 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1284 u32 offset;
1285 struct drm_connector *connector;
1286 struct drm_connector_list_iter iter;
1287 struct amdgpu_connector *amdgpu_connector = NULL;
1288 struct cea_sad *sads;
1289 int i, sad_count;
1290
1291 static const u16 eld_reg_to_type[][2] = {
1292 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1293 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1294 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1295 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1296 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1297 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1298 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1299 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1300 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1301 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1302 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1303 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1304 };
1305
1306 if (!dig || !dig->afmt || !dig->afmt->pin)
1307 return;
1308
1309 offset = dig->afmt->pin->offset;
1310
1311 drm_connector_list_iter_begin(dev, &iter);
1312 drm_for_each_connector_iter(connector, &iter) {
1313 if (connector->encoder == encoder) {
1314 amdgpu_connector = to_amdgpu_connector(connector);
1315 break;
1316 }
1317 }
1318 drm_connector_list_iter_end(&iter);
1319
1320 if (!amdgpu_connector) {
1321 DRM_ERROR("Couldn't find encoder's connector\n");
1322 return;
1323 }
1324
1325 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1326 if (sad_count < 0)
1327 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1328 if (sad_count <= 0)
1329 return;
1330 BUG_ON(!sads);
1331
1332 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1333 u32 value = 0;
1334 u8 stereo_freqs = 0;
1335 int max_channels = -1;
1336 int j;
1337
1338 for (j = 0; j < sad_count; j++) {
1339 struct cea_sad *sad = &sads[j];
1340
1341 if (sad->format == eld_reg_to_type[i][1]) {
1342 if (sad->channels > max_channels) {
1343 value = (sad->channels <<
1344 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1345 (sad->byte2 <<
1346 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1347 (sad->freq <<
1348 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1349 max_channels = sad->channels;
1350 }
1351
1352 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1353 stereo_freqs |= sad->freq;
1354 else
1355 break;
1356 }
1357 }
1358
1359 value |= (stereo_freqs <<
1360 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1361
1362 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1363 }
1364
1365 kfree(sads);
1366 }
1367
1368 static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1369 struct amdgpu_audio_pin *pin,
1370 bool enable)
1371 {
1372 if (!pin)
1373 return;
1374
1375 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1376 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1377 }
1378
1379 static const u32 pin_offsets[7] =
1380 {
1381 (0x1780 - 0x1780),
1382 (0x1786 - 0x1780),
1383 (0x178c - 0x1780),
1384 (0x1792 - 0x1780),
1385 (0x1798 - 0x1780),
1386 (0x179d - 0x1780),
1387 (0x17a4 - 0x1780),
1388 };
1389
1390 static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1391 {
1392 int i;
1393
1394 if (!amdgpu_audio)
1395 return 0;
1396
1397 adev->mode_info.audio.enabled = true;
1398
1399 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1400 adev->mode_info.audio.num_pins = 7;
1401 else if ((adev->asic_type == CHIP_KABINI) ||
1402 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1403 adev->mode_info.audio.num_pins = 3;
1404 else if ((adev->asic_type == CHIP_BONAIRE) ||
1405 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1406 adev->mode_info.audio.num_pins = 7;
1407 else
1408 adev->mode_info.audio.num_pins = 3;
1409
1410 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1411 adev->mode_info.audio.pin[i].channels = -1;
1412 adev->mode_info.audio.pin[i].rate = -1;
1413 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1414 adev->mode_info.audio.pin[i].status_bits = 0;
1415 adev->mode_info.audio.pin[i].category_code = 0;
1416 adev->mode_info.audio.pin[i].connected = false;
1417 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1418 adev->mode_info.audio.pin[i].id = i;
1419 /* disable audio. it will be set up later */
1420 /* XXX remove once we switch to ip funcs */
1421 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1422 }
1423
1424 return 0;
1425 }
1426
1427 static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1428 {
1429 int i;
1430
1431 if (!amdgpu_audio)
1432 return;
1433
1434 if (!adev->mode_info.audio.enabled)
1435 return;
1436
1437 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1438 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1439
1440 adev->mode_info.audio.enabled = false;
1441 }
1442
1443 /*
1444 * update the N and CTS parameters for a given pixel clock rate
1445 */
1446 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1447 {
1448 struct drm_device *dev = encoder->dev;
1449 struct amdgpu_device *adev = dev->dev_private;
1450 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1451 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1452 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1453 uint32_t offset = dig->afmt->offset;
1454
1455 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1456 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1457
1458 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1459 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1460
1461 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1462 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1463 }
1464
1465 /*
1466 * build a HDMI Video Info Frame
1467 */
1468 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1469 void *buffer, size_t size)
1470 {
1471 struct drm_device *dev = encoder->dev;
1472 struct amdgpu_device *adev = dev->dev_private;
1473 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1474 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1475 uint32_t offset = dig->afmt->offset;
1476 uint8_t *frame = buffer + 3;
1477 uint8_t *header = buffer;
1478
1479 WREG32(mmAFMT_AVI_INFO0 + offset,
1480 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1481 WREG32(mmAFMT_AVI_INFO1 + offset,
1482 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1483 WREG32(mmAFMT_AVI_INFO2 + offset,
1484 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1485 WREG32(mmAFMT_AVI_INFO3 + offset,
1486 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1487 }
1488
1489 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1490 {
1491 struct drm_device *dev = encoder->dev;
1492 struct amdgpu_device *adev = dev->dev_private;
1493 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1494 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1495 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1496 u32 dto_phase = 24 * 1000;
1497 u32 dto_modulo = clock;
1498
1499 if (!dig || !dig->afmt)
1500 return;
1501
1502 /* XXX two dtos; generally use dto0 for hdmi */
1503 /* Express [24MHz / target pixel clock] as an exact rational
1504 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1505 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1506 */
1507 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1508 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1509 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1510 }
1511
1512 /*
1513 * update the info frames with the data from the current display mode
1514 */
1515 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1516 struct drm_display_mode *mode)
1517 {
1518 struct drm_device *dev = encoder->dev;
1519 struct amdgpu_device *adev = dev->dev_private;
1520 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1521 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1522 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1523 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1524 struct hdmi_avi_infoframe frame;
1525 uint32_t offset, val;
1526 ssize_t err;
1527 int bpc = 8;
1528
1529 if (!dig || !dig->afmt)
1530 return;
1531
1532 /* Silent, r600_hdmi_enable will raise WARN for us */
1533 if (!dig->afmt->enabled)
1534 return;
1535
1536 offset = dig->afmt->offset;
1537
1538 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1539 if (encoder->crtc) {
1540 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1541 bpc = amdgpu_crtc->bpc;
1542 }
1543
1544 /* disable audio prior to setting up hw */
1545 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1546 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1547
1548 dce_v8_0_audio_set_dto(encoder, mode->clock);
1549
1550 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1551 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1552
1553 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1554
1555 val = RREG32(mmHDMI_CONTROL + offset);
1556 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1557 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1558
1559 switch (bpc) {
1560 case 0:
1561 case 6:
1562 case 8:
1563 case 16:
1564 default:
1565 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1566 connector->name, bpc);
1567 break;
1568 case 10:
1569 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1570 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1571 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1572 connector->name);
1573 break;
1574 case 12:
1575 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1576 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1577 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1578 connector->name);
1579 break;
1580 }
1581
1582 WREG32(mmHDMI_CONTROL + offset, val);
1583
1584 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1585 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1586 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1587 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1588
1589 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1590 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1591 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1592
1593 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1594 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1595
1596 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1597 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1598
1599 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1600
1601 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1602 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1603 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1604
1605 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1606 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1607
1608 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1609
1610 if (bpc > 8)
1611 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1612 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1613 else
1614 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1615 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1616 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1617
1618 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1619
1620 WREG32(mmAFMT_60958_0 + offset,
1621 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1622
1623 WREG32(mmAFMT_60958_1 + offset,
1624 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1625
1626 WREG32(mmAFMT_60958_2 + offset,
1627 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1628 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1629 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1630 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1631 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1632 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1633
1634 dce_v8_0_audio_write_speaker_allocation(encoder);
1635
1636
1637 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1638 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1639
1640 dce_v8_0_afmt_audio_select_pin(encoder);
1641 dce_v8_0_audio_write_sad_regs(encoder);
1642 dce_v8_0_audio_write_latency_fields(encoder, mode);
1643
1644 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1645 if (err < 0) {
1646 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1647 return;
1648 }
1649
1650 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1651 if (err < 0) {
1652 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1653 return;
1654 }
1655
1656 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1657
1658 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1659 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1660 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1661
1662 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1663 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1664 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1665
1666 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1667 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1668
1669 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1670 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1671 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1672 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1673
1674 /* enable audio after setting up hw */
1675 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1676 }
1677
1678 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1679 {
1680 struct drm_device *dev = encoder->dev;
1681 struct amdgpu_device *adev = dev->dev_private;
1682 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1683 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1684
1685 if (!dig || !dig->afmt)
1686 return;
1687
1688 /* Silent, r600_hdmi_enable will raise WARN for us */
1689 if (enable && dig->afmt->enabled)
1690 return;
1691 if (!enable && !dig->afmt->enabled)
1692 return;
1693
1694 if (!enable && dig->afmt->pin) {
1695 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1696 dig->afmt->pin = NULL;
1697 }
1698
1699 dig->afmt->enabled = enable;
1700
1701 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1702 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1703 }
1704
1705 static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1706 {
1707 int i;
1708
1709 for (i = 0; i < adev->mode_info.num_dig; i++)
1710 adev->mode_info.afmt[i] = NULL;
1711
1712 /* DCE8 has audio blocks tied to DIG encoders */
1713 for (i = 0; i < adev->mode_info.num_dig; i++) {
1714 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1715 if (adev->mode_info.afmt[i]) {
1716 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1717 adev->mode_info.afmt[i]->id = i;
1718 } else {
1719 int j;
1720 for (j = 0; j < i; j++) {
1721 kfree(adev->mode_info.afmt[j]);
1722 adev->mode_info.afmt[j] = NULL;
1723 }
1724 return -ENOMEM;
1725 }
1726 }
1727 return 0;
1728 }
1729
1730 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1731 {
1732 int i;
1733
1734 for (i = 0; i < adev->mode_info.num_dig; i++) {
1735 kfree(adev->mode_info.afmt[i]);
1736 adev->mode_info.afmt[i] = NULL;
1737 }
1738 }
1739
1740 static const u32 vga_control_regs[6] =
1741 {
1742 mmD1VGA_CONTROL,
1743 mmD2VGA_CONTROL,
1744 mmD3VGA_CONTROL,
1745 mmD4VGA_CONTROL,
1746 mmD5VGA_CONTROL,
1747 mmD6VGA_CONTROL,
1748 };
1749
1750 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1751 {
1752 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1753 struct drm_device *dev = crtc->dev;
1754 struct amdgpu_device *adev = dev->dev_private;
1755 u32 vga_control;
1756
1757 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1758 if (enable)
1759 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1760 else
1761 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1762 }
1763
1764 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1765 {
1766 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1767 struct drm_device *dev = crtc->dev;
1768 struct amdgpu_device *adev = dev->dev_private;
1769
1770 if (enable)
1771 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1772 else
1773 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1774 }
1775
1776 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1777 struct drm_framebuffer *fb,
1778 int x, int y, int atomic)
1779 {
1780 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1781 struct drm_device *dev = crtc->dev;
1782 struct amdgpu_device *adev = dev->dev_private;
1783 struct drm_framebuffer *target_fb;
1784 struct drm_gem_object *obj;
1785 struct amdgpu_bo *abo;
1786 uint64_t fb_location, tiling_flags;
1787 uint32_t fb_format, fb_pitch_pixels;
1788 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1789 u32 pipe_config;
1790 u32 viewport_w, viewport_h;
1791 int r;
1792 bool bypass_lut = false;
1793 struct drm_format_name_buf format_name;
1794
1795 /* no fb bound */
1796 if (!atomic && !crtc->primary->fb) {
1797 DRM_DEBUG_KMS("No FB bound\n");
1798 return 0;
1799 }
1800
1801 if (atomic)
1802 target_fb = fb;
1803 else
1804 target_fb = crtc->primary->fb;
1805
1806 /* If atomic, assume fb object is pinned & idle & fenced and
1807 * just update base pointers
1808 */
1809 obj = target_fb->obj[0];
1810 abo = gem_to_amdgpu_bo(obj);
1811 r = amdgpu_bo_reserve(abo, false);
1812 if (unlikely(r != 0))
1813 return r;
1814
1815 if (!atomic) {
1816 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1817 if (unlikely(r != 0)) {
1818 amdgpu_bo_unreserve(abo);
1819 return -EINVAL;
1820 }
1821 }
1822 fb_location = amdgpu_bo_gpu_offset(abo);
1823
1824 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1825 amdgpu_bo_unreserve(abo);
1826
1827 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1828
1829 switch (target_fb->format->format) {
1830 case DRM_FORMAT_C8:
1831 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1832 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1833 break;
1834 case DRM_FORMAT_XRGB4444:
1835 case DRM_FORMAT_ARGB4444:
1836 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1837 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1838 #ifdef __BIG_ENDIAN
1839 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1840 #endif
1841 break;
1842 case DRM_FORMAT_XRGB1555:
1843 case DRM_FORMAT_ARGB1555:
1844 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1845 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1846 #ifdef __BIG_ENDIAN
1847 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1848 #endif
1849 break;
1850 case DRM_FORMAT_BGRX5551:
1851 case DRM_FORMAT_BGRA5551:
1852 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1853 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1854 #ifdef __BIG_ENDIAN
1855 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1856 #endif
1857 break;
1858 case DRM_FORMAT_RGB565:
1859 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1860 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1861 #ifdef __BIG_ENDIAN
1862 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1863 #endif
1864 break;
1865 case DRM_FORMAT_XRGB8888:
1866 case DRM_FORMAT_ARGB8888:
1867 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1868 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1869 #ifdef __BIG_ENDIAN
1870 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1871 #endif
1872 break;
1873 case DRM_FORMAT_XRGB2101010:
1874 case DRM_FORMAT_ARGB2101010:
1875 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1876 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1877 #ifdef __BIG_ENDIAN
1878 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1879 #endif
1880 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1881 bypass_lut = true;
1882 break;
1883 case DRM_FORMAT_BGRX1010102:
1884 case DRM_FORMAT_BGRA1010102:
1885 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1886 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1887 #ifdef __BIG_ENDIAN
1888 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1889 #endif
1890 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1891 bypass_lut = true;
1892 break;
1893 case DRM_FORMAT_XBGR8888:
1894 case DRM_FORMAT_ABGR8888:
1895 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1896 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1897 fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) |
1898 (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT));
1899 #ifdef __BIG_ENDIAN
1900 fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1901 #endif
1902 break;
1903 default:
1904 DRM_ERROR("Unsupported screen format %s\n",
1905 drm_get_format_name(target_fb->format->format, &format_name));
1906 return -EINVAL;
1907 }
1908
1909 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1910 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1911
1912 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1913 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1914 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1915 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1916 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1917
1918 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
1919 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1920 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
1921 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
1922 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
1923 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
1924 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
1925 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1926 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1927 }
1928
1929 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
1930
1931 dce_v8_0_vga_enable(crtc, false);
1932
1933 /* Make sure surface address is updated at vertical blank rather than
1934 * horizontal blank
1935 */
1936 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1937
1938 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1939 upper_32_bits(fb_location));
1940 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1941 upper_32_bits(fb_location));
1942 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1943 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1944 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1945 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
1946 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1947 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1948
1949 /*
1950 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1951 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1952 * retain the full precision throughout the pipeline.
1953 */
1954 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
1955 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
1956 ~LUT_10BIT_BYPASS_EN);
1957
1958 if (bypass_lut)
1959 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1960
1961 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1962 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1963 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1964 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1965 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1966 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1967
1968 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1969 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1970
1971 dce_v8_0_grph_enable(crtc, true);
1972
1973 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1974 target_fb->height);
1975
1976 x &= ~3;
1977 y &= ~1;
1978 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1979 (x << 16) | y);
1980 viewport_w = crtc->mode.hdisplay;
1981 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1982 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1983 (viewport_w << 16) | viewport_h);
1984
1985 /* set pageflip to happen anywhere in vblank interval */
1986 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1987
1988 if (!atomic && fb && fb != crtc->primary->fb) {
1989 abo = gem_to_amdgpu_bo(fb->obj[0]);
1990 r = amdgpu_bo_reserve(abo, true);
1991 if (unlikely(r != 0))
1992 return r;
1993 amdgpu_bo_unpin(abo);
1994 amdgpu_bo_unreserve(abo);
1995 }
1996
1997 /* Bytes per pixel may have changed */
1998 dce_v8_0_bandwidth_update(adev);
1999
2000 return 0;
2001 }
2002
2003 static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2004 struct drm_display_mode *mode)
2005 {
2006 struct drm_device *dev = crtc->dev;
2007 struct amdgpu_device *adev = dev->dev_private;
2008 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2009
2010 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2011 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2012 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2013 else
2014 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2015 }
2016
2017 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2018 {
2019 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2020 struct drm_device *dev = crtc->dev;
2021 struct amdgpu_device *adev = dev->dev_private;
2022 u16 *r, *g, *b;
2023 int i;
2024
2025 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2026
2027 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2028 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2029 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2030 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2031 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2032 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2033 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2034 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2035 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2036 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2037
2038 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2039
2040 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2041 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2042 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2043
2044 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2045 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2046 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2047
2048 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2049 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2050
2051 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2052 r = crtc->gamma_store;
2053 g = r + crtc->gamma_size;
2054 b = g + crtc->gamma_size;
2055 for (i = 0; i < 256; i++) {
2056 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2057 ((*r++ & 0xffc0) << 14) |
2058 ((*g++ & 0xffc0) << 4) |
2059 (*b++ >> 6));
2060 }
2061
2062 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2063 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2064 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2065 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2066 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2067 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2068 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2069 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2070 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2071 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2072 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2073 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2074 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2075 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2076 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2077 /* XXX this only needs to be programmed once per crtc at startup,
2078 * not sure where the best place for it is
2079 */
2080 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2081 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2082 }
2083
2084 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2085 {
2086 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2087 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2088
2089 switch (amdgpu_encoder->encoder_id) {
2090 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2091 if (dig->linkb)
2092 return 1;
2093 else
2094 return 0;
2095 break;
2096 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2097 if (dig->linkb)
2098 return 3;
2099 else
2100 return 2;
2101 break;
2102 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2103 if (dig->linkb)
2104 return 5;
2105 else
2106 return 4;
2107 break;
2108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2109 return 6;
2110 break;
2111 default:
2112 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2113 return 0;
2114 }
2115 }
2116
2117 /**
2118 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2119 *
2120 * @crtc: drm crtc
2121 *
2122 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2123 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2124 * monitors a dedicated PPLL must be used. If a particular board has
2125 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2126 * as there is no need to program the PLL itself. If we are not able to
2127 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2128 * avoid messing up an existing monitor.
2129 *
2130 * Asic specific PLL information
2131 *
2132 * DCE 8.x
2133 * KB/KV
2134 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2135 * CI
2136 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2137 *
2138 */
2139 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2140 {
2141 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2142 struct drm_device *dev = crtc->dev;
2143 struct amdgpu_device *adev = dev->dev_private;
2144 u32 pll_in_use;
2145 int pll;
2146
2147 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2148 if (adev->clock.dp_extclk)
2149 /* skip PPLL programming if using ext clock */
2150 return ATOM_PPLL_INVALID;
2151 else {
2152 /* use the same PPLL for all DP monitors */
2153 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2154 if (pll != ATOM_PPLL_INVALID)
2155 return pll;
2156 }
2157 } else {
2158 /* use the same PPLL for all monitors with the same clock */
2159 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2160 if (pll != ATOM_PPLL_INVALID)
2161 return pll;
2162 }
2163 /* otherwise, pick one of the plls */
2164 if ((adev->asic_type == CHIP_KABINI) ||
2165 (adev->asic_type == CHIP_MULLINS)) {
2166 /* KB/ML has PPLL1 and PPLL2 */
2167 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2168 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2169 return ATOM_PPLL2;
2170 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2171 return ATOM_PPLL1;
2172 DRM_ERROR("unable to allocate a PPLL\n");
2173 return ATOM_PPLL_INVALID;
2174 } else {
2175 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2176 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2177 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2178 return ATOM_PPLL2;
2179 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2180 return ATOM_PPLL1;
2181 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2182 return ATOM_PPLL0;
2183 DRM_ERROR("unable to allocate a PPLL\n");
2184 return ATOM_PPLL_INVALID;
2185 }
2186 return ATOM_PPLL_INVALID;
2187 }
2188
2189 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2190 {
2191 struct amdgpu_device *adev = crtc->dev->dev_private;
2192 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2193 uint32_t cur_lock;
2194
2195 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2196 if (lock)
2197 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2198 else
2199 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2200 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2201 }
2202
2203 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2204 {
2205 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2206 struct amdgpu_device *adev = crtc->dev->dev_private;
2207
2208 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2209 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2210 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2211 }
2212
2213 static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2214 {
2215 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2216 struct amdgpu_device *adev = crtc->dev->dev_private;
2217
2218 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2219 upper_32_bits(amdgpu_crtc->cursor_addr));
2220 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2221 lower_32_bits(amdgpu_crtc->cursor_addr));
2222
2223 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2224 CUR_CONTROL__CURSOR_EN_MASK |
2225 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2226 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2227 }
2228
2229 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2230 int x, int y)
2231 {
2232 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2233 struct amdgpu_device *adev = crtc->dev->dev_private;
2234 int xorigin = 0, yorigin = 0;
2235
2236 amdgpu_crtc->cursor_x = x;
2237 amdgpu_crtc->cursor_y = y;
2238
2239 /* avivo cursor are offset into the total surface */
2240 x += crtc->x;
2241 y += crtc->y;
2242 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2243
2244 if (x < 0) {
2245 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2246 x = 0;
2247 }
2248 if (y < 0) {
2249 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2250 y = 0;
2251 }
2252
2253 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2254 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2255 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2256 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2257
2258 return 0;
2259 }
2260
2261 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2262 int x, int y)
2263 {
2264 int ret;
2265
2266 dce_v8_0_lock_cursor(crtc, true);
2267 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2268 dce_v8_0_lock_cursor(crtc, false);
2269
2270 return ret;
2271 }
2272
2273 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2274 struct drm_file *file_priv,
2275 uint32_t handle,
2276 uint32_t width,
2277 uint32_t height,
2278 int32_t hot_x,
2279 int32_t hot_y)
2280 {
2281 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2282 struct drm_gem_object *obj;
2283 struct amdgpu_bo *aobj;
2284 int ret;
2285
2286 if (!handle) {
2287 /* turn off cursor */
2288 dce_v8_0_hide_cursor(crtc);
2289 obj = NULL;
2290 goto unpin;
2291 }
2292
2293 if ((width > amdgpu_crtc->max_cursor_width) ||
2294 (height > amdgpu_crtc->max_cursor_height)) {
2295 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2296 return -EINVAL;
2297 }
2298
2299 obj = drm_gem_object_lookup(file_priv, handle);
2300 if (!obj) {
2301 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2302 return -ENOENT;
2303 }
2304
2305 aobj = gem_to_amdgpu_bo(obj);
2306 ret = amdgpu_bo_reserve(aobj, false);
2307 if (ret != 0) {
2308 drm_gem_object_put_unlocked(obj);
2309 return ret;
2310 }
2311
2312 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2313 amdgpu_bo_unreserve(aobj);
2314 if (ret) {
2315 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2316 drm_gem_object_put_unlocked(obj);
2317 return ret;
2318 }
2319 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2320
2321 dce_v8_0_lock_cursor(crtc, true);
2322
2323 if (width != amdgpu_crtc->cursor_width ||
2324 height != amdgpu_crtc->cursor_height ||
2325 hot_x != amdgpu_crtc->cursor_hot_x ||
2326 hot_y != amdgpu_crtc->cursor_hot_y) {
2327 int x, y;
2328
2329 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2330 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2331
2332 dce_v8_0_cursor_move_locked(crtc, x, y);
2333
2334 amdgpu_crtc->cursor_width = width;
2335 amdgpu_crtc->cursor_height = height;
2336 amdgpu_crtc->cursor_hot_x = hot_x;
2337 amdgpu_crtc->cursor_hot_y = hot_y;
2338 }
2339
2340 dce_v8_0_show_cursor(crtc);
2341 dce_v8_0_lock_cursor(crtc, false);
2342
2343 unpin:
2344 if (amdgpu_crtc->cursor_bo) {
2345 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2346 ret = amdgpu_bo_reserve(aobj, true);
2347 if (likely(ret == 0)) {
2348 amdgpu_bo_unpin(aobj);
2349 amdgpu_bo_unreserve(aobj);
2350 }
2351 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2352 }
2353
2354 amdgpu_crtc->cursor_bo = obj;
2355 return 0;
2356 }
2357
2358 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2359 {
2360 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2361
2362 if (amdgpu_crtc->cursor_bo) {
2363 dce_v8_0_lock_cursor(crtc, true);
2364
2365 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2366 amdgpu_crtc->cursor_y);
2367
2368 dce_v8_0_show_cursor(crtc);
2369
2370 dce_v8_0_lock_cursor(crtc, false);
2371 }
2372 }
2373
2374 static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2375 u16 *blue, uint32_t size,
2376 struct drm_modeset_acquire_ctx *ctx)
2377 {
2378 dce_v8_0_crtc_load_lut(crtc);
2379
2380 return 0;
2381 }
2382
2383 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2384 {
2385 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2386
2387 drm_crtc_cleanup(crtc);
2388 kfree(amdgpu_crtc);
2389 }
2390
2391 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2392 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2393 .cursor_move = dce_v8_0_crtc_cursor_move,
2394 .gamma_set = dce_v8_0_crtc_gamma_set,
2395 .set_config = amdgpu_display_crtc_set_config,
2396 .destroy = dce_v8_0_crtc_destroy,
2397 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2398 };
2399
2400 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2401 {
2402 struct drm_device *dev = crtc->dev;
2403 struct amdgpu_device *adev = dev->dev_private;
2404 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2405 unsigned type;
2406
2407 switch (mode) {
2408 case DRM_MODE_DPMS_ON:
2409 amdgpu_crtc->enabled = true;
2410 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2411 dce_v8_0_vga_enable(crtc, true);
2412 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2413 dce_v8_0_vga_enable(crtc, false);
2414 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2415 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2416 amdgpu_crtc->crtc_id);
2417 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2418 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2419 drm_crtc_vblank_on(crtc);
2420 dce_v8_0_crtc_load_lut(crtc);
2421 break;
2422 case DRM_MODE_DPMS_STANDBY:
2423 case DRM_MODE_DPMS_SUSPEND:
2424 case DRM_MODE_DPMS_OFF:
2425 drm_crtc_vblank_off(crtc);
2426 if (amdgpu_crtc->enabled) {
2427 dce_v8_0_vga_enable(crtc, true);
2428 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2429 dce_v8_0_vga_enable(crtc, false);
2430 }
2431 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2432 amdgpu_crtc->enabled = false;
2433 break;
2434 }
2435 /* adjust pm to dpms */
2436 amdgpu_pm_compute_clocks(adev);
2437 }
2438
2439 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2440 {
2441 /* disable crtc pair power gating before programming */
2442 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2443 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2444 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2445 }
2446
2447 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2448 {
2449 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2450 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2451 }
2452
2453 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2454 {
2455 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2456 struct drm_device *dev = crtc->dev;
2457 struct amdgpu_device *adev = dev->dev_private;
2458 struct amdgpu_atom_ss ss;
2459 int i;
2460
2461 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2462 if (crtc->primary->fb) {
2463 int r;
2464 struct amdgpu_bo *abo;
2465
2466 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2467 r = amdgpu_bo_reserve(abo, true);
2468 if (unlikely(r))
2469 DRM_ERROR("failed to reserve abo before unpin\n");
2470 else {
2471 amdgpu_bo_unpin(abo);
2472 amdgpu_bo_unreserve(abo);
2473 }
2474 }
2475 /* disable the GRPH */
2476 dce_v8_0_grph_enable(crtc, false);
2477
2478 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2479
2480 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2481 if (adev->mode_info.crtcs[i] &&
2482 adev->mode_info.crtcs[i]->enabled &&
2483 i != amdgpu_crtc->crtc_id &&
2484 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2485 /* one other crtc is using this pll don't turn
2486 * off the pll
2487 */
2488 goto done;
2489 }
2490 }
2491
2492 switch (amdgpu_crtc->pll_id) {
2493 case ATOM_PPLL1:
2494 case ATOM_PPLL2:
2495 /* disable the ppll */
2496 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2497 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2498 break;
2499 case ATOM_PPLL0:
2500 /* disable the ppll */
2501 if ((adev->asic_type == CHIP_KAVERI) ||
2502 (adev->asic_type == CHIP_BONAIRE) ||
2503 (adev->asic_type == CHIP_HAWAII))
2504 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2505 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2506 break;
2507 default:
2508 break;
2509 }
2510 done:
2511 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2512 amdgpu_crtc->adjusted_clock = 0;
2513 amdgpu_crtc->encoder = NULL;
2514 amdgpu_crtc->connector = NULL;
2515 }
2516
2517 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2518 struct drm_display_mode *mode,
2519 struct drm_display_mode *adjusted_mode,
2520 int x, int y, struct drm_framebuffer *old_fb)
2521 {
2522 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2523
2524 if (!amdgpu_crtc->adjusted_clock)
2525 return -EINVAL;
2526
2527 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2528 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2529 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2530 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2531 amdgpu_atombios_crtc_scaler_setup(crtc);
2532 dce_v8_0_cursor_reset(crtc);
2533 /* update the hw version fpr dpm */
2534 amdgpu_crtc->hw_mode = *adjusted_mode;
2535
2536 return 0;
2537 }
2538
2539 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2540 const struct drm_display_mode *mode,
2541 struct drm_display_mode *adjusted_mode)
2542 {
2543 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2544 struct drm_device *dev = crtc->dev;
2545 struct drm_encoder *encoder;
2546
2547 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2548 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2549 if (encoder->crtc == crtc) {
2550 amdgpu_crtc->encoder = encoder;
2551 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2552 break;
2553 }
2554 }
2555 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2556 amdgpu_crtc->encoder = NULL;
2557 amdgpu_crtc->connector = NULL;
2558 return false;
2559 }
2560 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2561 return false;
2562 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2563 return false;
2564 /* pick pll */
2565 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2566 /* if we can't get a PPLL for a non-DP encoder, fail */
2567 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2568 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2569 return false;
2570
2571 return true;
2572 }
2573
2574 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2575 struct drm_framebuffer *old_fb)
2576 {
2577 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2578 }
2579
2580 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2581 struct drm_framebuffer *fb,
2582 int x, int y, enum mode_set_atomic state)
2583 {
2584 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2585 }
2586
2587 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2588 .dpms = dce_v8_0_crtc_dpms,
2589 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2590 .mode_set = dce_v8_0_crtc_mode_set,
2591 .mode_set_base = dce_v8_0_crtc_set_base,
2592 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2593 .prepare = dce_v8_0_crtc_prepare,
2594 .commit = dce_v8_0_crtc_commit,
2595 .disable = dce_v8_0_crtc_disable,
2596 };
2597
2598 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2599 {
2600 struct amdgpu_crtc *amdgpu_crtc;
2601
2602 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2603 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2604 if (amdgpu_crtc == NULL)
2605 return -ENOMEM;
2606
2607 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2608
2609 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2610 amdgpu_crtc->crtc_id = index;
2611 adev->mode_info.crtcs[index] = amdgpu_crtc;
2612
2613 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2614 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2615 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2616 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2617
2618 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2619
2620 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2621 amdgpu_crtc->adjusted_clock = 0;
2622 amdgpu_crtc->encoder = NULL;
2623 amdgpu_crtc->connector = NULL;
2624 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2625
2626 return 0;
2627 }
2628
2629 static int dce_v8_0_early_init(void *handle)
2630 {
2631 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2632
2633 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2634 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2635
2636 dce_v8_0_set_display_funcs(adev);
2637
2638 adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2639
2640 switch (adev->asic_type) {
2641 case CHIP_BONAIRE:
2642 case CHIP_HAWAII:
2643 adev->mode_info.num_hpd = 6;
2644 adev->mode_info.num_dig = 6;
2645 break;
2646 case CHIP_KAVERI:
2647 adev->mode_info.num_hpd = 6;
2648 adev->mode_info.num_dig = 7;
2649 break;
2650 case CHIP_KABINI:
2651 case CHIP_MULLINS:
2652 adev->mode_info.num_hpd = 6;
2653 adev->mode_info.num_dig = 6; /* ? */
2654 break;
2655 default:
2656 /* FIXME: not supported yet */
2657 return -EINVAL;
2658 }
2659
2660 dce_v8_0_set_irq_funcs(adev);
2661
2662 return 0;
2663 }
2664
2665 static int dce_v8_0_sw_init(void *handle)
2666 {
2667 int r, i;
2668 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2669
2670 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2671 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2672 if (r)
2673 return r;
2674 }
2675
2676 for (i = 8; i < 20; i += 2) {
2677 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2678 if (r)
2679 return r;
2680 }
2681
2682 /* HPD hotplug */
2683 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2684 if (r)
2685 return r;
2686
2687 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2688
2689 adev->ddev->mode_config.async_page_flip = true;
2690
2691 adev->ddev->mode_config.max_width = 16384;
2692 adev->ddev->mode_config.max_height = 16384;
2693
2694 adev->ddev->mode_config.preferred_depth = 24;
2695 adev->ddev->mode_config.prefer_shadow = 1;
2696
2697 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2698
2699 r = amdgpu_display_modeset_create_props(adev);
2700 if (r)
2701 return r;
2702
2703 adev->ddev->mode_config.max_width = 16384;
2704 adev->ddev->mode_config.max_height = 16384;
2705
2706 /* allocate crtcs */
2707 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2708 r = dce_v8_0_crtc_init(adev, i);
2709 if (r)
2710 return r;
2711 }
2712
2713 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2714 amdgpu_display_print_display_setup(adev->ddev);
2715 else
2716 return -EINVAL;
2717
2718 /* setup afmt */
2719 r = dce_v8_0_afmt_init(adev);
2720 if (r)
2721 return r;
2722
2723 r = dce_v8_0_audio_init(adev);
2724 if (r)
2725 return r;
2726
2727 drm_kms_helper_poll_init(adev->ddev);
2728
2729 adev->mode_info.mode_config_initialized = true;
2730 return 0;
2731 }
2732
2733 static int dce_v8_0_sw_fini(void *handle)
2734 {
2735 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2736
2737 kfree(adev->mode_info.bios_hardcoded_edid);
2738
2739 drm_kms_helper_poll_fini(adev->ddev);
2740
2741 dce_v8_0_audio_fini(adev);
2742
2743 dce_v8_0_afmt_fini(adev);
2744
2745 drm_mode_config_cleanup(adev->ddev);
2746 adev->mode_info.mode_config_initialized = false;
2747
2748 return 0;
2749 }
2750
2751 static int dce_v8_0_hw_init(void *handle)
2752 {
2753 int i;
2754 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2755
2756 /* disable vga render */
2757 dce_v8_0_set_vga_render_state(adev, false);
2758 /* init dig PHYs, disp eng pll */
2759 amdgpu_atombios_encoder_init_dig(adev);
2760 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2761
2762 /* initialize hpd */
2763 dce_v8_0_hpd_init(adev);
2764
2765 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2766 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2767 }
2768
2769 dce_v8_0_pageflip_interrupt_init(adev);
2770
2771 return 0;
2772 }
2773
2774 static int dce_v8_0_hw_fini(void *handle)
2775 {
2776 int i;
2777 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2778
2779 dce_v8_0_hpd_fini(adev);
2780
2781 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2782 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2783 }
2784
2785 dce_v8_0_pageflip_interrupt_fini(adev);
2786
2787 return 0;
2788 }
2789
2790 static int dce_v8_0_suspend(void *handle)
2791 {
2792 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2793
2794 adev->mode_info.bl_level =
2795 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2796
2797 return dce_v8_0_hw_fini(handle);
2798 }
2799
2800 static int dce_v8_0_resume(void *handle)
2801 {
2802 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2803 int ret;
2804
2805 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2806 adev->mode_info.bl_level);
2807
2808 ret = dce_v8_0_hw_init(handle);
2809
2810 /* turn on the BL */
2811 if (adev->mode_info.bl_encoder) {
2812 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2813 adev->mode_info.bl_encoder);
2814 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2815 bl_level);
2816 }
2817
2818 return ret;
2819 }
2820
2821 static bool dce_v8_0_is_idle(void *handle)
2822 {
2823 return true;
2824 }
2825
2826 static int dce_v8_0_wait_for_idle(void *handle)
2827 {
2828 return 0;
2829 }
2830
2831 static int dce_v8_0_soft_reset(void *handle)
2832 {
2833 u32 srbm_soft_reset = 0, tmp;
2834 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2835
2836 if (dce_v8_0_is_display_hung(adev))
2837 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2838
2839 if (srbm_soft_reset) {
2840 tmp = RREG32(mmSRBM_SOFT_RESET);
2841 tmp |= srbm_soft_reset;
2842 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2843 WREG32(mmSRBM_SOFT_RESET, tmp);
2844 tmp = RREG32(mmSRBM_SOFT_RESET);
2845
2846 udelay(50);
2847
2848 tmp &= ~srbm_soft_reset;
2849 WREG32(mmSRBM_SOFT_RESET, tmp);
2850 tmp = RREG32(mmSRBM_SOFT_RESET);
2851
2852 /* Wait a little for things to settle down */
2853 udelay(50);
2854 }
2855 return 0;
2856 }
2857
2858 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2859 int crtc,
2860 enum amdgpu_interrupt_state state)
2861 {
2862 u32 reg_block, lb_interrupt_mask;
2863
2864 if (crtc >= adev->mode_info.num_crtc) {
2865 DRM_DEBUG("invalid crtc %d\n", crtc);
2866 return;
2867 }
2868
2869 switch (crtc) {
2870 case 0:
2871 reg_block = CRTC0_REGISTER_OFFSET;
2872 break;
2873 case 1:
2874 reg_block = CRTC1_REGISTER_OFFSET;
2875 break;
2876 case 2:
2877 reg_block = CRTC2_REGISTER_OFFSET;
2878 break;
2879 case 3:
2880 reg_block = CRTC3_REGISTER_OFFSET;
2881 break;
2882 case 4:
2883 reg_block = CRTC4_REGISTER_OFFSET;
2884 break;
2885 case 5:
2886 reg_block = CRTC5_REGISTER_OFFSET;
2887 break;
2888 default:
2889 DRM_DEBUG("invalid crtc %d\n", crtc);
2890 return;
2891 }
2892
2893 switch (state) {
2894 case AMDGPU_IRQ_STATE_DISABLE:
2895 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2896 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2897 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2898 break;
2899 case AMDGPU_IRQ_STATE_ENABLE:
2900 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2901 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2902 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2903 break;
2904 default:
2905 break;
2906 }
2907 }
2908
2909 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2910 int crtc,
2911 enum amdgpu_interrupt_state state)
2912 {
2913 u32 reg_block, lb_interrupt_mask;
2914
2915 if (crtc >= adev->mode_info.num_crtc) {
2916 DRM_DEBUG("invalid crtc %d\n", crtc);
2917 return;
2918 }
2919
2920 switch (crtc) {
2921 case 0:
2922 reg_block = CRTC0_REGISTER_OFFSET;
2923 break;
2924 case 1:
2925 reg_block = CRTC1_REGISTER_OFFSET;
2926 break;
2927 case 2:
2928 reg_block = CRTC2_REGISTER_OFFSET;
2929 break;
2930 case 3:
2931 reg_block = CRTC3_REGISTER_OFFSET;
2932 break;
2933 case 4:
2934 reg_block = CRTC4_REGISTER_OFFSET;
2935 break;
2936 case 5:
2937 reg_block = CRTC5_REGISTER_OFFSET;
2938 break;
2939 default:
2940 DRM_DEBUG("invalid crtc %d\n", crtc);
2941 return;
2942 }
2943
2944 switch (state) {
2945 case AMDGPU_IRQ_STATE_DISABLE:
2946 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2947 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2948 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2949 break;
2950 case AMDGPU_IRQ_STATE_ENABLE:
2951 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2952 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2953 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2954 break;
2955 default:
2956 break;
2957 }
2958 }
2959
2960 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2961 struct amdgpu_irq_src *src,
2962 unsigned type,
2963 enum amdgpu_interrupt_state state)
2964 {
2965 u32 dc_hpd_int_cntl;
2966
2967 if (type >= adev->mode_info.num_hpd) {
2968 DRM_DEBUG("invalid hdp %d\n", type);
2969 return 0;
2970 }
2971
2972 switch (state) {
2973 case AMDGPU_IRQ_STATE_DISABLE:
2974 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2975 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2976 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2977 break;
2978 case AMDGPU_IRQ_STATE_ENABLE:
2979 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2980 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2981 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2982 break;
2983 default:
2984 break;
2985 }
2986
2987 return 0;
2988 }
2989
2990 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
2991 struct amdgpu_irq_src *src,
2992 unsigned type,
2993 enum amdgpu_interrupt_state state)
2994 {
2995 switch (type) {
2996 case AMDGPU_CRTC_IRQ_VBLANK1:
2997 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
2998 break;
2999 case AMDGPU_CRTC_IRQ_VBLANK2:
3000 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3001 break;
3002 case AMDGPU_CRTC_IRQ_VBLANK3:
3003 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3004 break;
3005 case AMDGPU_CRTC_IRQ_VBLANK4:
3006 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3007 break;
3008 case AMDGPU_CRTC_IRQ_VBLANK5:
3009 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3010 break;
3011 case AMDGPU_CRTC_IRQ_VBLANK6:
3012 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3013 break;
3014 case AMDGPU_CRTC_IRQ_VLINE1:
3015 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3016 break;
3017 case AMDGPU_CRTC_IRQ_VLINE2:
3018 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3019 break;
3020 case AMDGPU_CRTC_IRQ_VLINE3:
3021 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3022 break;
3023 case AMDGPU_CRTC_IRQ_VLINE4:
3024 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3025 break;
3026 case AMDGPU_CRTC_IRQ_VLINE5:
3027 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3028 break;
3029 case AMDGPU_CRTC_IRQ_VLINE6:
3030 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3031 break;
3032 default:
3033 break;
3034 }
3035 return 0;
3036 }
3037
3038 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3039 struct amdgpu_irq_src *source,
3040 struct amdgpu_iv_entry *entry)
3041 {
3042 unsigned crtc = entry->src_id - 1;
3043 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3044 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3045 crtc);
3046
3047 switch (entry->src_data[0]) {
3048 case 0: /* vblank */
3049 if (disp_int & interrupt_status_offsets[crtc].vblank)
3050 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3051 else
3052 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3053
3054 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3055 drm_handle_vblank(adev->ddev, crtc);
3056 }
3057 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3058 break;
3059 case 1: /* vline */
3060 if (disp_int & interrupt_status_offsets[crtc].vline)
3061 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3062 else
3063 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3064
3065 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3066 break;
3067 default:
3068 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3069 break;
3070 }
3071
3072 return 0;
3073 }
3074
3075 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3076 struct amdgpu_irq_src *src,
3077 unsigned type,
3078 enum amdgpu_interrupt_state state)
3079 {
3080 u32 reg;
3081
3082 if (type >= adev->mode_info.num_crtc) {
3083 DRM_ERROR("invalid pageflip crtc %d\n", type);
3084 return -EINVAL;
3085 }
3086
3087 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3088 if (state == AMDGPU_IRQ_STATE_DISABLE)
3089 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3090 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3091 else
3092 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3093 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3094
3095 return 0;
3096 }
3097
3098 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3099 struct amdgpu_irq_src *source,
3100 struct amdgpu_iv_entry *entry)
3101 {
3102 unsigned long flags;
3103 unsigned crtc_id;
3104 struct amdgpu_crtc *amdgpu_crtc;
3105 struct amdgpu_flip_work *works;
3106
3107 crtc_id = (entry->src_id - 8) >> 1;
3108 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3109
3110 if (crtc_id >= adev->mode_info.num_crtc) {
3111 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3112 return -EINVAL;
3113 }
3114
3115 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3116 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3117 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3118 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3119
3120 /* IRQ could occur when in initial stage */
3121 if (amdgpu_crtc == NULL)
3122 return 0;
3123
3124 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3125 works = amdgpu_crtc->pflip_works;
3126 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3127 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3128 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3129 amdgpu_crtc->pflip_status,
3130 AMDGPU_FLIP_SUBMITTED);
3131 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3132 return 0;
3133 }
3134
3135 /* page flip completed. clean up */
3136 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3137 amdgpu_crtc->pflip_works = NULL;
3138
3139 /* wakeup usersapce */
3140 if (works->event)
3141 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3142
3143 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3144
3145 drm_crtc_vblank_put(&amdgpu_crtc->base);
3146 schedule_work(&works->unpin_work);
3147
3148 return 0;
3149 }
3150
3151 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3152 struct amdgpu_irq_src *source,
3153 struct amdgpu_iv_entry *entry)
3154 {
3155 uint32_t disp_int, mask, tmp;
3156 unsigned hpd;
3157
3158 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3159 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3160 return 0;
3161 }
3162
3163 hpd = entry->src_data[0];
3164 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3165 mask = interrupt_status_offsets[hpd].hpd;
3166
3167 if (disp_int & mask) {
3168 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3169 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3170 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3171 schedule_work(&adev->hotplug_work);
3172 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3173 }
3174
3175 return 0;
3176
3177 }
3178
3179 static int dce_v8_0_set_clockgating_state(void *handle,
3180 enum amd_clockgating_state state)
3181 {
3182 return 0;
3183 }
3184
3185 static int dce_v8_0_set_powergating_state(void *handle,
3186 enum amd_powergating_state state)
3187 {
3188 return 0;
3189 }
3190
3191 static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3192 .name = "dce_v8_0",
3193 .early_init = dce_v8_0_early_init,
3194 .late_init = NULL,
3195 .sw_init = dce_v8_0_sw_init,
3196 .sw_fini = dce_v8_0_sw_fini,
3197 .hw_init = dce_v8_0_hw_init,
3198 .hw_fini = dce_v8_0_hw_fini,
3199 .suspend = dce_v8_0_suspend,
3200 .resume = dce_v8_0_resume,
3201 .is_idle = dce_v8_0_is_idle,
3202 .wait_for_idle = dce_v8_0_wait_for_idle,
3203 .soft_reset = dce_v8_0_soft_reset,
3204 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3205 .set_powergating_state = dce_v8_0_set_powergating_state,
3206 };
3207
3208 static void
3209 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3210 struct drm_display_mode *mode,
3211 struct drm_display_mode *adjusted_mode)
3212 {
3213 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3214
3215 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3216
3217 /* need to call this here rather than in prepare() since we need some crtc info */
3218 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3219
3220 /* set scaler clears this on some chips */
3221 dce_v8_0_set_interleave(encoder->crtc, mode);
3222
3223 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3224 dce_v8_0_afmt_enable(encoder, true);
3225 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3226 }
3227 }
3228
3229 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3230 {
3231 struct amdgpu_device *adev = encoder->dev->dev_private;
3232 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3233 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3234
3235 if ((amdgpu_encoder->active_device &
3236 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3237 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3238 ENCODER_OBJECT_ID_NONE)) {
3239 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3240 if (dig) {
3241 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3242 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3243 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3244 }
3245 }
3246
3247 amdgpu_atombios_scratch_regs_lock(adev, true);
3248
3249 if (connector) {
3250 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3251
3252 /* select the clock/data port if it uses a router */
3253 if (amdgpu_connector->router.cd_valid)
3254 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3255
3256 /* turn eDP panel on for mode set */
3257 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3258 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3259 ATOM_TRANSMITTER_ACTION_POWER_ON);
3260 }
3261
3262 /* this is needed for the pll/ss setup to work correctly in some cases */
3263 amdgpu_atombios_encoder_set_crtc_source(encoder);
3264 /* set up the FMT blocks */
3265 dce_v8_0_program_fmt(encoder);
3266 }
3267
3268 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3269 {
3270 struct drm_device *dev = encoder->dev;
3271 struct amdgpu_device *adev = dev->dev_private;
3272
3273 /* need to call this here as we need the crtc set up */
3274 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3275 amdgpu_atombios_scratch_regs_lock(adev, false);
3276 }
3277
3278 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3279 {
3280 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3281 struct amdgpu_encoder_atom_dig *dig;
3282
3283 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3284
3285 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3286 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3287 dce_v8_0_afmt_enable(encoder, false);
3288 dig = amdgpu_encoder->enc_priv;
3289 dig->dig_encoder = -1;
3290 }
3291 amdgpu_encoder->active_device = 0;
3292 }
3293
3294 /* these are handled by the primary encoders */
3295 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3296 {
3297
3298 }
3299
3300 static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3301 {
3302
3303 }
3304
3305 static void
3306 dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3307 struct drm_display_mode *mode,
3308 struct drm_display_mode *adjusted_mode)
3309 {
3310
3311 }
3312
3313 static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3314 {
3315
3316 }
3317
3318 static void
3319 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3320 {
3321
3322 }
3323
3324 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3325 .dpms = dce_v8_0_ext_dpms,
3326 .prepare = dce_v8_0_ext_prepare,
3327 .mode_set = dce_v8_0_ext_mode_set,
3328 .commit = dce_v8_0_ext_commit,
3329 .disable = dce_v8_0_ext_disable,
3330 /* no detect for TMDS/LVDS yet */
3331 };
3332
3333 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3334 .dpms = amdgpu_atombios_encoder_dpms,
3335 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3336 .prepare = dce_v8_0_encoder_prepare,
3337 .mode_set = dce_v8_0_encoder_mode_set,
3338 .commit = dce_v8_0_encoder_commit,
3339 .disable = dce_v8_0_encoder_disable,
3340 .detect = amdgpu_atombios_encoder_dig_detect,
3341 };
3342
3343 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3344 .dpms = amdgpu_atombios_encoder_dpms,
3345 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3346 .prepare = dce_v8_0_encoder_prepare,
3347 .mode_set = dce_v8_0_encoder_mode_set,
3348 .commit = dce_v8_0_encoder_commit,
3349 .detect = amdgpu_atombios_encoder_dac_detect,
3350 };
3351
3352 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3353 {
3354 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3355 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3356 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3357 kfree(amdgpu_encoder->enc_priv);
3358 drm_encoder_cleanup(encoder);
3359 kfree(amdgpu_encoder);
3360 }
3361
3362 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3363 .destroy = dce_v8_0_encoder_destroy,
3364 };
3365
3366 static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3367 uint32_t encoder_enum,
3368 uint32_t supported_device,
3369 u16 caps)
3370 {
3371 struct drm_device *dev = adev->ddev;
3372 struct drm_encoder *encoder;
3373 struct amdgpu_encoder *amdgpu_encoder;
3374
3375 /* see if we already added it */
3376 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3377 amdgpu_encoder = to_amdgpu_encoder(encoder);
3378 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3379 amdgpu_encoder->devices |= supported_device;
3380 return;
3381 }
3382
3383 }
3384
3385 /* add a new one */
3386 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3387 if (!amdgpu_encoder)
3388 return;
3389
3390 encoder = &amdgpu_encoder->base;
3391 switch (adev->mode_info.num_crtc) {
3392 case 1:
3393 encoder->possible_crtcs = 0x1;
3394 break;
3395 case 2:
3396 default:
3397 encoder->possible_crtcs = 0x3;
3398 break;
3399 case 4:
3400 encoder->possible_crtcs = 0xf;
3401 break;
3402 case 6:
3403 encoder->possible_crtcs = 0x3f;
3404 break;
3405 }
3406
3407 amdgpu_encoder->enc_priv = NULL;
3408
3409 amdgpu_encoder->encoder_enum = encoder_enum;
3410 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3411 amdgpu_encoder->devices = supported_device;
3412 amdgpu_encoder->rmx_type = RMX_OFF;
3413 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3414 amdgpu_encoder->is_ext_encoder = false;
3415 amdgpu_encoder->caps = caps;
3416
3417 switch (amdgpu_encoder->encoder_id) {
3418 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3419 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3420 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3421 DRM_MODE_ENCODER_DAC, NULL);
3422 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3423 break;
3424 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3425 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3426 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3427 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3428 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3429 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3430 amdgpu_encoder->rmx_type = RMX_FULL;
3431 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3432 DRM_MODE_ENCODER_LVDS, NULL);
3433 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3434 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3435 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3436 DRM_MODE_ENCODER_DAC, NULL);
3437 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3438 } else {
3439 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3440 DRM_MODE_ENCODER_TMDS, NULL);
3441 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3442 }
3443 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3444 break;
3445 case ENCODER_OBJECT_ID_SI170B:
3446 case ENCODER_OBJECT_ID_CH7303:
3447 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3448 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3449 case ENCODER_OBJECT_ID_TITFP513:
3450 case ENCODER_OBJECT_ID_VT1623:
3451 case ENCODER_OBJECT_ID_HDMI_SI1930:
3452 case ENCODER_OBJECT_ID_TRAVIS:
3453 case ENCODER_OBJECT_ID_NUTMEG:
3454 /* these are handled by the primary encoders */
3455 amdgpu_encoder->is_ext_encoder = true;
3456 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3457 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3458 DRM_MODE_ENCODER_LVDS, NULL);
3459 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3460 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3461 DRM_MODE_ENCODER_DAC, NULL);
3462 else
3463 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3464 DRM_MODE_ENCODER_TMDS, NULL);
3465 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3466 break;
3467 }
3468 }
3469
3470 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3471 .bandwidth_update = &dce_v8_0_bandwidth_update,
3472 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3473 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3474 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3475 .hpd_sense = &dce_v8_0_hpd_sense,
3476 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3477 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3478 .page_flip = &dce_v8_0_page_flip,
3479 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3480 .add_encoder = &dce_v8_0_encoder_add,
3481 .add_connector = &amdgpu_connector_add,
3482 };
3483
3484 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3485 {
3486 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3487 }
3488
3489 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3490 .set = dce_v8_0_set_crtc_interrupt_state,
3491 .process = dce_v8_0_crtc_irq,
3492 };
3493
3494 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3495 .set = dce_v8_0_set_pageflip_interrupt_state,
3496 .process = dce_v8_0_pageflip_irq,
3497 };
3498
3499 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3500 .set = dce_v8_0_set_hpd_interrupt_state,
3501 .process = dce_v8_0_hpd_irq,
3502 };
3503
3504 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3505 {
3506 if (adev->mode_info.num_crtc > 0)
3507 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3508 else
3509 adev->crtc_irq.num_types = 0;
3510 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3511
3512 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3513 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3514
3515 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3516 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3517 }
3518
3519 const struct amdgpu_ip_block_version dce_v8_0_ip_block =
3520 {
3521 .type = AMD_IP_BLOCK_TYPE_DCE,
3522 .major = 8,
3523 .minor = 0,
3524 .rev = 0,
3525 .funcs = &dce_v8_0_ip_funcs,
3526 };
3527
3528 const struct amdgpu_ip_block_version dce_v8_1_ip_block =
3529 {
3530 .type = AMD_IP_BLOCK_TYPE_DCE,
3531 .major = 8,
3532 .minor = 1,
3533 .rev = 0,
3534 .funcs = &dce_v8_0_ip_funcs,
3535 };
3536
3537 const struct amdgpu_ip_block_version dce_v8_2_ip_block =
3538 {
3539 .type = AMD_IP_BLOCK_TYPE_DCE,
3540 .major = 8,
3541 .minor = 2,
3542 .rev = 0,
3543 .funcs = &dce_v8_0_ip_funcs,
3544 };
3545
3546 const struct amdgpu_ip_block_version dce_v8_3_ip_block =
3547 {
3548 .type = AMD_IP_BLOCK_TYPE_DCE,
3549 .major = 8,
3550 .minor = 3,
3551 .rev = 0,
3552 .funcs = &dce_v8_0_ip_funcs,
3553 };
3554
3555 const struct amdgpu_ip_block_version dce_v8_5_ip_block =
3556 {
3557 .type = AMD_IP_BLOCK_TYPE_DCE,
3558 .major = 8,
3559 .minor = 5,
3560 .rev = 0,
3561 .funcs = &dce_v8_0_ip_funcs,
3562 };
Linux with added FPC-III support