drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "gfxhub_v1_0.h"
  25
  26 #include "gc/gc_9_0_offset.h"
  27 #include "gc/gc_9_0_sh_mask.h"
  28 #include "gc/gc_9_0_default.h"
  29 #include "vega10_enum.h"
  30
  31 #include "soc15_common.h"
  32
  33 u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
  34 {
  35         return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
  36 }
  37
  38 void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  39                                 uint64_t page_table_base)
  40 {
  41         /* two registers distance between mmVM_CONTEXT0_* to mmVM_CONTEXT1_* */
  42         int offset = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
  43                         - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
  44
  45         WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  46                                 offset * vmid, lower_32_bits(page_table_base));
  47
  48         WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  49                                 offset * vmid, upper_32_bits(page_table_base));
  50 }
  51
  52 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  53 {
  54         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  55
  56         gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
  57
  58         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  59                      (u32)(adev->gmc.gart_start >> 12));
  60         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  61                      (u32)(adev->gmc.gart_start >> 44));
  62
  63         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  64                      (u32)(adev->gmc.gart_end >> 12));
  65         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  66                      (u32)(adev->gmc.gart_end >> 44));
  67 }
  68
  69 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
  70 {
  71         uint64_t value;
  72
  73         /* Program the AGP BAR */
  74         WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);
  75         WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
  76         WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
  77
  78         if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {
  79                 /* Program the system aperture low logical page number. */
  80                 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
  81                         min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
  82
  83                 if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
  84                         /*
  85                         * Raven2 has a HW issue that it is unable to use the
  86                         * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
  87                         * So here is the workaround that increase system
  88                         * aperture high address (add 1) to get rid of the VM
  89                         * fault and hardware hang.
  90                         */
  91                         WREG32_SOC15_RLC(GC, 0,
  92                                          mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  93                                          max((adev->gmc.fb_end >> 18) + 0x1,
  94                                              adev->gmc.agp_end >> 18));
  95                 else
  96                         WREG32_SOC15_RLC(
  97                                 GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  98                                 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
  99
 100                 /* Set default page address. */
 101                 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
 102                         adev->vm_manager.vram_base_offset;
 103                 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 104                              (u32)(value >> 12));
 105                 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 106                              (u32)(value >> 44));
 107
 108                 /* Program "protection fault". */
 109                 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 110                              (u32)(adev->dummy_page_addr >> 12));
 111                 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 112                              (u32)((u64)adev->dummy_page_addr >> 44));
 113
 114                 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
 115                                ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 116         }
 117 }
 118
 119 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 120 {
 121         uint32_t tmp;
 122
 123         /* Setup TLB control */
 124         tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
 125
 126         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 127         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 128         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 129                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 130         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 131                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 132         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 133         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 134                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 135         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 136
 137         WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 138 }
 139
 140 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 141 {
 142         uint32_t tmp;
 143
 144         /* Setup L2 cache */
 145         tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
 146         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 147         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 148         /* XXX for emulation, Refer to closed source code.*/
 149         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 150                             0);
 151         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 152         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 153         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 154         WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
 155
 156         tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
 157         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 158         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 159         WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
 160
 161         tmp = mmVM_L2_CNTL3_DEFAULT;
 162         if (adev->gmc.translate_further) {
 163                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 164                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 165                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 166         } else {
 167                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 168                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 169                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 170         }
 171         WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
 172
 173         tmp = mmVM_L2_CNTL4_DEFAULT;
 174         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 175         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 176         WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
 177 }
 178
 179 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 180 {
 181         uint32_t tmp;
 182
 183         tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
 184         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 185         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 186         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
 187                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 188         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
 189 }
 190
 191 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 192 {
 193         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 194                      0XFFFFFFFF);
 195         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 196                      0x0000000F);
 197
 198         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 199                      0);
 200         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 201                      0);
 202
 203         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 204         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 205
 206 }
 207
 208 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 209 {
 210         unsigned num_level, block_size;
 211         uint32_t tmp;
 212         int i;
 213
 214         num_level = adev->vm_manager.num_level;
 215         block_size = adev->vm_manager.block_size;
 216         if (adev->gmc.translate_further)
 217                 num_level -= 1;
 218         else
 219                 block_size -= 9;
 220
 221         for (i = 0; i <= 14; i++) {
 222                 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
 223                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 224                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 225                                     num_level);
 226                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 227                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 228                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 229                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 230                                     1);
 231                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 232                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 233                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 234                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 235                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 236                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 237                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 238                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 239                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 240                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 241                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 242                                     PAGE_TABLE_BLOCK_SIZE,
 243                                     block_size);
 244                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 245                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 246                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 247                                     !amdgpu_noretry);
 248                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
 249                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
 250                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
 251                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,  i*2,
 252                         lower_32_bits(adev->vm_manager.max_pfn - 1));
 253                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
 254                         upper_32_bits(adev->vm_manager.max_pfn - 1));
 255         }
 256 }
 257
 258 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 259 {
 260         unsigned i;
 261
 262         for (i = 0 ; i < 18; ++i) {
 263                 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 264                                     2 * i, 0xffffffff);
 265                 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 266                                     2 * i, 0x1f);
 267         }
 268 }
 269
 270 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 271 {
 272         if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) {
 273                 /*
 274                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 275                  * VF copy registers so vbios post doesn't program them, for
 276                  * SRIOV driver need to program them
 277                  */
 278                 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE,
 279                              adev->gmc.vram_start >> 24);
 280                 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP,
 281                              adev->gmc.vram_end >> 24);
 282         }
 283
 284         /* GART Enable. */
 285         gfxhub_v1_0_init_gart_aperture_regs(adev);
 286         gfxhub_v1_0_init_system_aperture_regs(adev);
 287         gfxhub_v1_0_init_tlb_regs(adev);
 288         if (!amdgpu_sriov_vf(adev))
 289                 gfxhub_v1_0_init_cache_regs(adev);
 290
 291         gfxhub_v1_0_enable_system_domain(adev);
 292         if (!amdgpu_sriov_vf(adev))
 293                 gfxhub_v1_0_disable_identity_aperture(adev);
 294         gfxhub_v1_0_setup_vmid_config(adev);
 295         gfxhub_v1_0_program_invalidation(adev);
 296
 297         return 0;
 298 }
 299
 300 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
 301 {
 302         u32 tmp;
 303         u32 i;
 304
 305         /* Disable all tables */
 306         for (i = 0; i < 16; i++)
 307                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0);
 308
 309         /* Setup TLB control */
 310         tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
 311         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 312         tmp = REG_SET_FIELD(tmp,
 313                                 MC_VM_MX_L1_TLB_CNTL,
 314                                 ENABLE_ADVANCED_DRIVER_MODEL,
 315                                 0);
 316         WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 317
 318         /* Setup L2 cache */
 319         WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 320         WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
 321 }
 322
 323 /**
 324  * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 325  *
 326  * @adev: amdgpu_device pointer
 327  * @value: true redirects VM faults to the default page
 328  */
 329 void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
 330                                           bool value)
 331 {
 332         u32 tmp;
 333         tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 334         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 335                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 336         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 337                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 338         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 339                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 340         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 341                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 342         tmp = REG_SET_FIELD(tmp,
 343                         VM_L2_PROTECTION_FAULT_CNTL,
 344                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 345                         value);
 346         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 347                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 348         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 349                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 350         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 351                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 352         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 353                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 354         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 355                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 356         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 357                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 358         if (!value) {
 359                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 360                                 CRASH_ON_NO_RETRY_FAULT, 1);
 361                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 362                                 CRASH_ON_RETRY_FAULT, 1);
 363     }
 364         WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 365 }
 366
 367 void gfxhub_v1_0_init(struct amdgpu_device *adev)
 368 {
 369         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 370
 371         hub->ctx0_ptb_addr_lo32 =
 372                 SOC15_REG_OFFSET(GC, 0,
 373                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 374         hub->ctx0_ptb_addr_hi32 =
 375                 SOC15_REG_OFFSET(GC, 0,
 376                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 377         hub->vm_inv_eng0_sem =
 378                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
 379         hub->vm_inv_eng0_req =
 380                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
 381         hub->vm_inv_eng0_ack =
 382                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
 383         hub->vm_context0_cntl =
 384                 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
 385         hub->vm_l2_pro_fault_status =
 386                 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
 387         hub->vm_l2_pro_fault_cntl =
 388                 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 389 }