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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / amdgpu / gmc_v6_0.c
blobb205039350b6c9d469ecdb3d738a71ea3cb40f17
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include <drm/drm_cache.h>
29 #include "amdgpu.h"
30 #include "gmc_v6_0.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_gem.h"
33
34 #include "bif/bif_3_0_d.h"
35 #include "bif/bif_3_0_sh_mask.h"
36 #include "oss/oss_1_0_d.h"
37 #include "oss/oss_1_0_sh_mask.h"
38 #include "gmc/gmc_6_0_d.h"
39 #include "gmc/gmc_6_0_sh_mask.h"
40 #include "dce/dce_6_0_d.h"
41 #include "dce/dce_6_0_sh_mask.h"
42 #include "si_enums.h"
43
44 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
45 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
46 static int gmc_v6_0_wait_for_idle(void *handle);
47
48 MODULE_FIRMWARE("amdgpu/tahiti_mc.bin");
49 MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");
50 MODULE_FIRMWARE("amdgpu/verde_mc.bin");
51 MODULE_FIRMWARE("amdgpu/oland_mc.bin");
52 MODULE_FIRMWARE("amdgpu/hainan_mc.bin");
53 MODULE_FIRMWARE("amdgpu/si58_mc.bin");
54
55 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
56 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
57 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
58 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
59 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
60 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
61 #define MC_SEQ_MISC0__MT__HBM 0x60000000
62 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
63
64
65 static const u32 crtc_offsets[6] =
66 {
67 SI_CRTC0_REGISTER_OFFSET,
68 SI_CRTC1_REGISTER_OFFSET,
69 SI_CRTC2_REGISTER_OFFSET,
70 SI_CRTC3_REGISTER_OFFSET,
71 SI_CRTC4_REGISTER_OFFSET,
72 SI_CRTC5_REGISTER_OFFSET
73 };
74
75 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
76 {
77 u32 blackout;
78
79 gmc_v6_0_wait_for_idle((void *)adev);
80
81 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
82 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
83 /* Block CPU access */
84 WREG32(mmBIF_FB_EN, 0);
85 /* blackout the MC */
86 blackout = REG_SET_FIELD(blackout,
87 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
88 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
89 }
90 /* wait for the MC to settle */
91 udelay(100);
92
93 }
94
95 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
96 {
97 u32 tmp;
98
99 /* unblackout the MC */
100 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
101 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
102 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
103 /* allow CPU access */
104 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
105 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
106 WREG32(mmBIF_FB_EN, tmp);
107 }
108
109 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
110 {
111 const char *chip_name;
112 char fw_name[30];
113 int err;
114 bool is_58_fw = false;
115
116 DRM_DEBUG("\n");
117
118 switch (adev->asic_type) {
119 case CHIP_TAHITI:
120 chip_name = "tahiti";
121 break;
122 case CHIP_PITCAIRN:
123 chip_name = "pitcairn";
124 break;
125 case CHIP_VERDE:
126 chip_name = "verde";
127 break;
128 case CHIP_OLAND:
129 chip_name = "oland";
130 break;
131 case CHIP_HAINAN:
132 chip_name = "hainan";
133 break;
134 default: BUG();
135 }
136
137 /* this memory configuration requires special firmware */
138 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
139 is_58_fw = true;
140
141 if (is_58_fw)
142 snprintf(fw_name, sizeof(fw_name), "amdgpu/si58_mc.bin");
143 else
144 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
145 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
146 if (err)
147 goto out;
148
149 err = amdgpu_ucode_validate(adev->gmc.fw);
150
151 out:
152 if (err) {
153 dev_err(adev->dev,
154 "si_mc: Failed to load firmware \"%s\"\n",
155 fw_name);
156 release_firmware(adev->gmc.fw);
157 adev->gmc.fw = NULL;
158 }
159 return err;
160 }
161
162 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
163 {
164 const __le32 *new_fw_data = NULL;
165 u32 running;
166 const __le32 *new_io_mc_regs = NULL;
167 int i, regs_size, ucode_size;
168 const struct mc_firmware_header_v1_0 *hdr;
169
170 if (!adev->gmc.fw)
171 return -EINVAL;
172
173 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
174
175 amdgpu_ucode_print_mc_hdr(&hdr->header);
176
177 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
178 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
179 new_io_mc_regs = (const __le32 *)
180 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
181 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
182 new_fw_data = (const __le32 *)
183 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
184
185 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
186
187 if (running == 0) {
188
189 /* reset the engine and set to writable */
190 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
191 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
192
193 /* load mc io regs */
194 for (i = 0; i < regs_size; i++) {
195 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
196 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
197 }
198 /* load the MC ucode */
199 for (i = 0; i < ucode_size; i++) {
200 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
201 }
202
203 /* put the engine back into the active state */
204 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
205 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
206 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
207
208 /* wait for training to complete */
209 for (i = 0; i < adev->usec_timeout; i++) {
210 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
211 break;
212 udelay(1);
213 }
214 for (i = 0; i < adev->usec_timeout; i++) {
215 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
216 break;
217 udelay(1);
218 }
219
220 }
221
222 return 0;
223 }
224
225 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
226 struct amdgpu_gmc *mc)
227 {
228 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
229 base <<= 24;
230
231 amdgpu_gmc_vram_location(adev, mc, base);
232 amdgpu_gmc_gart_location(adev, mc);
233 }
234
235 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
236 {
237 int i, j;
238
239 /* Initialize HDP */
240 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
241 WREG32((0xb05 + j), 0x00000000);
242 WREG32((0xb06 + j), 0x00000000);
243 WREG32((0xb07 + j), 0x00000000);
244 WREG32((0xb08 + j), 0x00000000);
245 WREG32((0xb09 + j), 0x00000000);
246 }
247 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
248
249 if (gmc_v6_0_wait_for_idle((void *)adev)) {
250 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
251 }
252
253 if (adev->mode_info.num_crtc) {
254 u32 tmp;
255
256 /* Lockout access through VGA aperture*/
257 tmp = RREG32(mmVGA_HDP_CONTROL);
258 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
259 WREG32(mmVGA_HDP_CONTROL, tmp);
260
261 /* disable VGA render */
262 tmp = RREG32(mmVGA_RENDER_CONTROL);
263 tmp &= ~VGA_VSTATUS_CNTL;
264 WREG32(mmVGA_RENDER_CONTROL, tmp);
265 }
266 /* Update configuration */
267 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
268 adev->gmc.vram_start >> 12);
269 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
270 adev->gmc.vram_end >> 12);
271 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
272 adev->vram_scratch.gpu_addr >> 12);
273 WREG32(mmMC_VM_AGP_BASE, 0);
274 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
275 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
276
277 if (gmc_v6_0_wait_for_idle((void *)adev)) {
278 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
279 }
280 }
281
282 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
283 {
284
285 u32 tmp;
286 int chansize, numchan;
287 int r;
288
289 tmp = RREG32(mmMC_ARB_RAMCFG);
290 if (tmp & (1 << 11)) {
291 chansize = 16;
292 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
293 chansize = 64;
294 } else {
295 chansize = 32;
296 }
297 tmp = RREG32(mmMC_SHARED_CHMAP);
298 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
299 case 0:
300 default:
301 numchan = 1;
302 break;
303 case 1:
304 numchan = 2;
305 break;
306 case 2:
307 numchan = 4;
308 break;
309 case 3:
310 numchan = 8;
311 break;
312 case 4:
313 numchan = 3;
314 break;
315 case 5:
316 numchan = 6;
317 break;
318 case 6:
319 numchan = 10;
320 break;
321 case 7:
322 numchan = 12;
323 break;
324 case 8:
325 numchan = 16;
326 break;
327 }
328 adev->gmc.vram_width = numchan * chansize;
329 /* size in MB on si */
330 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
331 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
332
333 if (!(adev->flags & AMD_IS_APU)) {
334 r = amdgpu_device_resize_fb_bar(adev);
335 if (r)
336 return r;
337 }
338 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
339 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
340 adev->gmc.visible_vram_size = adev->gmc.aper_size;
341
342 /* set the gart size */
343 if (amdgpu_gart_size == -1) {
344 switch (adev->asic_type) {
345 case CHIP_HAINAN: /* no MM engines */
346 default:
347 adev->gmc.gart_size = 256ULL << 20;
348 break;
349 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
350 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
351 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
352 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
353 adev->gmc.gart_size = 1024ULL << 20;
354 break;
355 }
356 } else {
357 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
358 }
359
360 gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
361
362 return 0;
363 }
364
365 static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
366 uint32_t vmhub, uint32_t flush_type)
367 {
368 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
369 }
370
371 static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
372 unsigned vmid, uint64_t pd_addr)
373 {
374 uint32_t reg;
375
376 /* write new base address */
377 if (vmid < 8)
378 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
379 else
380 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
381 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
382
383 /* bits 0-15 are the VM contexts0-15 */
384 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
385
386 return pd_addr;
387 }
388
389 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
390 uint64_t *addr, uint64_t *flags)
391 {
392 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
393 }
394
395 static void gmc_v6_0_get_vm_pte(struct amdgpu_device *adev,
396 struct amdgpu_bo_va_mapping *mapping,
397 uint64_t *flags)
398 {
399 *flags &= ~AMDGPU_PTE_EXECUTABLE;
400 *flags &= ~AMDGPU_PTE_PRT;
401 }
402
403 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
404 bool value)
405 {
406 u32 tmp;
407
408 tmp = RREG32(mmVM_CONTEXT1_CNTL);
409 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
410 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
411 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
412 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
413 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
414 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
415 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
416 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
417 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
418 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
419 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
420 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
421 WREG32(mmVM_CONTEXT1_CNTL, tmp);
422 }
423
424 /**
425 + * gmc_v8_0_set_prt - set PRT VM fault
426 + *
427 + * @adev: amdgpu_device pointer
428 + * @enable: enable/disable VM fault handling for PRT
429 +*/
430 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
431 {
432 u32 tmp;
433
434 if (enable && !adev->gmc.prt_warning) {
435 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
436 adev->gmc.prt_warning = true;
437 }
438
439 tmp = RREG32(mmVM_PRT_CNTL);
440 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
441 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
442 enable);
443 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
444 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
445 enable);
446 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
447 L2_CACHE_STORE_INVALID_ENTRIES,
448 enable);
449 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
450 L1_TLB_STORE_INVALID_ENTRIES,
451 enable);
452 WREG32(mmVM_PRT_CNTL, tmp);
453
454 if (enable) {
455 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
456 uint32_t high = adev->vm_manager.max_pfn -
457 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
458
459 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
460 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
461 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
462 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
463 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
464 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
465 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
466 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
467 } else {
468 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
469 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
470 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
471 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
472 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
473 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
474 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
475 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
476 }
477 }
478
479 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
480 {
481 uint64_t table_addr;
482 int r, i;
483 u32 field;
484
485 if (adev->gart.bo == NULL) {
486 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
487 return -EINVAL;
488 }
489 r = amdgpu_gart_table_vram_pin(adev);
490 if (r)
491 return r;
492
493 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
494
495 /* Setup TLB control */
496 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
497 (0xA << 7) |
498 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
499 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
500 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
501 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
502 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
503 /* Setup L2 cache */
504 WREG32(mmVM_L2_CNTL,
505 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
506 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
507 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
508 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
509 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
510 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
511 WREG32(mmVM_L2_CNTL2,
512 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
513 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
514
515 field = adev->vm_manager.fragment_size;
516 WREG32(mmVM_L2_CNTL3,
517 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
518 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
519 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
520 /* setup context0 */
521 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
522 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
523 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
524 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
525 (u32)(adev->dummy_page_addr >> 12));
526 WREG32(mmVM_CONTEXT0_CNTL2, 0);
527 WREG32(mmVM_CONTEXT0_CNTL,
528 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
529 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
530 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
531
532 WREG32(0x575, 0);
533 WREG32(0x576, 0);
534 WREG32(0x577, 0);
535
536 /* empty context1-15 */
537 /* set vm size, must be a multiple of 4 */
538 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
539 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
540 /* Assign the pt base to something valid for now; the pts used for
541 * the VMs are determined by the application and setup and assigned
542 * on the fly in the vm part of radeon_gart.c
543 */
544 for (i = 1; i < 16; i++) {
545 if (i < 8)
546 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
547 table_addr >> 12);
548 else
549 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
550 table_addr >> 12);
551 }
552
553 /* enable context1-15 */
554 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
555 (u32)(adev->dummy_page_addr >> 12));
556 WREG32(mmVM_CONTEXT1_CNTL2, 4);
557 WREG32(mmVM_CONTEXT1_CNTL,
558 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
559 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
560 ((adev->vm_manager.block_size - 9)
561 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
562 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
563 gmc_v6_0_set_fault_enable_default(adev, false);
564 else
565 gmc_v6_0_set_fault_enable_default(adev, true);
566
567 gmc_v6_0_flush_gpu_tlb(adev, 0, 0, 0);
568 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
569 (unsigned)(adev->gmc.gart_size >> 20),
570 (unsigned long long)table_addr);
571 adev->gart.ready = true;
572 return 0;
573 }
574
575 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
576 {
577 int r;
578
579 if (adev->gart.bo) {
580 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
581 return 0;
582 }
583 r = amdgpu_gart_init(adev);
584 if (r)
585 return r;
586 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
587 adev->gart.gart_pte_flags = 0;
588 return amdgpu_gart_table_vram_alloc(adev);
589 }
590
591 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
592 {
593 /*unsigned i;
594
595 for (i = 1; i < 16; ++i) {
596 uint32_t reg;
597 if (i < 8)
598 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
599 else
600 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
601 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
602 }*/
603
604 /* Disable all tables */
605 WREG32(mmVM_CONTEXT0_CNTL, 0);
606 WREG32(mmVM_CONTEXT1_CNTL, 0);
607 /* Setup TLB control */
608 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
609 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
610 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
611 /* Setup L2 cache */
612 WREG32(mmVM_L2_CNTL,
613 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
614 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
615 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
616 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
617 WREG32(mmVM_L2_CNTL2, 0);
618 WREG32(mmVM_L2_CNTL3,
619 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
620 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
621 amdgpu_gart_table_vram_unpin(adev);
622 }
623
624 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
625 u32 status, u32 addr, u32 mc_client)
626 {
627 u32 mc_id;
628 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
629 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
630 PROTECTIONS);
631 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
632 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
633
634 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
635 MEMORY_CLIENT_ID);
636
637 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
638 protections, vmid, addr,
639 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
640 MEMORY_CLIENT_RW) ?
641 "write" : "read", block, mc_client, mc_id);
642 }
643
644 /*
645 static const u32 mc_cg_registers[] = {
646 MC_HUB_MISC_HUB_CG,
647 MC_HUB_MISC_SIP_CG,
648 MC_HUB_MISC_VM_CG,
649 MC_XPB_CLK_GAT,
650 ATC_MISC_CG,
651 MC_CITF_MISC_WR_CG,
652 MC_CITF_MISC_RD_CG,
653 MC_CITF_MISC_VM_CG,
654 VM_L2_CG,
655 };
656
657 static const u32 mc_cg_ls_en[] = {
658 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
659 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
660 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
661 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
662 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
663 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
664 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
665 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
666 VM_L2_CG__MEM_LS_ENABLE_MASK,
667 };
668
669 static const u32 mc_cg_en[] = {
670 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
671 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
672 MC_HUB_MISC_VM_CG__ENABLE_MASK,
673 MC_XPB_CLK_GAT__ENABLE_MASK,
674 ATC_MISC_CG__ENABLE_MASK,
675 MC_CITF_MISC_WR_CG__ENABLE_MASK,
676 MC_CITF_MISC_RD_CG__ENABLE_MASK,
677 MC_CITF_MISC_VM_CG__ENABLE_MASK,
678 VM_L2_CG__ENABLE_MASK,
679 };
680
681 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
682 bool enable)
683 {
684 int i;
685 u32 orig, data;
686
687 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
688 orig = data = RREG32(mc_cg_registers[i]);
689 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
690 data |= mc_cg_ls_en[i];
691 else
692 data &= ~mc_cg_ls_en[i];
693 if (data != orig)
694 WREG32(mc_cg_registers[i], data);
695 }
696 }
697
698 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
699 bool enable)
700 {
701 int i;
702 u32 orig, data;
703
704 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
705 orig = data = RREG32(mc_cg_registers[i]);
706 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
707 data |= mc_cg_en[i];
708 else
709 data &= ~mc_cg_en[i];
710 if (data != orig)
711 WREG32(mc_cg_registers[i], data);
712 }
713 }
714
715 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
716 bool enable)
717 {
718 u32 orig, data;
719
720 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
721
722 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
723 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
724 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
725 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
726 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
727 } else {
728 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
729 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
730 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
731 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
732 }
733
734 if (orig != data)
735 WREG32_PCIE(ixPCIE_CNTL2, data);
736 }
737
738 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
739 bool enable)
740 {
741 u32 orig, data;
742
743 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
744
745 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
746 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
747 else
748 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
749
750 if (orig != data)
751 WREG32(mmHDP_HOST_PATH_CNTL, data);
752 }
753
754 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
755 bool enable)
756 {
757 u32 orig, data;
758
759 orig = data = RREG32(mmHDP_MEM_POWER_LS);
760
761 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
762 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
763 else
764 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
765
766 if (orig != data)
767 WREG32(mmHDP_MEM_POWER_LS, data);
768 }
769 */
770
771 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
772 {
773 switch (mc_seq_vram_type) {
774 case MC_SEQ_MISC0__MT__GDDR1:
775 return AMDGPU_VRAM_TYPE_GDDR1;
776 case MC_SEQ_MISC0__MT__DDR2:
777 return AMDGPU_VRAM_TYPE_DDR2;
778 case MC_SEQ_MISC0__MT__GDDR3:
779 return AMDGPU_VRAM_TYPE_GDDR3;
780 case MC_SEQ_MISC0__MT__GDDR4:
781 return AMDGPU_VRAM_TYPE_GDDR4;
782 case MC_SEQ_MISC0__MT__GDDR5:
783 return AMDGPU_VRAM_TYPE_GDDR5;
784 case MC_SEQ_MISC0__MT__DDR3:
785 return AMDGPU_VRAM_TYPE_DDR3;
786 default:
787 return AMDGPU_VRAM_TYPE_UNKNOWN;
788 }
789 }
790
791 static int gmc_v6_0_early_init(void *handle)
792 {
793 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
794
795 gmc_v6_0_set_gmc_funcs(adev);
796 gmc_v6_0_set_irq_funcs(adev);
797
798 return 0;
799 }
800
801 static int gmc_v6_0_late_init(void *handle)
802 {
803 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
804
805 amdgpu_bo_late_init(adev);
806
807 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
808 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
809 else
810 return 0;
811 }
812
813 static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
814 {
815 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
816 unsigned size;
817
818 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
819 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
820 } else {
821 u32 viewport = RREG32(mmVIEWPORT_SIZE);
822 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
823 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
824 4);
825 }
826 /* return 0 if the pre-OS buffer uses up most of vram */
827 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
828 return 0;
829 return size;
830 }
831
832 static int gmc_v6_0_sw_init(void *handle)
833 {
834 int r;
835 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
836
837 adev->num_vmhubs = 1;
838
839 if (adev->flags & AMD_IS_APU) {
840 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
841 } else {
842 u32 tmp = RREG32(mmMC_SEQ_MISC0);
843 tmp &= MC_SEQ_MISC0__MT__MASK;
844 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
845 }
846
847 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
848 if (r)
849 return r;
850
851 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
852 if (r)
853 return r;
854
855 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
856
857 adev->gmc.mc_mask = 0xffffffffffULL;
858
859 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
860 if (r) {
861 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
862 return r;
863 }
864 adev->need_swiotlb = drm_need_swiotlb(44);
865
866 r = gmc_v6_0_init_microcode(adev);
867 if (r) {
868 dev_err(adev->dev, "Failed to load mc firmware!\n");
869 return r;
870 }
871
872 r = gmc_v6_0_mc_init(adev);
873 if (r)
874 return r;
875
876 adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev);
877
878 r = amdgpu_bo_init(adev);
879 if (r)
880 return r;
881
882 r = gmc_v6_0_gart_init(adev);
883 if (r)
884 return r;
885
886 /*
887 * number of VMs
888 * VMID 0 is reserved for System
889 * amdgpu graphics/compute will use VMIDs 1-7
890 * amdkfd will use VMIDs 8-15
891 */
892 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
893 amdgpu_vm_manager_init(adev);
894
895 /* base offset of vram pages */
896 if (adev->flags & AMD_IS_APU) {
897 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
898
899 tmp <<= 22;
900 adev->vm_manager.vram_base_offset = tmp;
901 } else {
902 adev->vm_manager.vram_base_offset = 0;
903 }
904
905 return 0;
906 }
907
908 static int gmc_v6_0_sw_fini(void *handle)
909 {
910 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
911
912 amdgpu_gem_force_release(adev);
913 amdgpu_vm_manager_fini(adev);
914 amdgpu_gart_table_vram_free(adev);
915 amdgpu_bo_fini(adev);
916 amdgpu_gart_fini(adev);
917 release_firmware(adev->gmc.fw);
918 adev->gmc.fw = NULL;
919
920 return 0;
921 }
922
923 static int gmc_v6_0_hw_init(void *handle)
924 {
925 int r;
926 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
927
928 gmc_v6_0_mc_program(adev);
929
930 if (!(adev->flags & AMD_IS_APU)) {
931 r = gmc_v6_0_mc_load_microcode(adev);
932 if (r) {
933 dev_err(adev->dev, "Failed to load MC firmware!\n");
934 return r;
935 }
936 }
937
938 r = gmc_v6_0_gart_enable(adev);
939 if (r)
940 return r;
941
942 return r;
943 }
944
945 static int gmc_v6_0_hw_fini(void *handle)
946 {
947 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
948
949 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
950 gmc_v6_0_gart_disable(adev);
951
952 return 0;
953 }
954
955 static int gmc_v6_0_suspend(void *handle)
956 {
957 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
958
959 gmc_v6_0_hw_fini(adev);
960
961 return 0;
962 }
963
964 static int gmc_v6_0_resume(void *handle)
965 {
966 int r;
967 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
968
969 r = gmc_v6_0_hw_init(adev);
970 if (r)
971 return r;
972
973 amdgpu_vmid_reset_all(adev);
974
975 return 0;
976 }
977
978 static bool gmc_v6_0_is_idle(void *handle)
979 {
980 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
981 u32 tmp = RREG32(mmSRBM_STATUS);
982
983 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
984 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
985 return false;
986
987 return true;
988 }
989
990 static int gmc_v6_0_wait_for_idle(void *handle)
991 {
992 unsigned i;
993 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
994
995 for (i = 0; i < adev->usec_timeout; i++) {
996 if (gmc_v6_0_is_idle(handle))
997 return 0;
998 udelay(1);
999 }
1000 return -ETIMEDOUT;
1001
1002 }
1003
1004 static int gmc_v6_0_soft_reset(void *handle)
1005 {
1006 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007 u32 srbm_soft_reset = 0;
1008 u32 tmp = RREG32(mmSRBM_STATUS);
1009
1010 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1011 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1012 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1013
1014 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1015 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1016 if (!(adev->flags & AMD_IS_APU))
1017 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1018 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1019 }
1020
1021 if (srbm_soft_reset) {
1022 gmc_v6_0_mc_stop(adev);
1023 if (gmc_v6_0_wait_for_idle(adev)) {
1024 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1025 }
1026
1027
1028 tmp = RREG32(mmSRBM_SOFT_RESET);
1029 tmp |= srbm_soft_reset;
1030 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1031 WREG32(mmSRBM_SOFT_RESET, tmp);
1032 tmp = RREG32(mmSRBM_SOFT_RESET);
1033
1034 udelay(50);
1035
1036 tmp &= ~srbm_soft_reset;
1037 WREG32(mmSRBM_SOFT_RESET, tmp);
1038 tmp = RREG32(mmSRBM_SOFT_RESET);
1039
1040 udelay(50);
1041
1042 gmc_v6_0_mc_resume(adev);
1043 udelay(50);
1044 }
1045
1046 return 0;
1047 }
1048
1049 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1050 struct amdgpu_irq_src *src,
1051 unsigned type,
1052 enum amdgpu_interrupt_state state)
1053 {
1054 u32 tmp;
1055 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1056 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1057 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1058 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1059 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1060 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1061
1062 switch (state) {
1063 case AMDGPU_IRQ_STATE_DISABLE:
1064 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1065 tmp &= ~bits;
1066 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1067 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1068 tmp &= ~bits;
1069 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1070 break;
1071 case AMDGPU_IRQ_STATE_ENABLE:
1072 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1073 tmp |= bits;
1074 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1075 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1076 tmp |= bits;
1077 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1078 break;
1079 default:
1080 break;
1081 }
1082
1083 return 0;
1084 }
1085
1086 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1087 struct amdgpu_irq_src *source,
1088 struct amdgpu_iv_entry *entry)
1089 {
1090 u32 addr, status;
1091
1092 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1093 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1094 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1095
1096 if (!addr && !status)
1097 return 0;
1098
1099 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1100 gmc_v6_0_set_fault_enable_default(adev, false);
1101
1102 if (printk_ratelimit()) {
1103 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1104 entry->src_id, entry->src_data[0]);
1105 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1106 addr);
1107 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1108 status);
1109 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1110 }
1111
1112 return 0;
1113 }
1114
1115 static int gmc_v6_0_set_clockgating_state(void *handle,
1116 enum amd_clockgating_state state)
1117 {
1118 return 0;
1119 }
1120
1121 static int gmc_v6_0_set_powergating_state(void *handle,
1122 enum amd_powergating_state state)
1123 {
1124 return 0;
1125 }
1126
1127 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1128 .name = "gmc_v6_0",
1129 .early_init = gmc_v6_0_early_init,
1130 .late_init = gmc_v6_0_late_init,
1131 .sw_init = gmc_v6_0_sw_init,
1132 .sw_fini = gmc_v6_0_sw_fini,
1133 .hw_init = gmc_v6_0_hw_init,
1134 .hw_fini = gmc_v6_0_hw_fini,
1135 .suspend = gmc_v6_0_suspend,
1136 .resume = gmc_v6_0_resume,
1137 .is_idle = gmc_v6_0_is_idle,
1138 .wait_for_idle = gmc_v6_0_wait_for_idle,
1139 .soft_reset = gmc_v6_0_soft_reset,
1140 .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1141 .set_powergating_state = gmc_v6_0_set_powergating_state,
1142 };
1143
1144 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
1145 .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
1146 .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
1147 .set_prt = gmc_v6_0_set_prt,
1148 .get_vm_pde = gmc_v6_0_get_vm_pde,
1149 .get_vm_pte = gmc_v6_0_get_vm_pte,
1150 };
1151
1152 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1153 .set = gmc_v6_0_vm_fault_interrupt_state,
1154 .process = gmc_v6_0_process_interrupt,
1155 };
1156
1157 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
1158 {
1159 adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
1160 }
1161
1162 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1163 {
1164 adev->gmc.vm_fault.num_types = 1;
1165 adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1166 }
1167
1168 const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1169 {
1170 .type = AMD_IP_BLOCK_TYPE_GMC,
1171 .major = 6,
1172 .minor = 0,
1173 .rev = 0,
1174 .funcs = &gmc_v6_0_ip_funcs,
1175 };
Linux with added FPC-III support