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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / amdgpu / gmc_v7_0.c
blob19d5b133e1d7e7cabddf4693834397130ed72294
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include <drm/drm_cache.h>
29 #include "amdgpu.h"
30 #include "cikd.h"
31 #include "cik.h"
32 #include "gmc_v7_0.h"
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_amdkfd.h"
35 #include "amdgpu_gem.h"
36
37 #include "bif/bif_4_1_d.h"
38 #include "bif/bif_4_1_sh_mask.h"
39
40 #include "gmc/gmc_7_1_d.h"
41 #include "gmc/gmc_7_1_sh_mask.h"
42
43 #include "oss/oss_2_0_d.h"
44 #include "oss/oss_2_0_sh_mask.h"
45
46 #include "dce/dce_8_0_d.h"
47 #include "dce/dce_8_0_sh_mask.h"
48
49 #include "amdgpu_atombios.h"
50
51 #include "ivsrcid/ivsrcid_vislands30.h"
52
53 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
54 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55 static int gmc_v7_0_wait_for_idle(void *handle);
56
57 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin");
58 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin");
59 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
60
61 static const u32 golden_settings_iceland_a11[] =
62 {
63 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
64 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
65 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
66 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
67 };
68
69 static const u32 iceland_mgcg_cgcg_init[] =
70 {
71 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
72 };
73
74 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
75 {
76 switch (adev->asic_type) {
77 case CHIP_TOPAZ:
78 amdgpu_device_program_register_sequence(adev,
79 iceland_mgcg_cgcg_init,
80 ARRAY_SIZE(iceland_mgcg_cgcg_init));
81 amdgpu_device_program_register_sequence(adev,
82 golden_settings_iceland_a11,
83 ARRAY_SIZE(golden_settings_iceland_a11));
84 break;
85 default:
86 break;
87 }
88 }
89
90 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
91 {
92 u32 blackout;
93
94 gmc_v7_0_wait_for_idle((void *)adev);
95
96 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
97 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
98 /* Block CPU access */
99 WREG32(mmBIF_FB_EN, 0);
100 /* blackout the MC */
101 blackout = REG_SET_FIELD(blackout,
102 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
103 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
104 }
105 /* wait for the MC to settle */
106 udelay(100);
107 }
108
109 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
110 {
111 u32 tmp;
112
113 /* unblackout the MC */
114 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
115 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
116 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
117 /* allow CPU access */
118 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
119 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
120 WREG32(mmBIF_FB_EN, tmp);
121 }
122
123 /**
124 * gmc_v7_0_init_microcode - load ucode images from disk
125 *
126 * @adev: amdgpu_device pointer
127 *
128 * Use the firmware interface to load the ucode images into
129 * the driver (not loaded into hw).
130 * Returns 0 on success, error on failure.
131 */
132 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
133 {
134 const char *chip_name;
135 char fw_name[30];
136 int err;
137
138 DRM_DEBUG("\n");
139
140 switch (adev->asic_type) {
141 case CHIP_BONAIRE:
142 chip_name = "bonaire";
143 break;
144 case CHIP_HAWAII:
145 chip_name = "hawaii";
146 break;
147 case CHIP_TOPAZ:
148 chip_name = "topaz";
149 break;
150 case CHIP_KAVERI:
151 case CHIP_KABINI:
152 case CHIP_MULLINS:
153 return 0;
154 default: BUG();
155 }
156
157 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
158
159 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
160 if (err)
161 goto out;
162 err = amdgpu_ucode_validate(adev->gmc.fw);
163
164 out:
165 if (err) {
166 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
167 release_firmware(adev->gmc.fw);
168 adev->gmc.fw = NULL;
169 }
170 return err;
171 }
172
173 /**
174 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
175 *
176 * @adev: amdgpu_device pointer
177 *
178 * Load the GDDR MC ucode into the hw (CIK).
179 * Returns 0 on success, error on failure.
180 */
181 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
182 {
183 const struct mc_firmware_header_v1_0 *hdr;
184 const __le32 *fw_data = NULL;
185 const __le32 *io_mc_regs = NULL;
186 u32 running;
187 int i, ucode_size, regs_size;
188
189 if (!adev->gmc.fw)
190 return -EINVAL;
191
192 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
193 amdgpu_ucode_print_mc_hdr(&hdr->header);
194
195 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
196 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
197 io_mc_regs = (const __le32 *)
198 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
199 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
200 fw_data = (const __le32 *)
201 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
202
203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
204
205 if (running == 0) {
206 /* reset the engine and set to writable */
207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
209
210 /* load mc io regs */
211 for (i = 0; i < regs_size; i++) {
212 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
213 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
214 }
215 /* load the MC ucode */
216 for (i = 0; i < ucode_size; i++)
217 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
218
219 /* put the engine back into the active state */
220 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
221 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
222 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
223
224 /* wait for training to complete */
225 for (i = 0; i < adev->usec_timeout; i++) {
226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
227 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
228 break;
229 udelay(1);
230 }
231 for (i = 0; i < adev->usec_timeout; i++) {
232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
233 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
234 break;
235 udelay(1);
236 }
237 }
238
239 return 0;
240 }
241
242 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
243 struct amdgpu_gmc *mc)
244 {
245 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
246 base <<= 24;
247
248 amdgpu_gmc_vram_location(adev, mc, base);
249 amdgpu_gmc_gart_location(adev, mc);
250 }
251
252 /**
253 * gmc_v7_0_mc_program - program the GPU memory controller
254 *
255 * @adev: amdgpu_device pointer
256 *
257 * Set the location of vram, gart, and AGP in the GPU's
258 * physical address space (CIK).
259 */
260 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
261 {
262 u32 tmp;
263 int i, j;
264
265 /* Initialize HDP */
266 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
267 WREG32((0xb05 + j), 0x00000000);
268 WREG32((0xb06 + j), 0x00000000);
269 WREG32((0xb07 + j), 0x00000000);
270 WREG32((0xb08 + j), 0x00000000);
271 WREG32((0xb09 + j), 0x00000000);
272 }
273 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
274
275 if (gmc_v7_0_wait_for_idle((void *)adev)) {
276 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
277 }
278 if (adev->mode_info.num_crtc) {
279 /* Lockout access through VGA aperture*/
280 tmp = RREG32(mmVGA_HDP_CONTROL);
281 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
282 WREG32(mmVGA_HDP_CONTROL, tmp);
283
284 /* disable VGA render */
285 tmp = RREG32(mmVGA_RENDER_CONTROL);
286 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
287 WREG32(mmVGA_RENDER_CONTROL, tmp);
288 }
289 /* Update configuration */
290 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
291 adev->gmc.vram_start >> 12);
292 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
293 adev->gmc.vram_end >> 12);
294 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
295 adev->vram_scratch.gpu_addr >> 12);
296 WREG32(mmMC_VM_AGP_BASE, 0);
297 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
298 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
299 if (gmc_v7_0_wait_for_idle((void *)adev)) {
300 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
301 }
302
303 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
304
305 tmp = RREG32(mmHDP_MISC_CNTL);
306 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
307 WREG32(mmHDP_MISC_CNTL, tmp);
308
309 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
310 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
311 }
312
313 /**
314 * gmc_v7_0_mc_init - initialize the memory controller driver params
315 *
316 * @adev: amdgpu_device pointer
317 *
318 * Look up the amount of vram, vram width, and decide how to place
319 * vram and gart within the GPU's physical address space (CIK).
320 * Returns 0 for success.
321 */
322 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
323 {
324 int r;
325
326 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
327 if (!adev->gmc.vram_width) {
328 u32 tmp;
329 int chansize, numchan;
330
331 /* Get VRAM informations */
332 tmp = RREG32(mmMC_ARB_RAMCFG);
333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
334 chansize = 64;
335 } else {
336 chansize = 32;
337 }
338 tmp = RREG32(mmMC_SHARED_CHMAP);
339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
340 case 0:
341 default:
342 numchan = 1;
343 break;
344 case 1:
345 numchan = 2;
346 break;
347 case 2:
348 numchan = 4;
349 break;
350 case 3:
351 numchan = 8;
352 break;
353 case 4:
354 numchan = 3;
355 break;
356 case 5:
357 numchan = 6;
358 break;
359 case 6:
360 numchan = 10;
361 break;
362 case 7:
363 numchan = 12;
364 break;
365 case 8:
366 numchan = 16;
367 break;
368 }
369 adev->gmc.vram_width = numchan * chansize;
370 }
371 /* size in MB on si */
372 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
373 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
374
375 if (!(adev->flags & AMD_IS_APU)) {
376 r = amdgpu_device_resize_fb_bar(adev);
377 if (r)
378 return r;
379 }
380 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
381 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
382
383 #ifdef CONFIG_X86_64
384 if (adev->flags & AMD_IS_APU) {
385 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
386 adev->gmc.aper_size = adev->gmc.real_vram_size;
387 }
388 #endif
389
390 /* In case the PCI BAR is larger than the actual amount of vram */
391 adev->gmc.visible_vram_size = adev->gmc.aper_size;
392 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
393 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
394
395 /* set the gart size */
396 if (amdgpu_gart_size == -1) {
397 switch (adev->asic_type) {
398 case CHIP_TOPAZ: /* no MM engines */
399 default:
400 adev->gmc.gart_size = 256ULL << 20;
401 break;
402 #ifdef CONFIG_DRM_AMDGPU_CIK
403 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
404 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */
405 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */
406 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */
407 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
408 adev->gmc.gart_size = 1024ULL << 20;
409 break;
410 #endif
411 }
412 } else {
413 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
414 }
415
416 gmc_v7_0_vram_gtt_location(adev, &adev->gmc);
417
418 return 0;
419 }
420
421 /**
422 * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
423 *
424 * @adev: amdgpu_device pointer
425 * @pasid: pasid to be flush
426 *
427 * Flush the TLB for the requested pasid.
428 */
429 static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
430 uint16_t pasid, uint32_t flush_type,
431 bool all_hub)
432 {
433 int vmid;
434 unsigned int tmp;
435
436 if (adev->in_gpu_reset)
437 return -EIO;
438
439 for (vmid = 1; vmid < 16; vmid++) {
440
441 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
442 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
443 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
444 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
445 RREG32(mmVM_INVALIDATE_RESPONSE);
446 break;
447 }
448 }
449
450 return 0;
451 }
452
453 /*
454 * GART
455 * VMID 0 is the physical GPU addresses as used by the kernel.
456 * VMIDs 1-15 are used for userspace clients and are handled
457 * by the amdgpu vm/hsa code.
458 */
459
460 /**
461 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
462 *
463 * @adev: amdgpu_device pointer
464 * @vmid: vm instance to flush
465 *
466 * Flush the TLB for the requested page table (CIK).
467 */
468 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
469 uint32_t vmhub, uint32_t flush_type)
470 {
471 /* bits 0-15 are the VM contexts0-15 */
472 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
473 }
474
475 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
476 unsigned vmid, uint64_t pd_addr)
477 {
478 uint32_t reg;
479
480 if (vmid < 8)
481 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
482 else
483 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
484 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
485
486 /* bits 0-15 are the VM contexts0-15 */
487 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
488
489 return pd_addr;
490 }
491
492 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
493 unsigned pasid)
494 {
495 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
496 }
497
498 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
499 uint64_t *addr, uint64_t *flags)
500 {
501 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
502 }
503
504 static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev,
505 struct amdgpu_bo_va_mapping *mapping,
506 uint64_t *flags)
507 {
508 *flags &= ~AMDGPU_PTE_EXECUTABLE;
509 *flags &= ~AMDGPU_PTE_PRT;
510 }
511
512 /**
513 * gmc_v8_0_set_fault_enable_default - update VM fault handling
514 *
515 * @adev: amdgpu_device pointer
516 * @value: true redirects VM faults to the default page
517 */
518 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
519 bool value)
520 {
521 u32 tmp;
522
523 tmp = RREG32(mmVM_CONTEXT1_CNTL);
524 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
525 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
526 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
527 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
528 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
529 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
530 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
531 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
532 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
533 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
534 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
535 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
536 WREG32(mmVM_CONTEXT1_CNTL, tmp);
537 }
538
539 /**
540 * gmc_v7_0_set_prt - set PRT VM fault
541 *
542 * @adev: amdgpu_device pointer
543 * @enable: enable/disable VM fault handling for PRT
544 */
545 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
546 {
547 uint32_t tmp;
548
549 if (enable && !adev->gmc.prt_warning) {
550 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
551 adev->gmc.prt_warning = true;
552 }
553
554 tmp = RREG32(mmVM_PRT_CNTL);
555 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
556 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
557 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
558 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
559 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
560 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
561 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
562 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
563 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
564 L2_CACHE_STORE_INVALID_ENTRIES, enable);
565 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
566 L1_TLB_STORE_INVALID_ENTRIES, enable);
567 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
568 MASK_PDE0_FAULT, enable);
569 WREG32(mmVM_PRT_CNTL, tmp);
570
571 if (enable) {
572 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
573 uint32_t high = adev->vm_manager.max_pfn -
574 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
575
576 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
577 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
578 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
579 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
580 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
581 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
582 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
583 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
584 } else {
585 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
586 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
587 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
588 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
589 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
590 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
591 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
592 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
593 }
594 }
595
596 /**
597 * gmc_v7_0_gart_enable - gart enable
598 *
599 * @adev: amdgpu_device pointer
600 *
601 * This sets up the TLBs, programs the page tables for VMID0,
602 * sets up the hw for VMIDs 1-15 which are allocated on
603 * demand, and sets up the global locations for the LDS, GDS,
604 * and GPUVM for FSA64 clients (CIK).
605 * Returns 0 for success, errors for failure.
606 */
607 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
608 {
609 uint64_t table_addr;
610 int r, i;
611 u32 tmp, field;
612
613 if (adev->gart.bo == NULL) {
614 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
615 return -EINVAL;
616 }
617 r = amdgpu_gart_table_vram_pin(adev);
618 if (r)
619 return r;
620
621 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
622
623 /* Setup TLB control */
624 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
625 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
626 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
627 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
628 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
629 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
630 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
631 /* Setup L2 cache */
632 tmp = RREG32(mmVM_L2_CNTL);
633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
640 WREG32(mmVM_L2_CNTL, tmp);
641 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
642 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
643 WREG32(mmVM_L2_CNTL2, tmp);
644
645 field = adev->vm_manager.fragment_size;
646 tmp = RREG32(mmVM_L2_CNTL3);
647 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
648 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
649 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
650 WREG32(mmVM_L2_CNTL3, tmp);
651 /* setup context0 */
652 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
653 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
654 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
655 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
656 (u32)(adev->dummy_page_addr >> 12));
657 WREG32(mmVM_CONTEXT0_CNTL2, 0);
658 tmp = RREG32(mmVM_CONTEXT0_CNTL);
659 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
660 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
661 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
662 WREG32(mmVM_CONTEXT0_CNTL, tmp);
663
664 WREG32(0x575, 0);
665 WREG32(0x576, 0);
666 WREG32(0x577, 0);
667
668 /* empty context1-15 */
669 /* FIXME start with 4G, once using 2 level pt switch to full
670 * vm size space
671 */
672 /* set vm size, must be a multiple of 4 */
673 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
674 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
675 for (i = 1; i < 16; i++) {
676 if (i < 8)
677 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
678 table_addr >> 12);
679 else
680 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
681 table_addr >> 12);
682 }
683
684 /* enable context1-15 */
685 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
686 (u32)(adev->dummy_page_addr >> 12));
687 WREG32(mmVM_CONTEXT1_CNTL2, 4);
688 tmp = RREG32(mmVM_CONTEXT1_CNTL);
689 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
690 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
691 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
692 adev->vm_manager.block_size - 9);
693 WREG32(mmVM_CONTEXT1_CNTL, tmp);
694 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
695 gmc_v7_0_set_fault_enable_default(adev, false);
696 else
697 gmc_v7_0_set_fault_enable_default(adev, true);
698
699 if (adev->asic_type == CHIP_KAVERI) {
700 tmp = RREG32(mmCHUB_CONTROL);
701 tmp &= ~BYPASS_VM;
702 WREG32(mmCHUB_CONTROL, tmp);
703 }
704
705 gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0);
706 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
707 (unsigned)(adev->gmc.gart_size >> 20),
708 (unsigned long long)table_addr);
709 adev->gart.ready = true;
710 return 0;
711 }
712
713 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
714 {
715 int r;
716
717 if (adev->gart.bo) {
718 WARN(1, "R600 PCIE GART already initialized\n");
719 return 0;
720 }
721 /* Initialize common gart structure */
722 r = amdgpu_gart_init(adev);
723 if (r)
724 return r;
725 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
726 adev->gart.gart_pte_flags = 0;
727 return amdgpu_gart_table_vram_alloc(adev);
728 }
729
730 /**
731 * gmc_v7_0_gart_disable - gart disable
732 *
733 * @adev: amdgpu_device pointer
734 *
735 * This disables all VM page table (CIK).
736 */
737 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
738 {
739 u32 tmp;
740
741 /* Disable all tables */
742 WREG32(mmVM_CONTEXT0_CNTL, 0);
743 WREG32(mmVM_CONTEXT1_CNTL, 0);
744 /* Setup TLB control */
745 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
746 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
747 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
748 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
749 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
750 /* Setup L2 cache */
751 tmp = RREG32(mmVM_L2_CNTL);
752 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
753 WREG32(mmVM_L2_CNTL, tmp);
754 WREG32(mmVM_L2_CNTL2, 0);
755 amdgpu_gart_table_vram_unpin(adev);
756 }
757
758 /**
759 * gmc_v7_0_vm_decode_fault - print human readable fault info
760 *
761 * @adev: amdgpu_device pointer
762 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
763 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
764 *
765 * Print human readable fault information (CIK).
766 */
767 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
768 u32 addr, u32 mc_client, unsigned pasid)
769 {
770 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
771 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
772 PROTECTIONS);
773 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
774 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
775 u32 mc_id;
776
777 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
778 MEMORY_CLIENT_ID);
779
780 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
781 protections, vmid, pasid, addr,
782 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
783 MEMORY_CLIENT_RW) ?
784 "write" : "read", block, mc_client, mc_id);
785 }
786
787
788 static const u32 mc_cg_registers[] = {
789 mmMC_HUB_MISC_HUB_CG,
790 mmMC_HUB_MISC_SIP_CG,
791 mmMC_HUB_MISC_VM_CG,
792 mmMC_XPB_CLK_GAT,
793 mmATC_MISC_CG,
794 mmMC_CITF_MISC_WR_CG,
795 mmMC_CITF_MISC_RD_CG,
796 mmMC_CITF_MISC_VM_CG,
797 mmVM_L2_CG,
798 };
799
800 static const u32 mc_cg_ls_en[] = {
801 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
802 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
803 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
804 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
805 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
806 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
807 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
808 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
809 VM_L2_CG__MEM_LS_ENABLE_MASK,
810 };
811
812 static const u32 mc_cg_en[] = {
813 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
814 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
815 MC_HUB_MISC_VM_CG__ENABLE_MASK,
816 MC_XPB_CLK_GAT__ENABLE_MASK,
817 ATC_MISC_CG__ENABLE_MASK,
818 MC_CITF_MISC_WR_CG__ENABLE_MASK,
819 MC_CITF_MISC_RD_CG__ENABLE_MASK,
820 MC_CITF_MISC_VM_CG__ENABLE_MASK,
821 VM_L2_CG__ENABLE_MASK,
822 };
823
824 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
825 bool enable)
826 {
827 int i;
828 u32 orig, data;
829
830 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
831 orig = data = RREG32(mc_cg_registers[i]);
832 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
833 data |= mc_cg_ls_en[i];
834 else
835 data &= ~mc_cg_ls_en[i];
836 if (data != orig)
837 WREG32(mc_cg_registers[i], data);
838 }
839 }
840
841 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
842 bool enable)
843 {
844 int i;
845 u32 orig, data;
846
847 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
848 orig = data = RREG32(mc_cg_registers[i]);
849 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
850 data |= mc_cg_en[i];
851 else
852 data &= ~mc_cg_en[i];
853 if (data != orig)
854 WREG32(mc_cg_registers[i], data);
855 }
856 }
857
858 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
859 bool enable)
860 {
861 u32 orig, data;
862
863 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
864
865 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
866 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
867 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
868 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
869 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
870 } else {
871 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
872 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
873 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
874 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
875 }
876
877 if (orig != data)
878 WREG32_PCIE(ixPCIE_CNTL2, data);
879 }
880
881 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
882 bool enable)
883 {
884 u32 orig, data;
885
886 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
887
888 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
889 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
890 else
891 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
892
893 if (orig != data)
894 WREG32(mmHDP_HOST_PATH_CNTL, data);
895 }
896
897 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
898 bool enable)
899 {
900 u32 orig, data;
901
902 orig = data = RREG32(mmHDP_MEM_POWER_LS);
903
904 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
905 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
906 else
907 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
908
909 if (orig != data)
910 WREG32(mmHDP_MEM_POWER_LS, data);
911 }
912
913 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
914 {
915 switch (mc_seq_vram_type) {
916 case MC_SEQ_MISC0__MT__GDDR1:
917 return AMDGPU_VRAM_TYPE_GDDR1;
918 case MC_SEQ_MISC0__MT__DDR2:
919 return AMDGPU_VRAM_TYPE_DDR2;
920 case MC_SEQ_MISC0__MT__GDDR3:
921 return AMDGPU_VRAM_TYPE_GDDR3;
922 case MC_SEQ_MISC0__MT__GDDR4:
923 return AMDGPU_VRAM_TYPE_GDDR4;
924 case MC_SEQ_MISC0__MT__GDDR5:
925 return AMDGPU_VRAM_TYPE_GDDR5;
926 case MC_SEQ_MISC0__MT__HBM:
927 return AMDGPU_VRAM_TYPE_HBM;
928 case MC_SEQ_MISC0__MT__DDR3:
929 return AMDGPU_VRAM_TYPE_DDR3;
930 default:
931 return AMDGPU_VRAM_TYPE_UNKNOWN;
932 }
933 }
934
935 static int gmc_v7_0_early_init(void *handle)
936 {
937 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
938
939 gmc_v7_0_set_gmc_funcs(adev);
940 gmc_v7_0_set_irq_funcs(adev);
941
942 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
943 adev->gmc.shared_aperture_end =
944 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
945 adev->gmc.private_aperture_start =
946 adev->gmc.shared_aperture_end + 1;
947 adev->gmc.private_aperture_end =
948 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
949
950 return 0;
951 }
952
953 static int gmc_v7_0_late_init(void *handle)
954 {
955 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
956
957 amdgpu_bo_late_init(adev);
958
959 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
960 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
961 else
962 return 0;
963 }
964
965 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
966 {
967 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
968 unsigned size;
969
970 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
971 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
972 } else {
973 u32 viewport = RREG32(mmVIEWPORT_SIZE);
974 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
975 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
976 4);
977 }
978 /* return 0 if the pre-OS buffer uses up most of vram */
979 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
980 return 0;
981 return size;
982 }
983
984 static int gmc_v7_0_sw_init(void *handle)
985 {
986 int r;
987 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
988
989 adev->num_vmhubs = 1;
990
991 if (adev->flags & AMD_IS_APU) {
992 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
993 } else {
994 u32 tmp = RREG32(mmMC_SEQ_MISC0);
995 tmp &= MC_SEQ_MISC0__MT__MASK;
996 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
997 }
998
999 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1000 if (r)
1001 return r;
1002
1003 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1004 if (r)
1005 return r;
1006
1007 /* Adjust VM size here.
1008 * Currently set to 4GB ((1 << 20) 4k pages).
1009 * Max GPUVM size for cayman and SI is 40 bits.
1010 */
1011 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1012
1013 /* Set the internal MC address mask
1014 * This is the max address of the GPU's
1015 * internal address space.
1016 */
1017 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1018
1019 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1020 if (r) {
1021 pr_warn("amdgpu: No suitable DMA available\n");
1022 return r;
1023 }
1024 adev->need_swiotlb = drm_need_swiotlb(40);
1025
1026 r = gmc_v7_0_init_microcode(adev);
1027 if (r) {
1028 DRM_ERROR("Failed to load mc firmware!\n");
1029 return r;
1030 }
1031
1032 r = gmc_v7_0_mc_init(adev);
1033 if (r)
1034 return r;
1035
1036 adev->gmc.stolen_size = gmc_v7_0_get_vbios_fb_size(adev);
1037
1038 /* Memory manager */
1039 r = amdgpu_bo_init(adev);
1040 if (r)
1041 return r;
1042
1043 r = gmc_v7_0_gart_init(adev);
1044 if (r)
1045 return r;
1046
1047 /*
1048 * number of VMs
1049 * VMID 0 is reserved for System
1050 * amdgpu graphics/compute will use VMIDs 1-7
1051 * amdkfd will use VMIDs 8-15
1052 */
1053 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1054 amdgpu_vm_manager_init(adev);
1055
1056 /* base offset of vram pages */
1057 if (adev->flags & AMD_IS_APU) {
1058 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1059
1060 tmp <<= 22;
1061 adev->vm_manager.vram_base_offset = tmp;
1062 } else {
1063 adev->vm_manager.vram_base_offset = 0;
1064 }
1065
1066 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1067 GFP_KERNEL);
1068 if (!adev->gmc.vm_fault_info)
1069 return -ENOMEM;
1070 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1071
1072 return 0;
1073 }
1074
1075 static int gmc_v7_0_sw_fini(void *handle)
1076 {
1077 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1078
1079 amdgpu_gem_force_release(adev);
1080 amdgpu_vm_manager_fini(adev);
1081 kfree(adev->gmc.vm_fault_info);
1082 amdgpu_gart_table_vram_free(adev);
1083 amdgpu_bo_fini(adev);
1084 amdgpu_gart_fini(adev);
1085 release_firmware(adev->gmc.fw);
1086 adev->gmc.fw = NULL;
1087
1088 return 0;
1089 }
1090
1091 static int gmc_v7_0_hw_init(void *handle)
1092 {
1093 int r;
1094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1095
1096 gmc_v7_0_init_golden_registers(adev);
1097
1098 gmc_v7_0_mc_program(adev);
1099
1100 if (!(adev->flags & AMD_IS_APU)) {
1101 r = gmc_v7_0_mc_load_microcode(adev);
1102 if (r) {
1103 DRM_ERROR("Failed to load MC firmware!\n");
1104 return r;
1105 }
1106 }
1107
1108 r = gmc_v7_0_gart_enable(adev);
1109 if (r)
1110 return r;
1111
1112 return r;
1113 }
1114
1115 static int gmc_v7_0_hw_fini(void *handle)
1116 {
1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1118
1119 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1120 gmc_v7_0_gart_disable(adev);
1121
1122 return 0;
1123 }
1124
1125 static int gmc_v7_0_suspend(void *handle)
1126 {
1127 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1128
1129 gmc_v7_0_hw_fini(adev);
1130
1131 return 0;
1132 }
1133
1134 static int gmc_v7_0_resume(void *handle)
1135 {
1136 int r;
1137 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1138
1139 r = gmc_v7_0_hw_init(adev);
1140 if (r)
1141 return r;
1142
1143 amdgpu_vmid_reset_all(adev);
1144
1145 return 0;
1146 }
1147
1148 static bool gmc_v7_0_is_idle(void *handle)
1149 {
1150 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1151 u32 tmp = RREG32(mmSRBM_STATUS);
1152
1153 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1154 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1155 return false;
1156
1157 return true;
1158 }
1159
1160 static int gmc_v7_0_wait_for_idle(void *handle)
1161 {
1162 unsigned i;
1163 u32 tmp;
1164 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1165
1166 for (i = 0; i < adev->usec_timeout; i++) {
1167 /* read MC_STATUS */
1168 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1169 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1170 SRBM_STATUS__MCC_BUSY_MASK |
1171 SRBM_STATUS__MCD_BUSY_MASK |
1172 SRBM_STATUS__VMC_BUSY_MASK);
1173 if (!tmp)
1174 return 0;
1175 udelay(1);
1176 }
1177 return -ETIMEDOUT;
1178
1179 }
1180
1181 static int gmc_v7_0_soft_reset(void *handle)
1182 {
1183 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1184 u32 srbm_soft_reset = 0;
1185 u32 tmp = RREG32(mmSRBM_STATUS);
1186
1187 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1188 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1189 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1190
1191 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1192 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1193 if (!(adev->flags & AMD_IS_APU))
1194 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1195 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1196 }
1197
1198 if (srbm_soft_reset) {
1199 gmc_v7_0_mc_stop(adev);
1200 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1201 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1202 }
1203
1204
1205 tmp = RREG32(mmSRBM_SOFT_RESET);
1206 tmp |= srbm_soft_reset;
1207 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1208 WREG32(mmSRBM_SOFT_RESET, tmp);
1209 tmp = RREG32(mmSRBM_SOFT_RESET);
1210
1211 udelay(50);
1212
1213 tmp &= ~srbm_soft_reset;
1214 WREG32(mmSRBM_SOFT_RESET, tmp);
1215 tmp = RREG32(mmSRBM_SOFT_RESET);
1216
1217 /* Wait a little for things to settle down */
1218 udelay(50);
1219
1220 gmc_v7_0_mc_resume(adev);
1221 udelay(50);
1222 }
1223
1224 return 0;
1225 }
1226
1227 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1228 struct amdgpu_irq_src *src,
1229 unsigned type,
1230 enum amdgpu_interrupt_state state)
1231 {
1232 u32 tmp;
1233 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1234 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1235 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1236 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1237 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1238 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1239
1240 switch (state) {
1241 case AMDGPU_IRQ_STATE_DISABLE:
1242 /* system context */
1243 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1244 tmp &= ~bits;
1245 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1246 /* VMs */
1247 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1248 tmp &= ~bits;
1249 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1250 break;
1251 case AMDGPU_IRQ_STATE_ENABLE:
1252 /* system context */
1253 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1254 tmp |= bits;
1255 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1256 /* VMs */
1257 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1258 tmp |= bits;
1259 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1260 break;
1261 default:
1262 break;
1263 }
1264
1265 return 0;
1266 }
1267
1268 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1269 struct amdgpu_irq_src *source,
1270 struct amdgpu_iv_entry *entry)
1271 {
1272 u32 addr, status, mc_client, vmid;
1273
1274 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1275 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1276 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1277 /* reset addr and status */
1278 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1279
1280 if (!addr && !status)
1281 return 0;
1282
1283 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1284 gmc_v7_0_set_fault_enable_default(adev, false);
1285
1286 if (printk_ratelimit()) {
1287 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1288 entry->src_id, entry->src_data[0]);
1289 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1290 addr);
1291 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1292 status);
1293 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client,
1294 entry->pasid);
1295 }
1296
1297 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1298 VMID);
1299 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1300 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1301 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1302 u32 protections = REG_GET_FIELD(status,
1303 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1304 PROTECTIONS);
1305
1306 info->vmid = vmid;
1307 info->mc_id = REG_GET_FIELD(status,
1308 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1309 MEMORY_CLIENT_ID);
1310 info->status = status;
1311 info->page_addr = addr;
1312 info->prot_valid = protections & 0x7 ? true : false;
1313 info->prot_read = protections & 0x8 ? true : false;
1314 info->prot_write = protections & 0x10 ? true : false;
1315 info->prot_exec = protections & 0x20 ? true : false;
1316 mb();
1317 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1318 }
1319
1320 return 0;
1321 }
1322
1323 static int gmc_v7_0_set_clockgating_state(void *handle,
1324 enum amd_clockgating_state state)
1325 {
1326 bool gate = false;
1327 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1328
1329 if (state == AMD_CG_STATE_GATE)
1330 gate = true;
1331
1332 if (!(adev->flags & AMD_IS_APU)) {
1333 gmc_v7_0_enable_mc_mgcg(adev, gate);
1334 gmc_v7_0_enable_mc_ls(adev, gate);
1335 }
1336 gmc_v7_0_enable_bif_mgls(adev, gate);
1337 gmc_v7_0_enable_hdp_mgcg(adev, gate);
1338 gmc_v7_0_enable_hdp_ls(adev, gate);
1339
1340 return 0;
1341 }
1342
1343 static int gmc_v7_0_set_powergating_state(void *handle,
1344 enum amd_powergating_state state)
1345 {
1346 return 0;
1347 }
1348
1349 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1350 .name = "gmc_v7_0",
1351 .early_init = gmc_v7_0_early_init,
1352 .late_init = gmc_v7_0_late_init,
1353 .sw_init = gmc_v7_0_sw_init,
1354 .sw_fini = gmc_v7_0_sw_fini,
1355 .hw_init = gmc_v7_0_hw_init,
1356 .hw_fini = gmc_v7_0_hw_fini,
1357 .suspend = gmc_v7_0_suspend,
1358 .resume = gmc_v7_0_resume,
1359 .is_idle = gmc_v7_0_is_idle,
1360 .wait_for_idle = gmc_v7_0_wait_for_idle,
1361 .soft_reset = gmc_v7_0_soft_reset,
1362 .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1363 .set_powergating_state = gmc_v7_0_set_powergating_state,
1364 };
1365
1366 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
1367 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
1368 .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
1369 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
1370 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
1371 .set_prt = gmc_v7_0_set_prt,
1372 .get_vm_pde = gmc_v7_0_get_vm_pde,
1373 .get_vm_pte = gmc_v7_0_get_vm_pte
1374 };
1375
1376 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1377 .set = gmc_v7_0_vm_fault_interrupt_state,
1378 .process = gmc_v7_0_process_interrupt,
1379 };
1380
1381 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)
1382 {
1383 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
1384 }
1385
1386 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1387 {
1388 adev->gmc.vm_fault.num_types = 1;
1389 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1390 }
1391
1392 const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1393 {
1394 .type = AMD_IP_BLOCK_TYPE_GMC,
1395 .major = 7,
1396 .minor = 0,
1397 .rev = 0,
1398 .funcs = &gmc_v7_0_ip_funcs,
1399 };
1400
1401 const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1402 {
1403 .type = AMD_IP_BLOCK_TYPE_GMC,
1404 .major = 7,
1405 .minor = 4,
1406 .rev = 0,
1407 .funcs = &gmc_v7_0_ip_funcs,
1408 };
Linux with added FPC-III support