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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / amdgpu / gmc_v8_0.c
blob27d83204fa2b00c3a8e663ceb18402ce39ba24e0
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include <drm/drm_cache.h>
29 #include "amdgpu.h"
30 #include "gmc_v8_0.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_amdkfd.h"
33 #include "amdgpu_gem.h"
34
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
37
38 #include "bif/bif_5_0_d.h"
39 #include "bif/bif_5_0_sh_mask.h"
40
41 #include "oss/oss_3_0_d.h"
42 #include "oss/oss_3_0_sh_mask.h"
43
44 #include "dce/dce_10_0_d.h"
45 #include "dce/dce_10_0_sh_mask.h"
46
47 #include "vid.h"
48 #include "vi.h"
49
50 #include "amdgpu_atombios.h"
51
52 #include "ivsrcid/ivsrcid_vislands30.h"
53
54 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
55 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
56 static int gmc_v8_0_wait_for_idle(void *handle);
57
58 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
59 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
60 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
61 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
62 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin");
63 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin");
64 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin");
65
66 static const u32 golden_settings_tonga_a11[] =
67 {
68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
75 };
76
77 static const u32 tonga_mgcg_cgcg_init[] =
78 {
79 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
80 };
81
82 static const u32 golden_settings_fiji_a10[] =
83 {
84 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
85 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
86 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
87 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
88 };
89
90 static const u32 fiji_mgcg_cgcg_init[] =
91 {
92 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
93 };
94
95 static const u32 golden_settings_polaris11_a11[] =
96 {
97 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
98 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
99 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
100 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
101 };
102
103 static const u32 golden_settings_polaris10_a11[] =
104 {
105 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
106 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
107 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
108 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
109 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
110 };
111
112 static const u32 cz_mgcg_cgcg_init[] =
113 {
114 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
115 };
116
117 static const u32 stoney_mgcg_cgcg_init[] =
118 {
119 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
120 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
121 };
122
123 static const u32 golden_settings_stoney_common[] =
124 {
125 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
126 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
127 };
128
129 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
130 {
131 switch (adev->asic_type) {
132 case CHIP_FIJI:
133 amdgpu_device_program_register_sequence(adev,
134 fiji_mgcg_cgcg_init,
135 ARRAY_SIZE(fiji_mgcg_cgcg_init));
136 amdgpu_device_program_register_sequence(adev,
137 golden_settings_fiji_a10,
138 ARRAY_SIZE(golden_settings_fiji_a10));
139 break;
140 case CHIP_TONGA:
141 amdgpu_device_program_register_sequence(adev,
142 tonga_mgcg_cgcg_init,
143 ARRAY_SIZE(tonga_mgcg_cgcg_init));
144 amdgpu_device_program_register_sequence(adev,
145 golden_settings_tonga_a11,
146 ARRAY_SIZE(golden_settings_tonga_a11));
147 break;
148 case CHIP_POLARIS11:
149 case CHIP_POLARIS12:
150 case CHIP_VEGAM:
151 amdgpu_device_program_register_sequence(adev,
152 golden_settings_polaris11_a11,
153 ARRAY_SIZE(golden_settings_polaris11_a11));
154 break;
155 case CHIP_POLARIS10:
156 amdgpu_device_program_register_sequence(adev,
157 golden_settings_polaris10_a11,
158 ARRAY_SIZE(golden_settings_polaris10_a11));
159 break;
160 case CHIP_CARRIZO:
161 amdgpu_device_program_register_sequence(adev,
162 cz_mgcg_cgcg_init,
163 ARRAY_SIZE(cz_mgcg_cgcg_init));
164 break;
165 case CHIP_STONEY:
166 amdgpu_device_program_register_sequence(adev,
167 stoney_mgcg_cgcg_init,
168 ARRAY_SIZE(stoney_mgcg_cgcg_init));
169 amdgpu_device_program_register_sequence(adev,
170 golden_settings_stoney_common,
171 ARRAY_SIZE(golden_settings_stoney_common));
172 break;
173 default:
174 break;
175 }
176 }
177
178 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
179 {
180 u32 blackout;
181
182 gmc_v8_0_wait_for_idle(adev);
183
184 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
185 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
186 /* Block CPU access */
187 WREG32(mmBIF_FB_EN, 0);
188 /* blackout the MC */
189 blackout = REG_SET_FIELD(blackout,
190 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
191 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
192 }
193 /* wait for the MC to settle */
194 udelay(100);
195 }
196
197 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
198 {
199 u32 tmp;
200
201 /* unblackout the MC */
202 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
203 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
204 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
205 /* allow CPU access */
206 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
207 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
208 WREG32(mmBIF_FB_EN, tmp);
209 }
210
211 /**
212 * gmc_v8_0_init_microcode - load ucode images from disk
213 *
214 * @adev: amdgpu_device pointer
215 *
216 * Use the firmware interface to load the ucode images into
217 * the driver (not loaded into hw).
218 * Returns 0 on success, error on failure.
219 */
220 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
221 {
222 const char *chip_name;
223 char fw_name[30];
224 int err;
225
226 DRM_DEBUG("\n");
227
228 switch (adev->asic_type) {
229 case CHIP_TONGA:
230 chip_name = "tonga";
231 break;
232 case CHIP_POLARIS11:
233 if (((adev->pdev->device == 0x67ef) &&
234 ((adev->pdev->revision == 0xe0) ||
235 (adev->pdev->revision == 0xe5))) ||
236 ((adev->pdev->device == 0x67ff) &&
237 ((adev->pdev->revision == 0xcf) ||
238 (adev->pdev->revision == 0xef) ||
239 (adev->pdev->revision == 0xff))))
240 chip_name = "polaris11_k";
241 else if ((adev->pdev->device == 0x67ef) &&
242 (adev->pdev->revision == 0xe2))
243 chip_name = "polaris11_k";
244 else
245 chip_name = "polaris11";
246 break;
247 case CHIP_POLARIS10:
248 if ((adev->pdev->device == 0x67df) &&
249 ((adev->pdev->revision == 0xe1) ||
250 (adev->pdev->revision == 0xf7)))
251 chip_name = "polaris10_k";
252 else
253 chip_name = "polaris10";
254 break;
255 case CHIP_POLARIS12:
256 if (((adev->pdev->device == 0x6987) &&
257 ((adev->pdev->revision == 0xc0) ||
258 (adev->pdev->revision == 0xc3))) ||
259 ((adev->pdev->device == 0x6981) &&
260 ((adev->pdev->revision == 0x00) ||
261 (adev->pdev->revision == 0x01) ||
262 (adev->pdev->revision == 0x10))))
263 chip_name = "polaris12_k";
264 else
265 chip_name = "polaris12";
266 break;
267 case CHIP_FIJI:
268 case CHIP_CARRIZO:
269 case CHIP_STONEY:
270 case CHIP_VEGAM:
271 return 0;
272 default: BUG();
273 }
274
275 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
276 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
277 if (err)
278 goto out;
279 err = amdgpu_ucode_validate(adev->gmc.fw);
280
281 out:
282 if (err) {
283 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
284 release_firmware(adev->gmc.fw);
285 adev->gmc.fw = NULL;
286 }
287 return err;
288 }
289
290 /**
291 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
292 *
293 * @adev: amdgpu_device pointer
294 *
295 * Load the GDDR MC ucode into the hw (VI).
296 * Returns 0 on success, error on failure.
297 */
298 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
299 {
300 const struct mc_firmware_header_v1_0 *hdr;
301 const __le32 *fw_data = NULL;
302 const __le32 *io_mc_regs = NULL;
303 u32 running;
304 int i, ucode_size, regs_size;
305
306 /* Skip MC ucode loading on SR-IOV capable boards.
307 * vbios does this for us in asic_init in that case.
308 * Skip MC ucode loading on VF, because hypervisor will do that
309 * for this adaptor.
310 */
311 if (amdgpu_sriov_bios(adev))
312 return 0;
313
314 if (!adev->gmc.fw)
315 return -EINVAL;
316
317 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
318 amdgpu_ucode_print_mc_hdr(&hdr->header);
319
320 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
321 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
322 io_mc_regs = (const __le32 *)
323 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
324 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
325 fw_data = (const __le32 *)
326 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
327
328 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
329
330 if (running == 0) {
331 /* reset the engine and set to writable */
332 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
333 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
334
335 /* load mc io regs */
336 for (i = 0; i < regs_size; i++) {
337 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
338 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
339 }
340 /* load the MC ucode */
341 for (i = 0; i < ucode_size; i++)
342 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
343
344 /* put the engine back into the active state */
345 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
346 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
347 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
348
349 /* wait for training to complete */
350 for (i = 0; i < adev->usec_timeout; i++) {
351 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
352 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
353 break;
354 udelay(1);
355 }
356 for (i = 0; i < adev->usec_timeout; i++) {
357 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
358 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
359 break;
360 udelay(1);
361 }
362 }
363
364 return 0;
365 }
366
367 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
368 {
369 const struct mc_firmware_header_v1_0 *hdr;
370 const __le32 *fw_data = NULL;
371 const __le32 *io_mc_regs = NULL;
372 u32 data;
373 int i, ucode_size, regs_size;
374
375 /* Skip MC ucode loading on SR-IOV capable boards.
376 * vbios does this for us in asic_init in that case.
377 * Skip MC ucode loading on VF, because hypervisor will do that
378 * for this adaptor.
379 */
380 if (amdgpu_sriov_bios(adev))
381 return 0;
382
383 if (!adev->gmc.fw)
384 return -EINVAL;
385
386 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
387 amdgpu_ucode_print_mc_hdr(&hdr->header);
388
389 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
390 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
391 io_mc_regs = (const __le32 *)
392 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
393 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
394 fw_data = (const __le32 *)
395 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
396
397 data = RREG32(mmMC_SEQ_MISC0);
398 data &= ~(0x40);
399 WREG32(mmMC_SEQ_MISC0, data);
400
401 /* load mc io regs */
402 for (i = 0; i < regs_size; i++) {
403 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
404 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
405 }
406
407 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
408 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
409
410 /* load the MC ucode */
411 for (i = 0; i < ucode_size; i++)
412 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
413
414 /* put the engine back into the active state */
415 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
416 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
417 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
418
419 /* wait for training to complete */
420 for (i = 0; i < adev->usec_timeout; i++) {
421 data = RREG32(mmMC_SEQ_MISC0);
422 if (data & 0x80)
423 break;
424 udelay(1);
425 }
426
427 return 0;
428 }
429
430 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
431 struct amdgpu_gmc *mc)
432 {
433 u64 base = 0;
434
435 if (!amdgpu_sriov_vf(adev))
436 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
437 base <<= 24;
438
439 amdgpu_gmc_vram_location(adev, mc, base);
440 amdgpu_gmc_gart_location(adev, mc);
441 }
442
443 /**
444 * gmc_v8_0_mc_program - program the GPU memory controller
445 *
446 * @adev: amdgpu_device pointer
447 *
448 * Set the location of vram, gart, and AGP in the GPU's
449 * physical address space (VI).
450 */
451 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
452 {
453 u32 tmp;
454 int i, j;
455
456 /* Initialize HDP */
457 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
458 WREG32((0xb05 + j), 0x00000000);
459 WREG32((0xb06 + j), 0x00000000);
460 WREG32((0xb07 + j), 0x00000000);
461 WREG32((0xb08 + j), 0x00000000);
462 WREG32((0xb09 + j), 0x00000000);
463 }
464 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
465
466 if (gmc_v8_0_wait_for_idle((void *)adev)) {
467 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
468 }
469 if (adev->mode_info.num_crtc) {
470 /* Lockout access through VGA aperture*/
471 tmp = RREG32(mmVGA_HDP_CONTROL);
472 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
473 WREG32(mmVGA_HDP_CONTROL, tmp);
474
475 /* disable VGA render */
476 tmp = RREG32(mmVGA_RENDER_CONTROL);
477 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
478 WREG32(mmVGA_RENDER_CONTROL, tmp);
479 }
480 /* Update configuration */
481 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
482 adev->gmc.vram_start >> 12);
483 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
484 adev->gmc.vram_end >> 12);
485 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
486 adev->vram_scratch.gpu_addr >> 12);
487
488 if (amdgpu_sriov_vf(adev)) {
489 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
490 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
491 WREG32(mmMC_VM_FB_LOCATION, tmp);
492 /* XXX double check these! */
493 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
494 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
495 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
496 }
497
498 WREG32(mmMC_VM_AGP_BASE, 0);
499 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
500 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
501 if (gmc_v8_0_wait_for_idle((void *)adev)) {
502 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
503 }
504
505 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
506
507 tmp = RREG32(mmHDP_MISC_CNTL);
508 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
509 WREG32(mmHDP_MISC_CNTL, tmp);
510
511 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
512 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
513 }
514
515 /**
516 * gmc_v8_0_mc_init - initialize the memory controller driver params
517 *
518 * @adev: amdgpu_device pointer
519 *
520 * Look up the amount of vram, vram width, and decide how to place
521 * vram and gart within the GPU's physical address space (VI).
522 * Returns 0 for success.
523 */
524 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
525 {
526 int r;
527
528 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
529 if (!adev->gmc.vram_width) {
530 u32 tmp;
531 int chansize, numchan;
532
533 /* Get VRAM informations */
534 tmp = RREG32(mmMC_ARB_RAMCFG);
535 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
536 chansize = 64;
537 } else {
538 chansize = 32;
539 }
540 tmp = RREG32(mmMC_SHARED_CHMAP);
541 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
542 case 0:
543 default:
544 numchan = 1;
545 break;
546 case 1:
547 numchan = 2;
548 break;
549 case 2:
550 numchan = 4;
551 break;
552 case 3:
553 numchan = 8;
554 break;
555 case 4:
556 numchan = 3;
557 break;
558 case 5:
559 numchan = 6;
560 break;
561 case 6:
562 numchan = 10;
563 break;
564 case 7:
565 numchan = 12;
566 break;
567 case 8:
568 numchan = 16;
569 break;
570 }
571 adev->gmc.vram_width = numchan * chansize;
572 }
573 /* size in MB on si */
574 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
575 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
576
577 if (!(adev->flags & AMD_IS_APU)) {
578 r = amdgpu_device_resize_fb_bar(adev);
579 if (r)
580 return r;
581 }
582 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
583 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
584
585 #ifdef CONFIG_X86_64
586 if (adev->flags & AMD_IS_APU) {
587 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
588 adev->gmc.aper_size = adev->gmc.real_vram_size;
589 }
590 #endif
591
592 /* In case the PCI BAR is larger than the actual amount of vram */
593 adev->gmc.visible_vram_size = adev->gmc.aper_size;
594 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
595 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
596
597 /* set the gart size */
598 if (amdgpu_gart_size == -1) {
599 switch (adev->asic_type) {
600 case CHIP_POLARIS10: /* all engines support GPUVM */
601 case CHIP_POLARIS11: /* all engines support GPUVM */
602 case CHIP_POLARIS12: /* all engines support GPUVM */
603 case CHIP_VEGAM: /* all engines support GPUVM */
604 default:
605 adev->gmc.gart_size = 256ULL << 20;
606 break;
607 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */
608 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */
609 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
610 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */
611 adev->gmc.gart_size = 1024ULL << 20;
612 break;
613 }
614 } else {
615 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
616 }
617
618 gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
619
620 return 0;
621 }
622
623 /**
624 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
625 *
626 * @adev: amdgpu_device pointer
627 * @pasid: pasid to be flush
628 *
629 * Flush the TLB for the requested pasid.
630 */
631 static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
632 uint16_t pasid, uint32_t flush_type,
633 bool all_hub)
634 {
635 int vmid;
636 unsigned int tmp;
637
638 if (adev->in_gpu_reset)
639 return -EIO;
640
641 for (vmid = 1; vmid < 16; vmid++) {
642
643 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
644 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
645 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
646 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
647 RREG32(mmVM_INVALIDATE_RESPONSE);
648 break;
649 }
650 }
651
652 return 0;
653
654 }
655
656 /*
657 * GART
658 * VMID 0 is the physical GPU addresses as used by the kernel.
659 * VMIDs 1-15 are used for userspace clients and are handled
660 * by the amdgpu vm/hsa code.
661 */
662
663 /**
664 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
665 *
666 * @adev: amdgpu_device pointer
667 * @vmid: vm instance to flush
668 *
669 * Flush the TLB for the requested page table (VI).
670 */
671 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
672 uint32_t vmhub, uint32_t flush_type)
673 {
674 /* bits 0-15 are the VM contexts0-15 */
675 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
676 }
677
678 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
679 unsigned vmid, uint64_t pd_addr)
680 {
681 uint32_t reg;
682
683 if (vmid < 8)
684 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
685 else
686 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
687 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
688
689 /* bits 0-15 are the VM contexts0-15 */
690 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
691
692 return pd_addr;
693 }
694
695 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
696 unsigned pasid)
697 {
698 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
699 }
700
701 /*
702 * PTE format on VI:
703 * 63:40 reserved
704 * 39:12 4k physical page base address
705 * 11:7 fragment
706 * 6 write
707 * 5 read
708 * 4 exe
709 * 3 reserved
710 * 2 snooped
711 * 1 system
712 * 0 valid
713 *
714 * PDE format on VI:
715 * 63:59 block fragment size
716 * 58:40 reserved
717 * 39:1 physical base address of PTE
718 * bits 5:1 must be 0.
719 * 0 valid
720 */
721
722 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
723 uint64_t *addr, uint64_t *flags)
724 {
725 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
726 }
727
728 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev,
729 struct amdgpu_bo_va_mapping *mapping,
730 uint64_t *flags)
731 {
732 *flags &= ~AMDGPU_PTE_EXECUTABLE;
733 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
734 *flags &= ~AMDGPU_PTE_PRT;
735 }
736
737 /**
738 * gmc_v8_0_set_fault_enable_default - update VM fault handling
739 *
740 * @adev: amdgpu_device pointer
741 * @value: true redirects VM faults to the default page
742 */
743 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
744 bool value)
745 {
746 u32 tmp;
747
748 tmp = RREG32(mmVM_CONTEXT1_CNTL);
749 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
750 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
751 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
752 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
753 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
754 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
755 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
756 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
757 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
758 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
759 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
760 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
761 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
762 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
763 WREG32(mmVM_CONTEXT1_CNTL, tmp);
764 }
765
766 /**
767 * gmc_v8_0_set_prt - set PRT VM fault
768 *
769 * @adev: amdgpu_device pointer
770 * @enable: enable/disable VM fault handling for PRT
771 */
772 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
773 {
774 u32 tmp;
775
776 if (enable && !adev->gmc.prt_warning) {
777 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
778 adev->gmc.prt_warning = true;
779 }
780
781 tmp = RREG32(mmVM_PRT_CNTL);
782 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
783 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
784 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
785 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
786 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
787 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
788 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
789 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
790 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
791 L2_CACHE_STORE_INVALID_ENTRIES, enable);
792 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
793 L1_TLB_STORE_INVALID_ENTRIES, enable);
794 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
795 MASK_PDE0_FAULT, enable);
796 WREG32(mmVM_PRT_CNTL, tmp);
797
798 if (enable) {
799 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
800 uint32_t high = adev->vm_manager.max_pfn -
801 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
802
803 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
804 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
805 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
806 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
807 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
808 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
809 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
810 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
811 } else {
812 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
813 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
814 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
815 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
816 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
817 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
818 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
819 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
820 }
821 }
822
823 /**
824 * gmc_v8_0_gart_enable - gart enable
825 *
826 * @adev: amdgpu_device pointer
827 *
828 * This sets up the TLBs, programs the page tables for VMID0,
829 * sets up the hw for VMIDs 1-15 which are allocated on
830 * demand, and sets up the global locations for the LDS, GDS,
831 * and GPUVM for FSA64 clients (VI).
832 * Returns 0 for success, errors for failure.
833 */
834 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
835 {
836 uint64_t table_addr;
837 int r, i;
838 u32 tmp, field;
839
840 if (adev->gart.bo == NULL) {
841 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
842 return -EINVAL;
843 }
844 r = amdgpu_gart_table_vram_pin(adev);
845 if (r)
846 return r;
847
848 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
849
850 /* Setup TLB control */
851 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
852 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
853 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
854 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
855 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
856 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
857 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
858 /* Setup L2 cache */
859 tmp = RREG32(mmVM_L2_CNTL);
860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
863 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
864 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
865 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
867 WREG32(mmVM_L2_CNTL, tmp);
868 tmp = RREG32(mmVM_L2_CNTL2);
869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
871 WREG32(mmVM_L2_CNTL2, tmp);
872
873 field = adev->vm_manager.fragment_size;
874 tmp = RREG32(mmVM_L2_CNTL3);
875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
876 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
877 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
878 WREG32(mmVM_L2_CNTL3, tmp);
879 /* XXX: set to enable PTE/PDE in system memory */
880 tmp = RREG32(mmVM_L2_CNTL4);
881 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
882 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
883 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
884 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
885 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
886 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
887 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
888 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
889 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
890 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
891 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
892 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
893 WREG32(mmVM_L2_CNTL4, tmp);
894 /* setup context0 */
895 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
896 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
897 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
898 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
899 (u32)(adev->dummy_page_addr >> 12));
900 WREG32(mmVM_CONTEXT0_CNTL2, 0);
901 tmp = RREG32(mmVM_CONTEXT0_CNTL);
902 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
903 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
904 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
905 WREG32(mmVM_CONTEXT0_CNTL, tmp);
906
907 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
908 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
909 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
910
911 /* empty context1-15 */
912 /* FIXME start with 4G, once using 2 level pt switch to full
913 * vm size space
914 */
915 /* set vm size, must be a multiple of 4 */
916 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
917 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
918 for (i = 1; i < 16; i++) {
919 if (i < 8)
920 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
921 table_addr >> 12);
922 else
923 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
924 table_addr >> 12);
925 }
926
927 /* enable context1-15 */
928 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
929 (u32)(adev->dummy_page_addr >> 12));
930 WREG32(mmVM_CONTEXT1_CNTL2, 4);
931 tmp = RREG32(mmVM_CONTEXT1_CNTL);
932 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
933 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
934 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
935 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
936 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
937 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
938 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
939 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
940 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
941 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
942 adev->vm_manager.block_size - 9);
943 WREG32(mmVM_CONTEXT1_CNTL, tmp);
944 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
945 gmc_v8_0_set_fault_enable_default(adev, false);
946 else
947 gmc_v8_0_set_fault_enable_default(adev, true);
948
949 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0);
950 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
951 (unsigned)(adev->gmc.gart_size >> 20),
952 (unsigned long long)table_addr);
953 adev->gart.ready = true;
954 return 0;
955 }
956
957 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
958 {
959 int r;
960
961 if (adev->gart.bo) {
962 WARN(1, "R600 PCIE GART already initialized\n");
963 return 0;
964 }
965 /* Initialize common gart structure */
966 r = amdgpu_gart_init(adev);
967 if (r)
968 return r;
969 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
970 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
971 return amdgpu_gart_table_vram_alloc(adev);
972 }
973
974 /**
975 * gmc_v8_0_gart_disable - gart disable
976 *
977 * @adev: amdgpu_device pointer
978 *
979 * This disables all VM page table (VI).
980 */
981 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
982 {
983 u32 tmp;
984
985 /* Disable all tables */
986 WREG32(mmVM_CONTEXT0_CNTL, 0);
987 WREG32(mmVM_CONTEXT1_CNTL, 0);
988 /* Setup TLB control */
989 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
990 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
991 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
992 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
993 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
994 /* Setup L2 cache */
995 tmp = RREG32(mmVM_L2_CNTL);
996 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
997 WREG32(mmVM_L2_CNTL, tmp);
998 WREG32(mmVM_L2_CNTL2, 0);
999 amdgpu_gart_table_vram_unpin(adev);
1000 }
1001
1002 /**
1003 * gmc_v8_0_vm_decode_fault - print human readable fault info
1004 *
1005 * @adev: amdgpu_device pointer
1006 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
1007 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
1008 *
1009 * Print human readable fault information (VI).
1010 */
1011 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
1012 u32 addr, u32 mc_client, unsigned pasid)
1013 {
1014 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
1015 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1016 PROTECTIONS);
1017 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
1018 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
1019 u32 mc_id;
1020
1021 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1022 MEMORY_CLIENT_ID);
1023
1024 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1025 protections, vmid, pasid, addr,
1026 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1027 MEMORY_CLIENT_RW) ?
1028 "write" : "read", block, mc_client, mc_id);
1029 }
1030
1031 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1032 {
1033 switch (mc_seq_vram_type) {
1034 case MC_SEQ_MISC0__MT__GDDR1:
1035 return AMDGPU_VRAM_TYPE_GDDR1;
1036 case MC_SEQ_MISC0__MT__DDR2:
1037 return AMDGPU_VRAM_TYPE_DDR2;
1038 case MC_SEQ_MISC0__MT__GDDR3:
1039 return AMDGPU_VRAM_TYPE_GDDR3;
1040 case MC_SEQ_MISC0__MT__GDDR4:
1041 return AMDGPU_VRAM_TYPE_GDDR4;
1042 case MC_SEQ_MISC0__MT__GDDR5:
1043 return AMDGPU_VRAM_TYPE_GDDR5;
1044 case MC_SEQ_MISC0__MT__HBM:
1045 return AMDGPU_VRAM_TYPE_HBM;
1046 case MC_SEQ_MISC0__MT__DDR3:
1047 return AMDGPU_VRAM_TYPE_DDR3;
1048 default:
1049 return AMDGPU_VRAM_TYPE_UNKNOWN;
1050 }
1051 }
1052
1053 static int gmc_v8_0_early_init(void *handle)
1054 {
1055 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1056
1057 gmc_v8_0_set_gmc_funcs(adev);
1058 gmc_v8_0_set_irq_funcs(adev);
1059
1060 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1061 adev->gmc.shared_aperture_end =
1062 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1063 adev->gmc.private_aperture_start =
1064 adev->gmc.shared_aperture_end + 1;
1065 adev->gmc.private_aperture_end =
1066 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1067
1068 return 0;
1069 }
1070
1071 static int gmc_v8_0_late_init(void *handle)
1072 {
1073 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1074
1075 amdgpu_bo_late_init(adev);
1076
1077 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1078 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1079 else
1080 return 0;
1081 }
1082
1083 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1084 {
1085 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1086 unsigned size;
1087
1088 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1089 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
1090 } else {
1091 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1092 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1093 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1094 4);
1095 }
1096 /* return 0 if the pre-OS buffer uses up most of vram */
1097 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1098 return 0;
1099 return size;
1100 }
1101
1102 #define mmMC_SEQ_MISC0_FIJI 0xA71
1103
1104 static int gmc_v8_0_sw_init(void *handle)
1105 {
1106 int r;
1107 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1108
1109 adev->num_vmhubs = 1;
1110
1111 if (adev->flags & AMD_IS_APU) {
1112 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1113 } else {
1114 u32 tmp;
1115
1116 if ((adev->asic_type == CHIP_FIJI) ||
1117 (adev->asic_type == CHIP_VEGAM))
1118 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1119 else
1120 tmp = RREG32(mmMC_SEQ_MISC0);
1121 tmp &= MC_SEQ_MISC0__MT__MASK;
1122 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1123 }
1124
1125 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1126 if (r)
1127 return r;
1128
1129 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1130 if (r)
1131 return r;
1132
1133 /* Adjust VM size here.
1134 * Currently set to 4GB ((1 << 20) 4k pages).
1135 * Max GPUVM size for cayman and SI is 40 bits.
1136 */
1137 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1138
1139 /* Set the internal MC address mask
1140 * This is the max address of the GPU's
1141 * internal address space.
1142 */
1143 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1144
1145 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1146 if (r) {
1147 pr_warn("amdgpu: No suitable DMA available\n");
1148 return r;
1149 }
1150 adev->need_swiotlb = drm_need_swiotlb(40);
1151
1152 r = gmc_v8_0_init_microcode(adev);
1153 if (r) {
1154 DRM_ERROR("Failed to load mc firmware!\n");
1155 return r;
1156 }
1157
1158 r = gmc_v8_0_mc_init(adev);
1159 if (r)
1160 return r;
1161
1162 adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev);
1163
1164 /* Memory manager */
1165 r = amdgpu_bo_init(adev);
1166 if (r)
1167 return r;
1168
1169 r = gmc_v8_0_gart_init(adev);
1170 if (r)
1171 return r;
1172
1173 /*
1174 * number of VMs
1175 * VMID 0 is reserved for System
1176 * amdgpu graphics/compute will use VMIDs 1-7
1177 * amdkfd will use VMIDs 8-15
1178 */
1179 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1180 amdgpu_vm_manager_init(adev);
1181
1182 /* base offset of vram pages */
1183 if (adev->flags & AMD_IS_APU) {
1184 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1185
1186 tmp <<= 22;
1187 adev->vm_manager.vram_base_offset = tmp;
1188 } else {
1189 adev->vm_manager.vram_base_offset = 0;
1190 }
1191
1192 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1193 GFP_KERNEL);
1194 if (!adev->gmc.vm_fault_info)
1195 return -ENOMEM;
1196 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1197
1198 return 0;
1199 }
1200
1201 static int gmc_v8_0_sw_fini(void *handle)
1202 {
1203 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1204
1205 amdgpu_gem_force_release(adev);
1206 amdgpu_vm_manager_fini(adev);
1207 kfree(adev->gmc.vm_fault_info);
1208 amdgpu_gart_table_vram_free(adev);
1209 amdgpu_bo_fini(adev);
1210 amdgpu_gart_fini(adev);
1211 release_firmware(adev->gmc.fw);
1212 adev->gmc.fw = NULL;
1213
1214 return 0;
1215 }
1216
1217 static int gmc_v8_0_hw_init(void *handle)
1218 {
1219 int r;
1220 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1221
1222 gmc_v8_0_init_golden_registers(adev);
1223
1224 gmc_v8_0_mc_program(adev);
1225
1226 if (adev->asic_type == CHIP_TONGA) {
1227 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1228 if (r) {
1229 DRM_ERROR("Failed to load MC firmware!\n");
1230 return r;
1231 }
1232 } else if (adev->asic_type == CHIP_POLARIS11 ||
1233 adev->asic_type == CHIP_POLARIS10 ||
1234 adev->asic_type == CHIP_POLARIS12) {
1235 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1236 if (r) {
1237 DRM_ERROR("Failed to load MC firmware!\n");
1238 return r;
1239 }
1240 }
1241
1242 r = gmc_v8_0_gart_enable(adev);
1243 if (r)
1244 return r;
1245
1246 return r;
1247 }
1248
1249 static int gmc_v8_0_hw_fini(void *handle)
1250 {
1251 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1252
1253 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1254 gmc_v8_0_gart_disable(adev);
1255
1256 return 0;
1257 }
1258
1259 static int gmc_v8_0_suspend(void *handle)
1260 {
1261 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1262
1263 gmc_v8_0_hw_fini(adev);
1264
1265 return 0;
1266 }
1267
1268 static int gmc_v8_0_resume(void *handle)
1269 {
1270 int r;
1271 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1272
1273 r = gmc_v8_0_hw_init(adev);
1274 if (r)
1275 return r;
1276
1277 amdgpu_vmid_reset_all(adev);
1278
1279 return 0;
1280 }
1281
1282 static bool gmc_v8_0_is_idle(void *handle)
1283 {
1284 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285 u32 tmp = RREG32(mmSRBM_STATUS);
1286
1287 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1288 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1289 return false;
1290
1291 return true;
1292 }
1293
1294 static int gmc_v8_0_wait_for_idle(void *handle)
1295 {
1296 unsigned i;
1297 u32 tmp;
1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299
1300 for (i = 0; i < adev->usec_timeout; i++) {
1301 /* read MC_STATUS */
1302 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1303 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1304 SRBM_STATUS__MCC_BUSY_MASK |
1305 SRBM_STATUS__MCD_BUSY_MASK |
1306 SRBM_STATUS__VMC_BUSY_MASK |
1307 SRBM_STATUS__VMC1_BUSY_MASK);
1308 if (!tmp)
1309 return 0;
1310 udelay(1);
1311 }
1312 return -ETIMEDOUT;
1313
1314 }
1315
1316 static bool gmc_v8_0_check_soft_reset(void *handle)
1317 {
1318 u32 srbm_soft_reset = 0;
1319 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1320 u32 tmp = RREG32(mmSRBM_STATUS);
1321
1322 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1323 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1324 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1325
1326 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1327 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1328 if (!(adev->flags & AMD_IS_APU))
1329 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1330 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1331 }
1332 if (srbm_soft_reset) {
1333 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1334 return true;
1335 } else {
1336 adev->gmc.srbm_soft_reset = 0;
1337 return false;
1338 }
1339 }
1340
1341 static int gmc_v8_0_pre_soft_reset(void *handle)
1342 {
1343 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1344
1345 if (!adev->gmc.srbm_soft_reset)
1346 return 0;
1347
1348 gmc_v8_0_mc_stop(adev);
1349 if (gmc_v8_0_wait_for_idle(adev)) {
1350 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1351 }
1352
1353 return 0;
1354 }
1355
1356 static int gmc_v8_0_soft_reset(void *handle)
1357 {
1358 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1359 u32 srbm_soft_reset;
1360
1361 if (!adev->gmc.srbm_soft_reset)
1362 return 0;
1363 srbm_soft_reset = adev->gmc.srbm_soft_reset;
1364
1365 if (srbm_soft_reset) {
1366 u32 tmp;
1367
1368 tmp = RREG32(mmSRBM_SOFT_RESET);
1369 tmp |= srbm_soft_reset;
1370 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1371 WREG32(mmSRBM_SOFT_RESET, tmp);
1372 tmp = RREG32(mmSRBM_SOFT_RESET);
1373
1374 udelay(50);
1375
1376 tmp &= ~srbm_soft_reset;
1377 WREG32(mmSRBM_SOFT_RESET, tmp);
1378 tmp = RREG32(mmSRBM_SOFT_RESET);
1379
1380 /* Wait a little for things to settle down */
1381 udelay(50);
1382 }
1383
1384 return 0;
1385 }
1386
1387 static int gmc_v8_0_post_soft_reset(void *handle)
1388 {
1389 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1390
1391 if (!adev->gmc.srbm_soft_reset)
1392 return 0;
1393
1394 gmc_v8_0_mc_resume(adev);
1395 return 0;
1396 }
1397
1398 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1399 struct amdgpu_irq_src *src,
1400 unsigned type,
1401 enum amdgpu_interrupt_state state)
1402 {
1403 u32 tmp;
1404 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1405 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1406 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1407 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1408 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1409 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1410 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1411
1412 switch (state) {
1413 case AMDGPU_IRQ_STATE_DISABLE:
1414 /* system context */
1415 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1416 tmp &= ~bits;
1417 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1418 /* VMs */
1419 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1420 tmp &= ~bits;
1421 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1422 break;
1423 case AMDGPU_IRQ_STATE_ENABLE:
1424 /* system context */
1425 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1426 tmp |= bits;
1427 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1428 /* VMs */
1429 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1430 tmp |= bits;
1431 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1432 break;
1433 default:
1434 break;
1435 }
1436
1437 return 0;
1438 }
1439
1440 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1441 struct amdgpu_irq_src *source,
1442 struct amdgpu_iv_entry *entry)
1443 {
1444 u32 addr, status, mc_client, vmid;
1445
1446 if (amdgpu_sriov_vf(adev)) {
1447 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1448 entry->src_id, entry->src_data[0]);
1449 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1450 return 0;
1451 }
1452
1453 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1454 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1455 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1456 /* reset addr and status */
1457 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1458
1459 if (!addr && !status)
1460 return 0;
1461
1462 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1463 gmc_v8_0_set_fault_enable_default(adev, false);
1464
1465 if (printk_ratelimit()) {
1466 struct amdgpu_task_info task_info;
1467
1468 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
1469 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1470
1471 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
1472 entry->src_id, entry->src_data[0], task_info.process_name,
1473 task_info.tgid, task_info.task_name, task_info.pid);
1474 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1475 addr);
1476 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1477 status);
1478 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1479 entry->pasid);
1480 }
1481
1482 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1483 VMID);
1484 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1485 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1486 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1487 u32 protections = REG_GET_FIELD(status,
1488 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1489 PROTECTIONS);
1490
1491 info->vmid = vmid;
1492 info->mc_id = REG_GET_FIELD(status,
1493 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1494 MEMORY_CLIENT_ID);
1495 info->status = status;
1496 info->page_addr = addr;
1497 info->prot_valid = protections & 0x7 ? true : false;
1498 info->prot_read = protections & 0x8 ? true : false;
1499 info->prot_write = protections & 0x10 ? true : false;
1500 info->prot_exec = protections & 0x20 ? true : false;
1501 mb();
1502 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1503 }
1504
1505 return 0;
1506 }
1507
1508 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1509 bool enable)
1510 {
1511 uint32_t data;
1512
1513 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1514 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1515 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1516 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1517
1518 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1519 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1520 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1521
1522 data = RREG32(mmMC_HUB_MISC_VM_CG);
1523 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1524 WREG32(mmMC_HUB_MISC_VM_CG, data);
1525
1526 data = RREG32(mmMC_XPB_CLK_GAT);
1527 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1528 WREG32(mmMC_XPB_CLK_GAT, data);
1529
1530 data = RREG32(mmATC_MISC_CG);
1531 data |= ATC_MISC_CG__ENABLE_MASK;
1532 WREG32(mmATC_MISC_CG, data);
1533
1534 data = RREG32(mmMC_CITF_MISC_WR_CG);
1535 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1536 WREG32(mmMC_CITF_MISC_WR_CG, data);
1537
1538 data = RREG32(mmMC_CITF_MISC_RD_CG);
1539 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1540 WREG32(mmMC_CITF_MISC_RD_CG, data);
1541
1542 data = RREG32(mmMC_CITF_MISC_VM_CG);
1543 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1544 WREG32(mmMC_CITF_MISC_VM_CG, data);
1545
1546 data = RREG32(mmVM_L2_CG);
1547 data |= VM_L2_CG__ENABLE_MASK;
1548 WREG32(mmVM_L2_CG, data);
1549 } else {
1550 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1551 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1552 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1553
1554 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1555 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1556 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1557
1558 data = RREG32(mmMC_HUB_MISC_VM_CG);
1559 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1560 WREG32(mmMC_HUB_MISC_VM_CG, data);
1561
1562 data = RREG32(mmMC_XPB_CLK_GAT);
1563 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1564 WREG32(mmMC_XPB_CLK_GAT, data);
1565
1566 data = RREG32(mmATC_MISC_CG);
1567 data &= ~ATC_MISC_CG__ENABLE_MASK;
1568 WREG32(mmATC_MISC_CG, data);
1569
1570 data = RREG32(mmMC_CITF_MISC_WR_CG);
1571 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1572 WREG32(mmMC_CITF_MISC_WR_CG, data);
1573
1574 data = RREG32(mmMC_CITF_MISC_RD_CG);
1575 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1576 WREG32(mmMC_CITF_MISC_RD_CG, data);
1577
1578 data = RREG32(mmMC_CITF_MISC_VM_CG);
1579 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1580 WREG32(mmMC_CITF_MISC_VM_CG, data);
1581
1582 data = RREG32(mmVM_L2_CG);
1583 data &= ~VM_L2_CG__ENABLE_MASK;
1584 WREG32(mmVM_L2_CG, data);
1585 }
1586 }
1587
1588 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1589 bool enable)
1590 {
1591 uint32_t data;
1592
1593 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1594 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1595 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1596 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1597
1598 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1599 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1600 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1601
1602 data = RREG32(mmMC_HUB_MISC_VM_CG);
1603 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1604 WREG32(mmMC_HUB_MISC_VM_CG, data);
1605
1606 data = RREG32(mmMC_XPB_CLK_GAT);
1607 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1608 WREG32(mmMC_XPB_CLK_GAT, data);
1609
1610 data = RREG32(mmATC_MISC_CG);
1611 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1612 WREG32(mmATC_MISC_CG, data);
1613
1614 data = RREG32(mmMC_CITF_MISC_WR_CG);
1615 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1616 WREG32(mmMC_CITF_MISC_WR_CG, data);
1617
1618 data = RREG32(mmMC_CITF_MISC_RD_CG);
1619 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1620 WREG32(mmMC_CITF_MISC_RD_CG, data);
1621
1622 data = RREG32(mmMC_CITF_MISC_VM_CG);
1623 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1624 WREG32(mmMC_CITF_MISC_VM_CG, data);
1625
1626 data = RREG32(mmVM_L2_CG);
1627 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1628 WREG32(mmVM_L2_CG, data);
1629 } else {
1630 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1631 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1632 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1633
1634 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1635 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1636 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1637
1638 data = RREG32(mmMC_HUB_MISC_VM_CG);
1639 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1640 WREG32(mmMC_HUB_MISC_VM_CG, data);
1641
1642 data = RREG32(mmMC_XPB_CLK_GAT);
1643 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1644 WREG32(mmMC_XPB_CLK_GAT, data);
1645
1646 data = RREG32(mmATC_MISC_CG);
1647 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1648 WREG32(mmATC_MISC_CG, data);
1649
1650 data = RREG32(mmMC_CITF_MISC_WR_CG);
1651 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1652 WREG32(mmMC_CITF_MISC_WR_CG, data);
1653
1654 data = RREG32(mmMC_CITF_MISC_RD_CG);
1655 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1656 WREG32(mmMC_CITF_MISC_RD_CG, data);
1657
1658 data = RREG32(mmMC_CITF_MISC_VM_CG);
1659 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1660 WREG32(mmMC_CITF_MISC_VM_CG, data);
1661
1662 data = RREG32(mmVM_L2_CG);
1663 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1664 WREG32(mmVM_L2_CG, data);
1665 }
1666 }
1667
1668 static int gmc_v8_0_set_clockgating_state(void *handle,
1669 enum amd_clockgating_state state)
1670 {
1671 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1672
1673 if (amdgpu_sriov_vf(adev))
1674 return 0;
1675
1676 switch (adev->asic_type) {
1677 case CHIP_FIJI:
1678 fiji_update_mc_medium_grain_clock_gating(adev,
1679 state == AMD_CG_STATE_GATE);
1680 fiji_update_mc_light_sleep(adev,
1681 state == AMD_CG_STATE_GATE);
1682 break;
1683 default:
1684 break;
1685 }
1686 return 0;
1687 }
1688
1689 static int gmc_v8_0_set_powergating_state(void *handle,
1690 enum amd_powergating_state state)
1691 {
1692 return 0;
1693 }
1694
1695 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1696 {
1697 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1698 int data;
1699
1700 if (amdgpu_sriov_vf(adev))
1701 *flags = 0;
1702
1703 /* AMD_CG_SUPPORT_MC_MGCG */
1704 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1705 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1706 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1707
1708 /* AMD_CG_SUPPORT_MC_LS */
1709 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1710 *flags |= AMD_CG_SUPPORT_MC_LS;
1711 }
1712
1713 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1714 .name = "gmc_v8_0",
1715 .early_init = gmc_v8_0_early_init,
1716 .late_init = gmc_v8_0_late_init,
1717 .sw_init = gmc_v8_0_sw_init,
1718 .sw_fini = gmc_v8_0_sw_fini,
1719 .hw_init = gmc_v8_0_hw_init,
1720 .hw_fini = gmc_v8_0_hw_fini,
1721 .suspend = gmc_v8_0_suspend,
1722 .resume = gmc_v8_0_resume,
1723 .is_idle = gmc_v8_0_is_idle,
1724 .wait_for_idle = gmc_v8_0_wait_for_idle,
1725 .check_soft_reset = gmc_v8_0_check_soft_reset,
1726 .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1727 .soft_reset = gmc_v8_0_soft_reset,
1728 .post_soft_reset = gmc_v8_0_post_soft_reset,
1729 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1730 .set_powergating_state = gmc_v8_0_set_powergating_state,
1731 .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1732 };
1733
1734 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1735 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1736 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
1737 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1738 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1739 .set_prt = gmc_v8_0_set_prt,
1740 .get_vm_pde = gmc_v8_0_get_vm_pde,
1741 .get_vm_pte = gmc_v8_0_get_vm_pte
1742 };
1743
1744 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1745 .set = gmc_v8_0_vm_fault_interrupt_state,
1746 .process = gmc_v8_0_process_interrupt,
1747 };
1748
1749 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1750 {
1751 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1752 }
1753
1754 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1755 {
1756 adev->gmc.vm_fault.num_types = 1;
1757 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1758 }
1759
1760 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1761 {
1762 .type = AMD_IP_BLOCK_TYPE_GMC,
1763 .major = 8,
1764 .minor = 0,
1765 .rev = 0,
1766 .funcs = &gmc_v8_0_ip_funcs,
1767 };
1768
1769 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1770 {
1771 .type = AMD_IP_BLOCK_TYPE_GMC,
1772 .major = 8,
1773 .minor = 1,
1774 .rev = 0,
1775 .funcs = &gmc_v8_0_ip_funcs,
1776 };
1777
1778 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1779 {
1780 .type = AMD_IP_BLOCK_TYPE_GMC,
1781 .major = 8,
1782 .minor = 5,
1783 .rev = 0,
1784 .funcs = &gmc_v8_0_ip_funcs,
1785 };
Linux with added FPC-III support