drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "amdgpu_jpeg.h"
  26 #include "soc15.h"
  27 #include "soc15d.h"
  28 #include "jpeg_v2_0.h"
  29
  30 #include "vcn/vcn_2_5_offset.h"
  31 #include "vcn/vcn_2_5_sh_mask.h"
  32 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  33
  34 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET                        0x401f
  35
  36 #define JPEG25_MAX_HW_INSTANCES_ARCTURUS                        2
  37
  38 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
  39 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
  40 static int jpeg_v2_5_set_powergating_state(void *handle,
  41                                 enum amd_powergating_state state);
  42
  43 static int amdgpu_ih_clientid_jpeg[] = {
  44         SOC15_IH_CLIENTID_VCN,
  45         SOC15_IH_CLIENTID_VCN1
  46 };
  47
  48 /**
  49  * jpeg_v2_5_early_init - set function pointers
  50  *
  51  * @handle: amdgpu_device pointer
  52  *
  53  * Set ring and irq function pointers
  54  */
  55 static int jpeg_v2_5_early_init(void *handle)
  56 {
  57         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  58         if (adev->asic_type == CHIP_ARCTURUS) {
  59                 u32 harvest;
  60                 int i;
  61
  62                 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS;
  63                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
  64                         harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING);
  65                         if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
  66                                 adev->jpeg.harvest_config |= 1 << i;
  67                 }
  68
  69                 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 |
  70                                                  AMDGPU_JPEG_HARVEST_JPEG1))
  71                         return -ENOENT;
  72         } else
  73                 adev->jpeg.num_jpeg_inst = 1;
  74
  75         jpeg_v2_5_set_dec_ring_funcs(adev);
  76         jpeg_v2_5_set_irq_funcs(adev);
  77
  78         return 0;
  79 }
  80
  81 /**
  82  * jpeg_v2_5_sw_init - sw init for JPEG block
  83  *
  84  * @handle: amdgpu_device pointer
  85  *
  86  * Load firmware and sw initialization
  87  */
  88 static int jpeg_v2_5_sw_init(void *handle)
  89 {
  90         struct amdgpu_ring *ring;
  91         int i, r;
  92         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  93
  94         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
  95                 if (adev->jpeg.harvest_config & (1 << i))
  96                         continue;
  97
  98                 /* JPEG TRAP */
  99                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
 100                                 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq);
 101                 if (r)
 102                         return r;
 103         }
 104
 105         r = amdgpu_jpeg_sw_init(adev);
 106         if (r)
 107                 return r;
 108
 109         r = amdgpu_jpeg_resume(adev);
 110         if (r)
 111                 return r;
 112
 113         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 114                 if (adev->jpeg.harvest_config & (1 << i))
 115                         continue;
 116
 117                 ring = &adev->jpeg.inst[i].ring_dec;
 118                 ring->use_doorbell = true;
 119                 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
 120                 sprintf(ring->name, "jpeg_dec_%d", i);
 121                 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 0);
 122                 if (r)
 123                         return r;
 124
 125                 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
 126                 adev->jpeg.inst[i].external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH);
 127         }
 128
 129         return 0;
 130 }
 131
 132 /**
 133  * jpeg_v2_5_sw_fini - sw fini for JPEG block
 134  *
 135  * @handle: amdgpu_device pointer
 136  *
 137  * JPEG suspend and free up sw allocation
 138  */
 139 static int jpeg_v2_5_sw_fini(void *handle)
 140 {
 141         int r;
 142         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 143
 144         r = amdgpu_jpeg_suspend(adev);
 145         if (r)
 146                 return r;
 147
 148         r = amdgpu_jpeg_sw_fini(adev);
 149
 150         return r;
 151 }
 152
 153 /**
 154  * jpeg_v2_5_hw_init - start and test JPEG block
 155  *
 156  * @handle: amdgpu_device pointer
 157  *
 158  */
 159 static int jpeg_v2_5_hw_init(void *handle)
 160 {
 161         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 162         struct amdgpu_ring *ring;
 163         int i, r;
 164
 165         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 166                 if (adev->jpeg.harvest_config & (1 << i))
 167                         continue;
 168
 169                 ring = &adev->jpeg.inst[i].ring_dec;
 170                 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 171                         (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i);
 172
 173                 r = amdgpu_ring_test_helper(ring);
 174                 if (r)
 175                         return r;
 176         }
 177
 178         DRM_INFO("JPEG decode initialized successfully.\n");
 179
 180         return 0;
 181 }
 182
 183 /**
 184  * jpeg_v2_5_hw_fini - stop the hardware block
 185  *
 186  * @handle: amdgpu_device pointer
 187  *
 188  * Stop the JPEG block, mark ring as not ready any more
 189  */
 190 static int jpeg_v2_5_hw_fini(void *handle)
 191 {
 192         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 193         struct amdgpu_ring *ring;
 194         int i;
 195
 196         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 197                 if (adev->jpeg.harvest_config & (1 << i))
 198                         continue;
 199
 200                 ring = &adev->jpeg.inst[i].ring_dec;
 201                 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
 202                       RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
 203                         jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
 204
 205                 ring->sched.ready = false;
 206         }
 207
 208         return 0;
 209 }
 210
 211 /**
 212  * jpeg_v2_5_suspend - suspend JPEG block
 213  *
 214  * @handle: amdgpu_device pointer
 215  *
 216  * HW fini and suspend JPEG block
 217  */
 218 static int jpeg_v2_5_suspend(void *handle)
 219 {
 220         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 221         int r;
 222
 223         r = jpeg_v2_5_hw_fini(adev);
 224         if (r)
 225                 return r;
 226
 227         r = amdgpu_jpeg_suspend(adev);
 228
 229         return r;
 230 }
 231
 232 /**
 233  * jpeg_v2_5_resume - resume JPEG block
 234  *
 235  * @handle: amdgpu_device pointer
 236  *
 237  * Resume firmware and hw init JPEG block
 238  */
 239 static int jpeg_v2_5_resume(void *handle)
 240 {
 241         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 242         int r;
 243
 244         r = amdgpu_jpeg_resume(adev);
 245         if (r)
 246                 return r;
 247
 248         r = jpeg_v2_5_hw_init(adev);
 249
 250         return r;
 251 }
 252
 253 static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device* adev, int inst)
 254 {
 255         uint32_t data;
 256
 257         data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
 258         if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
 259                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 260         else
 261                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 262
 263         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 264         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 265         WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
 266
 267         data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
 268         data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
 269                 | JPEG_CGC_GATE__JPEG2_DEC_MASK
 270                 | JPEG_CGC_GATE__JPEG_ENC_MASK
 271                 | JPEG_CGC_GATE__JMCIF_MASK
 272                 | JPEG_CGC_GATE__JRBBM_MASK);
 273         WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
 274
 275         data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
 276         data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
 277                 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
 278                 | JPEG_CGC_CTRL__JMCIF_MODE_MASK
 279                 | JPEG_CGC_CTRL__JRBBM_MODE_MASK);
 280         WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
 281 }
 282
 283 static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device* adev, int inst)
 284 {
 285         uint32_t data;
 286
 287         data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
 288         data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
 289                 |JPEG_CGC_GATE__JPEG2_DEC_MASK
 290                 |JPEG_CGC_GATE__JPEG_ENC_MASK
 291                 |JPEG_CGC_GATE__JMCIF_MASK
 292                 |JPEG_CGC_GATE__JRBBM_MASK);
 293         WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
 294 }
 295
 296 /**
 297  * jpeg_v2_5_start - start JPEG block
 298  *
 299  * @adev: amdgpu_device pointer
 300  *
 301  * Setup and start the JPEG block
 302  */
 303 static int jpeg_v2_5_start(struct amdgpu_device *adev)
 304 {
 305         struct amdgpu_ring *ring;
 306         int i;
 307
 308         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 309                 if (adev->jpeg.harvest_config & (1 << i))
 310                         continue;
 311
 312                 ring = &adev->jpeg.inst[i].ring_dec;
 313                 /* disable anti hang mechanism */
 314                 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,
 315                         ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
 316
 317                 /* JPEG disable CGC */
 318                 jpeg_v2_5_disable_clock_gating(adev, i);
 319
 320                 /* MJPEG global tiling registers */
 321                 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
 322                         adev->gfx.config.gb_addr_config);
 323                 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
 324                         adev->gfx.config.gb_addr_config);
 325
 326                 /* enable JMI channel */
 327                 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,
 328                         ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 329
 330                 /* enable System Interrupt for JRBC */
 331                 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),
 332                         JPEG_SYS_INT_EN__DJRBC_MASK,
 333                         ~JPEG_SYS_INT_EN__DJRBC_MASK);
 334
 335                 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
 336                 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
 337                 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
 338                         lower_32_bits(ring->gpu_addr));
 339                 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
 340                         upper_32_bits(ring->gpu_addr));
 341                 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0);
 342                 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0);
 343                 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
 344                 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
 345                 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);
 346         }
 347
 348         return 0;
 349 }
 350
 351 /**
 352  * jpeg_v2_5_stop - stop JPEG block
 353  *
 354  * @adev: amdgpu_device pointer
 355  *
 356  * stop the JPEG block
 357  */
 358 static int jpeg_v2_5_stop(struct amdgpu_device *adev)
 359 {
 360         int i;
 361
 362         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 363                 if (adev->jpeg.harvest_config & (1 << i))
 364                         continue;
 365
 366                 /* reset JMI */
 367                 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),
 368                         UVD_JMI_CNTL__SOFT_RESET_MASK,
 369                         ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 370
 371                 jpeg_v2_5_enable_clock_gating(adev, i);
 372
 373                 /* enable anti hang mechanism */
 374                 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),
 375                         UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
 376                         ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
 377         }
 378
 379         return 0;
 380 }
 381
 382 /**
 383  * jpeg_v2_5_dec_ring_get_rptr - get read pointer
 384  *
 385  * @ring: amdgpu_ring pointer
 386  *
 387  * Returns the current hardware read pointer
 388  */
 389 static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
 390 {
 391         struct amdgpu_device *adev = ring->adev;
 392
 393         return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR);
 394 }
 395
 396 /**
 397  * jpeg_v2_5_dec_ring_get_wptr - get write pointer
 398  *
 399  * @ring: amdgpu_ring pointer
 400  *
 401  * Returns the current hardware write pointer
 402  */
 403 static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
 404 {
 405         struct amdgpu_device *adev = ring->adev;
 406
 407         if (ring->use_doorbell)
 408                 return adev->wb.wb[ring->wptr_offs];
 409         else
 410                 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR);
 411 }
 412
 413 /**
 414  * jpeg_v2_5_dec_ring_set_wptr - set write pointer
 415  *
 416  * @ring: amdgpu_ring pointer
 417  *
 418  * Commits the write pointer to the hardware
 419  */
 420 static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
 421 {
 422         struct amdgpu_device *adev = ring->adev;
 423
 424         if (ring->use_doorbell) {
 425                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
 426                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 427         } else {
 428                 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
 429         }
 430 }
 431
 432 static bool jpeg_v2_5_is_idle(void *handle)
 433 {
 434         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 435         int i, ret = 1;
 436
 437         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 438                 if (adev->jpeg.harvest_config & (1 << i))
 439                         continue;
 440
 441                 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) &
 442                         UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
 443                         UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
 444         }
 445
 446         return ret;
 447 }
 448
 449 static int jpeg_v2_5_wait_for_idle(void *handle)
 450 {
 451         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 452         int i, ret = 0;
 453
 454         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 455                 if (adev->jpeg.harvest_config & (1 << i))
 456                         continue;
 457
 458                 SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,
 459                         UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
 460                         UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
 461                 if (ret)
 462                         return ret;
 463         }
 464
 465         return ret;
 466 }
 467
 468 static int jpeg_v2_5_set_clockgating_state(void *handle,
 469                                           enum amd_clockgating_state state)
 470 {
 471         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 472         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
 473         int i;
 474
 475         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 476                 if (adev->jpeg.harvest_config & (1 << i))
 477                         continue;
 478
 479                 if (enable) {
 480                         if (jpeg_v2_5_is_idle(handle))
 481                                 return -EBUSY;
 482                         jpeg_v2_5_enable_clock_gating(adev, i);
 483                 } else {
 484                         jpeg_v2_5_disable_clock_gating(adev, i);
 485                 }
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int jpeg_v2_5_set_powergating_state(void *handle,
 492                                           enum amd_powergating_state state)
 493 {
 494         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 495         int ret;
 496
 497         if(state == adev->jpeg.cur_state)
 498                 return 0;
 499
 500         if (state == AMD_PG_STATE_GATE)
 501                 ret = jpeg_v2_5_stop(adev);
 502         else
 503                 ret = jpeg_v2_5_start(adev);
 504
 505         if(!ret)
 506                 adev->jpeg.cur_state = state;
 507
 508         return ret;
 509 }
 510
 511 static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev,
 512                                         struct amdgpu_irq_src *source,
 513                                         unsigned type,
 514                                         enum amdgpu_interrupt_state state)
 515 {
 516         return 0;
 517 }
 518
 519 static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev,
 520                                       struct amdgpu_irq_src *source,
 521                                       struct amdgpu_iv_entry *entry)
 522 {
 523         uint32_t ip_instance;
 524
 525         switch (entry->client_id) {
 526         case SOC15_IH_CLIENTID_VCN:
 527                 ip_instance = 0;
 528                 break;
 529         case SOC15_IH_CLIENTID_VCN1:
 530                 ip_instance = 1;
 531                 break;
 532         default:
 533                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
 534                 return 0;
 535         }
 536
 537         DRM_DEBUG("IH: JPEG TRAP\n");
 538
 539         switch (entry->src_id) {
 540         case VCN_2_0__SRCID__JPEG_DECODE:
 541                 amdgpu_fence_process(&adev->jpeg.inst[ip_instance].ring_dec);
 542                 break;
 543         default:
 544                 DRM_ERROR("Unhandled interrupt: %d %d\n",
 545                           entry->src_id, entry->src_data[0]);
 546                 break;
 547         }
 548
 549         return 0;
 550 }
 551
 552 static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
 553         .name = "jpeg_v2_5",
 554         .early_init = jpeg_v2_5_early_init,
 555         .late_init = NULL,
 556         .sw_init = jpeg_v2_5_sw_init,
 557         .sw_fini = jpeg_v2_5_sw_fini,
 558         .hw_init = jpeg_v2_5_hw_init,
 559         .hw_fini = jpeg_v2_5_hw_fini,
 560         .suspend = jpeg_v2_5_suspend,
 561         .resume = jpeg_v2_5_resume,
 562         .is_idle = jpeg_v2_5_is_idle,
 563         .wait_for_idle = jpeg_v2_5_wait_for_idle,
 564         .check_soft_reset = NULL,
 565         .pre_soft_reset = NULL,
 566         .soft_reset = NULL,
 567         .post_soft_reset = NULL,
 568         .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
 569         .set_powergating_state = jpeg_v2_5_set_powergating_state,
 570 };
 571
 572 static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
 573         .type = AMDGPU_RING_TYPE_VCN_JPEG,
 574         .align_mask = 0xf,
 575         .vmhub = AMDGPU_MMHUB_1,
 576         .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
 577         .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
 578         .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
 579         .emit_frame_size =
 580                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 581                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
 582                 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
 583                 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
 584                 8 + 16,
 585         .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
 586         .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
 587         .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
 588         .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
 589         .test_ring = amdgpu_jpeg_dec_ring_test_ring,
 590         .test_ib = amdgpu_jpeg_dec_ring_test_ib,
 591         .insert_nop = jpeg_v2_0_dec_ring_nop,
 592         .insert_start = jpeg_v2_0_dec_ring_insert_start,
 593         .insert_end = jpeg_v2_0_dec_ring_insert_end,
 594         .pad_ib = amdgpu_ring_generic_pad_ib,
 595         .begin_use = amdgpu_jpeg_ring_begin_use,
 596         .end_use = amdgpu_jpeg_ring_end_use,
 597         .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
 598         .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
 599         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 600 };
 601
 602 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
 603 {
 604         int i;
 605
 606         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 607                 if (adev->jpeg.harvest_config & (1 << i))
 608                         continue;
 609
 610                 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs;
 611                 adev->jpeg.inst[i].ring_dec.me = i;
 612                 DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i);
 613         }
 614 }
 615
 616 static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = {
 617         .set = jpeg_v2_5_set_interrupt_state,
 618         .process = jpeg_v2_5_process_interrupt,
 619 };
 620
 621 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev)
 622 {
 623         int i;
 624
 625         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 626                 if (adev->jpeg.harvest_config & (1 << i))
 627                         continue;
 628
 629                 adev->jpeg.inst[i].irq.num_types = 1;
 630                 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs;
 631         }
 632 }
 633
 634 const struct amdgpu_ip_block_version jpeg_v2_5_ip_block =
 635 {
 636                 .type = AMD_IP_BLOCK_TYPE_JPEG,
 637                 .major = 2,
 638                 .minor = 5,
 639                 .rev = 0,
 640                 .funcs = &jpeg_v2_5_ip_funcs,
 641 };