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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / amdgpu / psp_v11_0.c
blob685dd9754c67a7123c62a8812dfe5f4b91851098
1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_psp.h"
28 #include "amdgpu_ucode.h"
29 #include "soc15_common.h"
30 #include "psp_v11_0.h"
31
32 #include "mp/mp_11_0_offset.h"
33 #include "mp/mp_11_0_sh_mask.h"
34 #include "gc/gc_9_0_offset.h"
35 #include "sdma0/sdma0_4_0_offset.h"
36 #include "nbio/nbio_7_4_offset.h"
37
38 #include "oss/osssys_4_0_offset.h"
39 #include "oss/osssys_4_0_sh_mask.h"
40
41 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
42 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
43 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
44 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
45 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
46 MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
47 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
48 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
49 MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
50 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
51 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
52 MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
53 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
54 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
55 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
56
57 /* address block */
58 #define smnMP1_FIRMWARE_FLAGS 0x3010024
59 /* navi10 reg offset define */
60 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61
61 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62
62 #define mmSDMA0_UCODE_ADDR_NV10 0x5880
63 #define mmSDMA0_UCODE_DATA_NV10 0x5881
64 /* memory training timeout define */
65 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
66
67 static int psp_v11_0_init_microcode(struct psp_context *psp)
68 {
69 struct amdgpu_device *adev = psp->adev;
70 const char *chip_name;
71 char fw_name[30];
72 int err = 0;
73 const struct psp_firmware_header_v1_0 *sos_hdr;
74 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
75 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
76 const struct psp_firmware_header_v1_0 *asd_hdr;
77 const struct ta_firmware_header_v1_0 *ta_hdr;
78
79 DRM_DEBUG("\n");
80
81 switch (adev->asic_type) {
82 case CHIP_VEGA20:
83 chip_name = "vega20";
84 break;
85 case CHIP_NAVI10:
86 chip_name = "navi10";
87 break;
88 case CHIP_NAVI14:
89 chip_name = "navi14";
90 break;
91 case CHIP_NAVI12:
92 chip_name = "navi12";
93 break;
94 case CHIP_ARCTURUS:
95 chip_name = "arcturus";
96 break;
97 default:
98 BUG();
99 }
100
101 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
102 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
103 if (err)
104 goto out;
105
106 err = amdgpu_ucode_validate(adev->psp.sos_fw);
107 if (err)
108 goto out;
109
110 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
111 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
112
113 switch (sos_hdr->header.header_version_major) {
114 case 1:
115 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
116 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
117 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
118 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
119 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
120 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
121 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
122 le32_to_cpu(sos_hdr->sos_offset_bytes);
123 if (sos_hdr->header.header_version_minor == 1) {
124 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
125 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
126 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
127 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
128 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
129 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
130 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
131 }
132 if (sos_hdr->header.header_version_minor == 2) {
133 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
134 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
135 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
136 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
137 }
138 break;
139 default:
140 dev_err(adev->dev,
141 "Unsupported psp sos firmware\n");
142 err = -EINVAL;
143 goto out;
144 }
145
146 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
147 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
148 if (err)
149 goto out1;
150
151 err = amdgpu_ucode_validate(adev->psp.asd_fw);
152 if (err)
153 goto out1;
154
155 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
156 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
157 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
158 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
159 adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
160 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
161
162 switch (adev->asic_type) {
163 case CHIP_VEGA20:
164 case CHIP_ARCTURUS:
165 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
166 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
167 if (err) {
168 release_firmware(adev->psp.ta_fw);
169 adev->psp.ta_fw = NULL;
170 dev_info(adev->dev,
171 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
172 } else {
173 err = amdgpu_ucode_validate(adev->psp.ta_fw);
174 if (err)
175 goto out2;
176
177 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
178 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
179 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
180 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
181 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
182 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
183 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
184 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
185 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr +
186 le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
187 }
188 break;
189 case CHIP_NAVI10:
190 case CHIP_NAVI14:
191 case CHIP_NAVI12:
192 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
193 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
194 if (err) {
195 release_firmware(adev->psp.ta_fw);
196 adev->psp.ta_fw = NULL;
197 dev_info(adev->dev,
198 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
199 } else {
200 err = amdgpu_ucode_validate(adev->psp.ta_fw);
201 if (err)
202 goto out2;
203
204 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
205 adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
206 adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
207 adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr +
208 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
209
210 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
211
212 adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
213 adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
214 adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr +
215 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
216 }
217 break;
218 default:
219 BUG();
220 }
221
222 return 0;
223
224 out2:
225 release_firmware(adev->psp.ta_fw);
226 adev->psp.ta_fw = NULL;
227 out1:
228 release_firmware(adev->psp.asd_fw);
229 adev->psp.asd_fw = NULL;
230 out:
231 dev_err(adev->dev,
232 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
233 release_firmware(adev->psp.sos_fw);
234 adev->psp.sos_fw = NULL;
235
236 return err;
237 }
238
239 int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
240 {
241 struct amdgpu_device *adev = psp->adev;
242
243 int ret;
244 int retry_loop;
245
246 for (retry_loop = 0; retry_loop < 10; retry_loop++) {
247 /* Wait for bootloader to signify that is
248 ready having bit 31 of C2PMSG_35 set to 1 */
249 ret = psp_wait_for(psp,
250 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
251 0x80000000,
252 0x80000000,
253 false);
254
255 if (ret == 0)
256 return 0;
257 }
258
259 return ret;
260 }
261
262 static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
263 {
264 struct amdgpu_device *adev = psp->adev;
265 uint32_t sol_reg;
266
267 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
268
269 return sol_reg != 0x0;
270 }
271
272 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
273 {
274 int ret;
275 uint32_t psp_gfxdrv_command_reg = 0;
276 struct amdgpu_device *adev = psp->adev;
277
278 /* Check tOS sign of life register to confirm sys driver and sOS
279 * are already been loaded.
280 */
281 if (psp_v11_0_is_sos_alive(psp)) {
282 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
283 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
284 return 0;
285 }
286
287 ret = psp_v11_0_wait_for_bootloader(psp);
288 if (ret)
289 return ret;
290
291 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
292
293 /* Copy PSP KDB binary to memory */
294 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
295
296 /* Provide the PSP KDB to bootloader */
297 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
298 (uint32_t)(psp->fw_pri_mc_addr >> 20));
299 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
300 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
301 psp_gfxdrv_command_reg);
302
303 ret = psp_v11_0_wait_for_bootloader(psp);
304
305 return ret;
306 }
307
308 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
309 {
310 int ret;
311 uint32_t psp_gfxdrv_command_reg = 0;
312 struct amdgpu_device *adev = psp->adev;
313
314 /* Check sOS sign of life register to confirm sys driver and sOS
315 * are already been loaded.
316 */
317 if (psp_v11_0_is_sos_alive(psp)) {
318 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
319 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
320 return 0;
321 }
322
323 ret = psp_v11_0_wait_for_bootloader(psp);
324 if (ret)
325 return ret;
326
327 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
328
329 /* Copy PSP System Driver binary to memory */
330 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
331
332 /* Provide the sys driver to bootloader */
333 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
334 (uint32_t)(psp->fw_pri_mc_addr >> 20));
335 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
336 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
337 psp_gfxdrv_command_reg);
338
339 /* there might be handshake issue with hardware which needs delay */
340 mdelay(20);
341
342 ret = psp_v11_0_wait_for_bootloader(psp);
343
344 return ret;
345 }
346
347 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
348 {
349 int ret;
350 unsigned int psp_gfxdrv_command_reg = 0;
351 struct amdgpu_device *adev = psp->adev;
352
353 /* Check sOS sign of life register to confirm sys driver and sOS
354 * are already been loaded.
355 */
356 if (psp_v11_0_is_sos_alive(psp))
357 return 0;
358
359 ret = psp_v11_0_wait_for_bootloader(psp);
360 if (ret)
361 return ret;
362
363 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
364
365 /* Copy Secure OS binary to PSP memory */
366 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
367
368 /* Provide the PSP secure OS to bootloader */
369 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
370 (uint32_t)(psp->fw_pri_mc_addr >> 20));
371 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
372 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
373 psp_gfxdrv_command_reg);
374
375 /* there might be handshake issue with hardware which needs delay */
376 mdelay(20);
377 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
378 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
379 0, true);
380
381 return ret;
382 }
383
384 static void psp_v11_0_reroute_ih(struct psp_context *psp)
385 {
386 struct amdgpu_device *adev = psp->adev;
387 uint32_t tmp;
388
389 /* Change IH ring for VMC */
390 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
391 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
392 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
393
394 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
395 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
396 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
397
398 mdelay(20);
399 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
400 0x80000000, 0x8000FFFF, false);
401
402 /* Change IH ring for UMC */
403 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
404 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
405
406 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
407 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
408 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
409
410 mdelay(20);
411 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
412 0x80000000, 0x8000FFFF, false);
413 }
414
415 static int psp_v11_0_ring_init(struct psp_context *psp,
416 enum psp_ring_type ring_type)
417 {
418 int ret = 0;
419 struct psp_ring *ring;
420 struct amdgpu_device *adev = psp->adev;
421
422 psp_v11_0_reroute_ih(psp);
423
424 ring = &psp->km_ring;
425
426 ring->ring_type = ring_type;
427
428 /* allocate 4k Page of Local Frame Buffer memory for ring */
429 ring->ring_size = 0x1000;
430 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
431 AMDGPU_GEM_DOMAIN_VRAM,
432 &adev->firmware.rbuf,
433 &ring->ring_mem_mc_addr,
434 (void **)&ring->ring_mem);
435 if (ret) {
436 ring->ring_size = 0;
437 return ret;
438 }
439
440 return 0;
441 }
442
443 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
444 {
445 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
446 return true;
447 return false;
448 }
449
450 static int psp_v11_0_ring_stop(struct psp_context *psp,
451 enum psp_ring_type ring_type)
452 {
453 int ret = 0;
454 struct amdgpu_device *adev = psp->adev;
455
456 /* Write the ring destroy command*/
457 if (psp_v11_0_support_vmr_ring(psp))
458 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
459 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
460 else
461 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
462 GFX_CTRL_CMD_ID_DESTROY_RINGS);
463
464 /* there might be handshake issue with hardware which needs delay */
465 mdelay(20);
466
467 /* Wait for response flag (bit 31) */
468 if (psp_v11_0_support_vmr_ring(psp))
469 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
470 0x80000000, 0x80000000, false);
471 else
472 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
473 0x80000000, 0x80000000, false);
474
475 return ret;
476 }
477
478 static int psp_v11_0_ring_create(struct psp_context *psp,
479 enum psp_ring_type ring_type)
480 {
481 int ret = 0;
482 unsigned int psp_ring_reg = 0;
483 struct psp_ring *ring = &psp->km_ring;
484 struct amdgpu_device *adev = psp->adev;
485
486 if (psp_v11_0_support_vmr_ring(psp)) {
487 ret = psp_v11_0_ring_stop(psp, ring_type);
488 if (ret) {
489 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
490 return ret;
491 }
492
493 /* Write low address of the ring to C2PMSG_102 */
494 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
495 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
496 /* Write high address of the ring to C2PMSG_103 */
497 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
498 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
499
500 /* Write the ring initialization command to C2PMSG_101 */
501 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
502 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
503
504 /* there might be handshake issue with hardware which needs delay */
505 mdelay(20);
506
507 /* Wait for response flag (bit 31) in C2PMSG_101 */
508 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
509 0x80000000, 0x8000FFFF, false);
510
511 } else {
512 /* Wait for sOS ready for ring creation */
513 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
514 0x80000000, 0x80000000, false);
515 if (ret) {
516 DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
517 return ret;
518 }
519
520 /* Write low address of the ring to C2PMSG_69 */
521 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
522 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
523 /* Write high address of the ring to C2PMSG_70 */
524 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
525 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
526 /* Write size of ring to C2PMSG_71 */
527 psp_ring_reg = ring->ring_size;
528 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
529 /* Write the ring initialization command to C2PMSG_64 */
530 psp_ring_reg = ring_type;
531 psp_ring_reg = psp_ring_reg << 16;
532 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
533
534 /* there might be handshake issue with hardware which needs delay */
535 mdelay(20);
536
537 /* Wait for response flag (bit 31) in C2PMSG_64 */
538 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
539 0x80000000, 0x8000FFFF, false);
540 }
541
542 return ret;
543 }
544
545
546 static int psp_v11_0_ring_destroy(struct psp_context *psp,
547 enum psp_ring_type ring_type)
548 {
549 int ret = 0;
550 struct psp_ring *ring = &psp->km_ring;
551 struct amdgpu_device *adev = psp->adev;
552
553 ret = psp_v11_0_ring_stop(psp, ring_type);
554 if (ret)
555 DRM_ERROR("Fail to stop psp ring\n");
556
557 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
558 &ring->ring_mem_mc_addr,
559 (void **)&ring->ring_mem);
560
561 return ret;
562 }
563
564 static int
565 psp_v11_0_sram_map(struct amdgpu_device *adev,
566 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
567 unsigned int *sram_data_reg_offset,
568 enum AMDGPU_UCODE_ID ucode_id)
569 {
570 int ret = 0;
571
572 switch (ucode_id) {
573 /* TODO: needs to confirm */
574 #if 0
575 case AMDGPU_UCODE_ID_SMC:
576 *sram_offset = 0;
577 *sram_addr_reg_offset = 0;
578 *sram_data_reg_offset = 0;
579 break;
580 #endif
581
582 case AMDGPU_UCODE_ID_CP_CE:
583 *sram_offset = 0x0;
584 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
585 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
586 break;
587
588 case AMDGPU_UCODE_ID_CP_PFP:
589 *sram_offset = 0x0;
590 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
591 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
592 break;
593
594 case AMDGPU_UCODE_ID_CP_ME:
595 *sram_offset = 0x0;
596 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
597 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
598 break;
599
600 case AMDGPU_UCODE_ID_CP_MEC1:
601 *sram_offset = 0x10000;
602 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
603 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
604 break;
605
606 case AMDGPU_UCODE_ID_CP_MEC2:
607 *sram_offset = 0x10000;
608 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
609 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
610 break;
611
612 case AMDGPU_UCODE_ID_RLC_G:
613 *sram_offset = 0x2000;
614 if (adev->asic_type < CHIP_NAVI10) {
615 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
616 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
617 } else {
618 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10;
619 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10;
620 }
621 break;
622
623 case AMDGPU_UCODE_ID_SDMA0:
624 *sram_offset = 0x0;
625 if (adev->asic_type < CHIP_NAVI10) {
626 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
627 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
628 } else {
629 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10;
630 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10;
631 }
632 break;
633
634 /* TODO: needs to confirm */
635 #if 0
636 case AMDGPU_UCODE_ID_SDMA1:
637 *sram_offset = ;
638 *sram_addr_reg_offset = ;
639 break;
640
641 case AMDGPU_UCODE_ID_UVD:
642 *sram_offset = ;
643 *sram_addr_reg_offset = ;
644 break;
645
646 case AMDGPU_UCODE_ID_VCE:
647 *sram_offset = ;
648 *sram_addr_reg_offset = ;
649 break;
650 #endif
651
652 case AMDGPU_UCODE_ID_MAXIMUM:
653 default:
654 ret = -EINVAL;
655 break;
656 }
657
658 return ret;
659 }
660
661 static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
662 struct amdgpu_firmware_info *ucode,
663 enum AMDGPU_UCODE_ID ucode_type)
664 {
665 int err = 0;
666 unsigned int fw_sram_reg_val = 0;
667 unsigned int fw_sram_addr_reg_offset = 0;
668 unsigned int fw_sram_data_reg_offset = 0;
669 unsigned int ucode_size;
670 uint32_t *ucode_mem = NULL;
671 struct amdgpu_device *adev = psp->adev;
672
673 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
674 &fw_sram_data_reg_offset, ucode_type);
675 if (err)
676 return false;
677
678 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
679
680 ucode_size = ucode->ucode_size;
681 ucode_mem = (uint32_t *)ucode->kaddr;
682 while (ucode_size) {
683 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
684
685 if (*ucode_mem != fw_sram_reg_val)
686 return false;
687
688 ucode_mem++;
689 /* 4 bytes */
690 ucode_size -= 4;
691 }
692
693 return true;
694 }
695
696 static int psp_v11_0_mode1_reset(struct psp_context *psp)
697 {
698 int ret;
699 uint32_t offset;
700 struct amdgpu_device *adev = psp->adev;
701
702 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
703
704 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
705
706 if (ret) {
707 DRM_INFO("psp is not working correctly before mode1 reset!\n");
708 return -EINVAL;
709 }
710
711 /*send the mode 1 reset command*/
712 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
713
714 msleep(500);
715
716 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
717
718 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
719
720 if (ret) {
721 DRM_INFO("psp mode 1 reset failed!\n");
722 return -EINVAL;
723 }
724
725 DRM_INFO("psp mode1 reset succeed \n");
726
727 return 0;
728 }
729
730 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
731 * For now, return success and hack the hive_id so high level code can
732 * start testing
733 */
734 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
735 int number_devices, struct psp_xgmi_topology_info *topology)
736 {
737 struct ta_xgmi_shared_memory *xgmi_cmd;
738 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
739 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
740 int i;
741 int ret;
742
743 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
744 return -EINVAL;
745
746 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
747 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
748
749 /* Fill in the shared memory with topology information as input */
750 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
751 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
752 topology_info_input->num_nodes = number_devices;
753
754 for (i = 0; i < topology_info_input->num_nodes; i++) {
755 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
756 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
757 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
758 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
759 }
760
761 /* Invoke xgmi ta to get the topology information */
762 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
763 if (ret)
764 return ret;
765
766 /* Read the output topology information from the shared memory */
767 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
768 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
769 for (i = 0; i < topology->num_nodes; i++) {
770 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
771 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
772 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
773 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
774 }
775
776 return 0;
777 }
778
779 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
780 int number_devices, struct psp_xgmi_topology_info *topology)
781 {
782 struct ta_xgmi_shared_memory *xgmi_cmd;
783 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
784 int i;
785
786 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
787 return -EINVAL;
788
789 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
790 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
791
792 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
793 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
794 topology_info_input->num_nodes = number_devices;
795
796 for (i = 0; i < topology_info_input->num_nodes; i++) {
797 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
798 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
799 topology_info_input->nodes[i].is_sharing_enabled = 1;
800 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
801 }
802
803 /* Invoke xgmi ta to set topology information */
804 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
805 }
806
807 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
808 {
809 struct ta_xgmi_shared_memory *xgmi_cmd;
810 int ret;
811
812 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
813 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
814
815 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
816
817 /* Invoke xgmi ta to get hive id */
818 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
819 if (ret)
820 return ret;
821
822 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
823
824 return 0;
825 }
826
827 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
828 {
829 struct ta_xgmi_shared_memory *xgmi_cmd;
830 int ret;
831
832 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
833 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
834
835 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
836
837 /* Invoke xgmi ta to get the node id */
838 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
839 if (ret)
840 return ret;
841
842 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
843
844 return 0;
845 }
846
847 static int psp_v11_0_ras_trigger_error(struct psp_context *psp,
848 struct ta_ras_trigger_error_input *info)
849 {
850 struct ta_ras_shared_memory *ras_cmd;
851 int ret;
852
853 if (!psp->ras.ras_initialized)
854 return -EINVAL;
855
856 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
857 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
858
859 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
860 ras_cmd->ras_in_message.trigger_error = *info;
861
862 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
863 if (ret)
864 return -EINVAL;
865
866 return ras_cmd->ras_status;
867 }
868
869 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr)
870 {
871 #if 0
872 // not support yet.
873 struct ta_ras_shared_memory *ras_cmd;
874 int ret;
875
876 if (!psp->ras.ras_initialized)
877 return -EINVAL;
878
879 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
880 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
881
882 ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON;
883 ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr;
884
885 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
886 if (ret)
887 return -EINVAL;
888
889 return ras_cmd->ras_status;
890 #else
891 return -EINVAL;
892 #endif
893 }
894
895 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
896 {
897 return psp_rlc_autoload_start(psp);
898 }
899
900 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
901 {
902 int ret;
903 int i;
904 uint32_t data_32;
905 int max_wait;
906 struct amdgpu_device *adev = psp->adev;
907
908 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
909 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
910 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
911
912 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
913 for (i = 0; i < max_wait; i++) {
914 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
915 0x80000000, 0x80000000, false);
916 if (ret == 0)
917 break;
918 }
919 if (i < max_wait)
920 ret = 0;
921 else
922 ret = -ETIME;
923
924 DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
925 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
926 (ret == 0) ? "succeed" : "failed",
927 i, adev->usec_timeout/1000);
928 return ret;
929 }
930
931 static void psp_v11_0_memory_training_fini(struct psp_context *psp)
932 {
933 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
934
935 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
936 kfree(ctx->sys_cache);
937 ctx->sys_cache = NULL;
938 }
939
940 static int psp_v11_0_memory_training_init(struct psp_context *psp)
941 {
942 int ret;
943 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
944
945 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
946 DRM_DEBUG("memory training is not supported!\n");
947 return 0;
948 }
949
950 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
951 if (ctx->sys_cache == NULL) {
952 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
953 ret = -ENOMEM;
954 goto Err_out;
955 }
956
957 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
958 ctx->train_data_size,
959 ctx->p2c_train_data_offset,
960 ctx->c2p_train_data_offset);
961 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
962 return 0;
963
964 Err_out:
965 psp_v11_0_memory_training_fini(psp);
966 return ret;
967 }
968
969 /*
970 * save and restore proces
971 */
972 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
973 {
974 int ret;
975 uint32_t p2c_header[4];
976 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
977 uint32_t *pcache = (uint32_t*)ctx->sys_cache;
978
979 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
980 DRM_DEBUG("Memory training is not supported.\n");
981 return 0;
982 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
983 DRM_ERROR("Memory training initialization failure.\n");
984 return -EINVAL;
985 }
986
987 if (psp_v11_0_is_sos_alive(psp)) {
988 DRM_DEBUG("SOS is alive, skip memory training.\n");
989 return 0;
990 }
991
992 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
993 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
994 pcache[0], pcache[1], pcache[2], pcache[3],
995 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
996
997 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
998 DRM_DEBUG("Short training depends on restore.\n");
999 ops |= PSP_MEM_TRAIN_RESTORE;
1000 }
1001
1002 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
1003 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
1004 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
1005 ops |= PSP_MEM_TRAIN_SAVE;
1006 }
1007
1008 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
1009 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
1010 pcache[3] == p2c_header[3])) {
1011 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
1012 ops |= PSP_MEM_TRAIN_SAVE;
1013 }
1014
1015 if ((ops & PSP_MEM_TRAIN_SAVE) &&
1016 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
1017 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
1018 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
1019 }
1020
1021 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
1022 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
1023 ops |= PSP_MEM_TRAIN_SAVE;
1024 }
1025
1026 DRM_DEBUG("Memory training ops:%x.\n", ops);
1027
1028 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
1029 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
1030 if (ret) {
1031 DRM_ERROR("Send long training msg failed.\n");
1032 return ret;
1033 }
1034 }
1035
1036 if (ops & PSP_MEM_TRAIN_SAVE) {
1037 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
1038 }
1039
1040 if (ops & PSP_MEM_TRAIN_RESTORE) {
1041 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
1042 }
1043
1044 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
1045 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
1046 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
1047 if (ret) {
1048 DRM_ERROR("send training msg failed.\n");
1049 return ret;
1050 }
1051 }
1052 ctx->training_cnt++;
1053 return 0;
1054 }
1055
1056 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
1057 {
1058 uint32_t data;
1059 struct amdgpu_device *adev = psp->adev;
1060
1061 if (psp_v11_0_support_vmr_ring(psp))
1062 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
1063 else
1064 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
1065
1066 return data;
1067 }
1068
1069 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
1070 {
1071 struct amdgpu_device *adev = psp->adev;
1072
1073 if (psp_v11_0_support_vmr_ring(psp)) {
1074 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
1075 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
1076 } else
1077 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
1078 }
1079
1080 static const struct psp_funcs psp_v11_0_funcs = {
1081 .init_microcode = psp_v11_0_init_microcode,
1082 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
1083 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
1084 .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
1085 .ring_init = psp_v11_0_ring_init,
1086 .ring_create = psp_v11_0_ring_create,
1087 .ring_stop = psp_v11_0_ring_stop,
1088 .ring_destroy = psp_v11_0_ring_destroy,
1089 .compare_sram_data = psp_v11_0_compare_sram_data,
1090 .mode1_reset = psp_v11_0_mode1_reset,
1091 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
1092 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
1093 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
1094 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
1095 .support_vmr_ring = psp_v11_0_support_vmr_ring,
1096 .ras_trigger_error = psp_v11_0_ras_trigger_error,
1097 .ras_cure_posion = psp_v11_0_ras_cure_posion,
1098 .rlc_autoload_start = psp_v11_0_rlc_autoload_start,
1099 .mem_training_init = psp_v11_0_memory_training_init,
1100 .mem_training_fini = psp_v11_0_memory_training_fini,
1101 .mem_training = psp_v11_0_memory_training,
1102 .ring_get_wptr = psp_v11_0_ring_get_wptr,
1103 .ring_set_wptr = psp_v11_0_ring_set_wptr,
1104 };
1105
1106 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
1107 {
1108 psp->funcs = &psp_v11_0_funcs;
1109 }
Linux with added FPC-III support