drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __SDMA_V5_0_H__
  25 #define __SDMA_V5_0_H__
  26
  27 enum sdma_v5_0_utcl2_cache_read_policy {
  28         CACHE_READ_POLICY_L2__LRU    = 0x00000000,
  29         CACHE_READ_POLICY_L2__STREAM = 0x00000001,
  30         CACHE_READ_POLICY_L2__NOA    = 0x00000002,
  31         CACHE_READ_POLICY_L2__DEFAULT = CACHE_READ_POLICY_L2__NOA,
  32 };
  33
  34 enum sdma_v5_0_utcl2_cache_write_policy {
  35         CACHE_WRITE_POLICY_L2__LRU    = 0x00000000,
  36         CACHE_WRITE_POLICY_L2__STREAM = 0x00000001,
  37         CACHE_WRITE_POLICY_L2__NOA    = 0x00000002,
  38         CACHE_WRITE_POLICY_L2__BYPASS = 0x00000003,
  39         CACHE_WRITE_POLICY_L2__DEFAULT = CACHE_WRITE_POLICY_L2__BYPASS,
  40 };
  41
  42 extern const struct amd_ip_funcs sdma_v5_0_ip_funcs;
  43 extern const struct amdgpu_ip_block_version sdma_v5_0_ip_block;
  44
  45 #endif /* __SDMA_V5_0_H__ */