drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm

   1 /*
   2  * Copyright 2015-2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /* To compile this assembly code:
  24  * PROJECT=vi ./sp3 cwsr_trap_handler_gfx8.asm -hex tmp.hex
  25  */
  26
  27 /**************************************************************************/
  28 /*                      variables                                         */
  29 /**************************************************************************/
  30 var SQ_WAVE_STATUS_INST_ATC_SHIFT  = 23
  31 var SQ_WAVE_STATUS_INST_ATC_MASK   = 0x00800000
  32 var SQ_WAVE_STATUS_SPI_PRIO_SHIFT  = 1
  33 var SQ_WAVE_STATUS_SPI_PRIO_MASK   = 0x00000006
  34 var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT   = 0
  35 var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE    = 1
  36 var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT  = 3
  37 var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE   = 29
  38
  39 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT    = 12
  40 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE     = 9
  41 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT   = 8
  42 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE    = 6
  43 var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT   = 24
  44 var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE    = 3                     //FIXME  sq.blk still has 4 bits at this time while SQ programming guide has 3 bits
  45
  46 var SQ_WAVE_TRAPSTS_SAVECTX_MASK    =   0x400
  47 var SQ_WAVE_TRAPSTS_EXCE_MASK       =   0x1FF                   // Exception mask
  48 var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT   =   10
  49 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK   =   0x100
  50 var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT  =   8
  51 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK    =   0x3FF
  52 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT   =   0x0
  53 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE    =   10
  54 var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK   =   0xFFFFF800
  55 var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT  =   11
  56 var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE   =   21
  57
  58 var SQ_WAVE_IB_STS_RCNT_SHIFT           =   16                  //FIXME
  59 var SQ_WAVE_IB_STS_RCNT_SIZE            =   4                   //FIXME
  60 var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT   =   15                  //FIXME
  61 var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE    =   1                   //FIXME
  62 var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG   = 0x00007FFF    //FIXME
  63
  64 var SQ_BUF_RSRC_WORD1_ATC_SHIFT     =   24
  65 var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT   =   27
  66
  67
  68 /*      Save        */
  69 var S_SAVE_BUF_RSRC_WORD1_STRIDE        =   0x00040000          //stride is 4 bytes
  70 var S_SAVE_BUF_RSRC_WORD3_MISC          =   0x00807FAC          //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE
  71
  72 var S_SAVE_SPI_INIT_ATC_MASK            =   0x08000000          //bit[27]: ATC bit
  73 var S_SAVE_SPI_INIT_ATC_SHIFT           =   27
  74 var S_SAVE_SPI_INIT_MTYPE_MASK          =   0x70000000          //bit[30:28]: Mtype
  75 var S_SAVE_SPI_INIT_MTYPE_SHIFT         =   28
  76 var S_SAVE_SPI_INIT_FIRST_WAVE_MASK     =   0x04000000          //bit[26]: FirstWaveInTG
  77 var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT    =   26
  78
  79 var S_SAVE_PC_HI_RCNT_SHIFT             =   28                  //FIXME  check with Brian to ensure all fields other than PC[47:0] can be used
  80 var S_SAVE_PC_HI_RCNT_MASK              =   0xF0000000          //FIXME
  81 var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT     =   27                  //FIXME
  82 var S_SAVE_PC_HI_FIRST_REPLAY_MASK      =   0x08000000          //FIXME
  83
  84 var s_save_spi_init_lo              =   exec_lo
  85 var s_save_spi_init_hi              =   exec_hi
  86
  87                                                 //tba_lo and tba_hi need to be saved/restored
  88 var s_save_pc_lo            =   ttmp0           //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]}
  89 var s_save_pc_hi            =   ttmp1
  90 var s_save_exec_lo          =   ttmp2
  91 var s_save_exec_hi          =   ttmp3
  92 var s_save_status           =   ttmp4
  93 var s_save_trapsts          =   ttmp5           //not really used until the end of the SAVE routine
  94 var s_save_xnack_mask_lo    =   ttmp6
  95 var s_save_xnack_mask_hi    =   ttmp7
  96 var s_save_buf_rsrc0        =   ttmp8
  97 var s_save_buf_rsrc1        =   ttmp9
  98 var s_save_buf_rsrc2        =   ttmp10
  99 var s_save_buf_rsrc3        =   ttmp11
 100
 101 var s_save_mem_offset       =   tma_lo
 102 var s_save_alloc_size       =   s_save_trapsts          //conflict
 103 var s_save_tmp              =   s_save_buf_rsrc2        //shared with s_save_buf_rsrc2  (conflict: should not use mem access with s_save_tmp at the same time)
 104 var s_save_m0               =   tma_hi
 105
 106 /*      Restore     */
 107 var S_RESTORE_BUF_RSRC_WORD1_STRIDE         =   S_SAVE_BUF_RSRC_WORD1_STRIDE
 108 var S_RESTORE_BUF_RSRC_WORD3_MISC           =   S_SAVE_BUF_RSRC_WORD3_MISC
 109
 110 var S_RESTORE_SPI_INIT_ATC_MASK             =   0x08000000          //bit[27]: ATC bit
 111 var S_RESTORE_SPI_INIT_ATC_SHIFT            =   27
 112 var S_RESTORE_SPI_INIT_MTYPE_MASK           =   0x70000000          //bit[30:28]: Mtype
 113 var S_RESTORE_SPI_INIT_MTYPE_SHIFT          =   28
 114 var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK      =   0x04000000          //bit[26]: FirstWaveInTG
 115 var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT     =   26
 116
 117 var S_RESTORE_PC_HI_RCNT_SHIFT              =   S_SAVE_PC_HI_RCNT_SHIFT
 118 var S_RESTORE_PC_HI_RCNT_MASK               =   S_SAVE_PC_HI_RCNT_MASK
 119 var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT      =   S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
 120 var S_RESTORE_PC_HI_FIRST_REPLAY_MASK       =   S_SAVE_PC_HI_FIRST_REPLAY_MASK
 121
 122 var s_restore_spi_init_lo                   =   exec_lo
 123 var s_restore_spi_init_hi                   =   exec_hi
 124
 125 var s_restore_mem_offset        =   ttmp2
 126 var s_restore_alloc_size        =   ttmp3
 127 var s_restore_tmp               =   ttmp6               //tba_lo/hi need to be restored
 128 var s_restore_mem_offset_save   =   s_restore_tmp       //no conflict
 129
 130 var s_restore_m0            =   s_restore_alloc_size    //no conflict
 131
 132 var s_restore_mode          =   ttmp7
 133
 134 var s_restore_pc_lo         =   ttmp0
 135 var s_restore_pc_hi         =   ttmp1
 136 var s_restore_exec_lo       =   tma_lo                  //no conflict
 137 var s_restore_exec_hi       =   tma_hi                  //no conflict
 138 var s_restore_status        =   ttmp4
 139 var s_restore_trapsts       =   ttmp5
 140 var s_restore_xnack_mask_lo =   xnack_mask_lo
 141 var s_restore_xnack_mask_hi =   xnack_mask_hi
 142 var s_restore_buf_rsrc0     =   ttmp8
 143 var s_restore_buf_rsrc1     =   ttmp9
 144 var s_restore_buf_rsrc2     =   ttmp10
 145 var s_restore_buf_rsrc3     =   ttmp11
 146
 147 /**************************************************************************/
 148 /*                      trap handler entry points                         */
 149 /**************************************************************************/
 150 /* Shader Main*/
 151
 152 shader main
 153   asic(VI)
 154   type(CS)
 155
 156
 157         s_branch L_SKIP_RESTORE                                     //NOT restore. might be a regular trap or save
 158
 159 L_JUMP_TO_RESTORE:
 160     s_branch L_RESTORE                                              //restore
 161
 162 L_SKIP_RESTORE:
 163
 164     s_getreg_b32    s_save_status, hwreg(HW_REG_STATUS)                             //save STATUS since we will change SCC
 165     s_andn2_b32     s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK      //check whether this is for save
 166     s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
 167     s_and_b32       s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK    //check whether this is for save
 168     s_cbranch_scc1  L_SAVE                                      //this is the operation for save
 169
 170     // *********    Handle non-CWSR traps       *******************
 171
 172     /* read tba and tma for next level trap handler, ttmp4 is used as s_save_status */
 173     s_load_dwordx4  [ttmp8,ttmp9,ttmp10, ttmp11], [tma_lo,tma_hi], 0
 174     s_waitcnt lgkmcnt(0)
 175     s_or_b32        ttmp7, ttmp8, ttmp9
 176     s_cbranch_scc0  L_NO_NEXT_TRAP //next level trap handler not been set
 177     set_status_without_spi_prio(s_save_status, ttmp2) //restore HW status(SCC)
 178     s_setpc_b64     [ttmp8,ttmp9] //jump to next level trap handler
 179
 180 L_NO_NEXT_TRAP:
 181     s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
 182     s_and_b32       s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception
 183     s_cbranch_scc1  L_EXCP_CASE   // Exception, jump back to the shader program directly.
 184     s_add_u32       ttmp0, ttmp0, 4   // S_TRAP case, add 4 to ttmp0
 185     s_addc_u32  ttmp1, ttmp1, 0
 186 L_EXCP_CASE:
 187     s_and_b32   ttmp1, ttmp1, 0xFFFF
 188     set_status_without_spi_prio(s_save_status, ttmp2) //restore HW status(SCC)
 189     s_rfe_b64       [ttmp0, ttmp1]
 190
 191     // *********        End handling of non-CWSR traps   *******************
 192
 193 /**************************************************************************/
 194 /*                      save routine                                      */
 195 /**************************************************************************/
 196
 197 L_SAVE:
 198     s_mov_b32       s_save_tmp, 0                                                           //clear saveCtx bit
 199     s_setreg_b32    hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp     //clear saveCtx bit
 200
 201     s_mov_b32       s_save_xnack_mask_lo,   xnack_mask_lo                                   //save XNACK_MASK
 202     s_mov_b32       s_save_xnack_mask_hi,   xnack_mask_hi    //save XNACK must before any memory operation
 203     s_getreg_b32    s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE)                   //save RCNT
 204     s_lshl_b32      s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT
 205     s_or_b32        s_save_pc_hi, s_save_pc_hi, s_save_tmp
 206     s_getreg_b32    s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE)   //save FIRST_REPLAY
 207     s_lshl_b32      s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
 208     s_or_b32        s_save_pc_hi, s_save_pc_hi, s_save_tmp
 209     s_getreg_b32    s_save_tmp, hwreg(HW_REG_IB_STS)                                        //clear RCNT and FIRST_REPLAY in IB_STS
 210     s_and_b32       s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG
 211
 212     s_setreg_b32    hwreg(HW_REG_IB_STS), s_save_tmp
 213
 214     /*      inform SPI the readiness and wait for SPI's go signal */
 215     s_mov_b32       s_save_exec_lo, exec_lo                                                 //save EXEC and use EXEC for the go signal from SPI
 216     s_mov_b32       s_save_exec_hi, exec_hi
 217     s_mov_b64       exec,   0x0                                                             //clear EXEC to get ready to receive
 218
 219         s_sendmsg   sendmsg(MSG_SAVEWAVE)  //send SPI a message and wait for SPI's write to EXEC
 220
 221     // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for.
 222     s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT)
 223     s_setreg_b32 hwreg(HW_REG_STATUS), s_save_tmp
 224
 225   L_SLEEP:
 226     s_sleep 0x2                // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0
 227
 228         s_cbranch_execz L_SLEEP
 229
 230     /*      setup Resource Contants    */
 231     s_mov_b32       s_save_buf_rsrc0,   s_save_spi_init_lo                                                      //base_addr_lo
 232     s_and_b32       s_save_buf_rsrc1,   s_save_spi_init_hi, 0x0000FFFF                                          //base_addr_hi
 233     s_or_b32        s_save_buf_rsrc1,   s_save_buf_rsrc1,  S_SAVE_BUF_RSRC_WORD1_STRIDE
 234     s_mov_b32       s_save_buf_rsrc2,   0                                                                       //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited
 235     s_mov_b32       s_save_buf_rsrc3,   S_SAVE_BUF_RSRC_WORD3_MISC
 236     s_and_b32       s_save_tmp,         s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK
 237     s_lshr_b32      s_save_tmp,         s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)         //get ATC bit into position
 238     s_or_b32        s_save_buf_rsrc3,   s_save_buf_rsrc3,  s_save_tmp                                           //or ATC
 239     s_and_b32       s_save_tmp,         s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK
 240     s_lshr_b32      s_save_tmp,         s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)     //get MTYPE bits into position
 241     s_or_b32        s_save_buf_rsrc3,   s_save_buf_rsrc3,  s_save_tmp                                           //or MTYPE
 242
 243     //FIXME  right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi  (might need to save them before using them?)
 244     s_mov_b32       s_save_m0,          m0                                                                  //save M0
 245
 246     /*      global mem offset           */
 247     s_mov_b32       s_save_mem_offset,  0x0                                                                     //mem offset initial value = 0
 248
 249
 250
 251
 252     /*      save HW registers   */
 253     //////////////////////////////
 254
 255   L_SAVE_HWREG:
 256         // HWREG SR memory offset : size(VGPR)+size(SGPR)
 257        get_vgpr_size_bytes(s_save_mem_offset)
 258        get_sgpr_size_bytes(s_save_tmp)
 259        s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp
 260
 261
 262     s_mov_b32       s_save_buf_rsrc2, 0x4                               //NUM_RECORDS   in bytes
 263         s_mov_b32       s_save_buf_rsrc2,  0x1000000                                //NUM_RECORDS in bytes
 264
 265
 266     write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)                  //M0
 267     write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset)                   //PC
 268     write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset)
 269     write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset)             //EXEC
 270     write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset)
 271     write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset)              //STATUS
 272
 273     //s_save_trapsts conflicts with s_save_alloc_size
 274     s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
 275     write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset)             //TRAPSTS
 276
 277     write_hwreg_to_mem(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset)           //XNACK_MASK_LO
 278     write_hwreg_to_mem(s_save_xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset)           //XNACK_MASK_HI
 279
 280     //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2
 281     s_getreg_b32    s_save_m0, hwreg(HW_REG_MODE)                                                   //MODE
 282     write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
 283     write_hwreg_to_mem(tba_lo, s_save_buf_rsrc0, s_save_mem_offset)                     //TBA_LO
 284     write_hwreg_to_mem(tba_hi, s_save_buf_rsrc0, s_save_mem_offset)                     //TBA_HI
 285
 286
 287
 288     /*      the first wave in the threadgroup    */
 289         // save fist_wave bits in tba_hi unused bit.26
 290     s_and_b32       s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK     // extract fisrt wave bit
 291     //s_or_b32        tba_hi, s_save_tmp, tba_hi                                        // save first wave bit to tba_hi.bits[26]
 292     s_mov_b32        s_save_exec_hi, 0x0
 293     s_or_b32         s_save_exec_hi, s_save_tmp, s_save_exec_hi                          // save first wave bit to s_save_exec_hi.bits[26]
 294
 295
 296     /*          save SGPRs      */
 297         // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save...
 298     //////////////////////////////
 299
 300     // SGPR SR memory offset : size(VGPR)
 301     get_vgpr_size_bytes(s_save_mem_offset)
 302     // TODO, change RSRC word to rearrange memory layout for SGPRS
 303
 304     s_getreg_b32    s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE)               //spgr_size
 305     s_add_u32       s_save_alloc_size, s_save_alloc_size, 1
 306     s_lshl_b32      s_save_alloc_size, s_save_alloc_size, 4                         //Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
 307
 308         s_lshl_b32      s_save_buf_rsrc2,   s_save_alloc_size, 2                    //NUM_RECORDS in bytes
 309         s_mov_b32       s_save_buf_rsrc2,  0x1000000                                //NUM_RECORDS in bytes
 310
 311     // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0
 312     //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0
 313     s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0
 314     s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset
 315     s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0
 316
 317     s_mov_b32       m0, 0x0                         //SGPR initial index value =0
 318   L_SAVE_SGPR_LOOP:
 319     // SGPR is allocated in 16 SGPR granularity
 320     s_movrels_b64   s0, s0     //s0 = s[0+m0], s1 = s[1+m0]
 321     s_movrels_b64   s2, s2     //s2 = s[2+m0], s3 = s[3+m0]
 322     s_movrels_b64   s4, s4     //s4 = s[4+m0], s5 = s[5+m0]
 323     s_movrels_b64   s6, s6     //s6 = s[6+m0], s7 = s[7+m0]
 324     s_movrels_b64   s8, s8     //s8 = s[8+m0], s9 = s[9+m0]
 325     s_movrels_b64   s10, s10   //s10 = s[10+m0], s11 = s[11+m0]
 326     s_movrels_b64   s12, s12   //s12 = s[12+m0], s13 = s[13+m0]
 327     s_movrels_b64   s14, s14   //s14 = s[14+m0], s15 = s[15+m0]
 328
 329     write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4
 330     s_add_u32       m0, m0, 16                                                      //next sgpr index
 331     s_cmp_lt_u32    m0, s_save_alloc_size                                           //scc = (m0 < s_save_alloc_size) ? 1 : 0
 332     s_cbranch_scc1  L_SAVE_SGPR_LOOP                                    //SGPR save is complete?
 333     // restore s_save_buf_rsrc0,1
 334     //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo
 335     s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo
 336
 337
 338
 339
 340     /*          save first 4 VGPR, then LDS save could use   */
 341         // each wave will alloc 4 vgprs at least...
 342     /////////////////////////////////////////////////////////////////////////////////////
 343
 344     s_mov_b32       s_save_mem_offset, 0
 345     s_mov_b32       exec_lo, 0xFFFFFFFF                                             //need every thread from now on
 346     s_mov_b32       exec_hi, 0xFFFFFFFF
 347
 348         s_mov_b32       s_save_buf_rsrc2,  0x1000000                                //NUM_RECORDS in bytes
 349
 350     // VGPR Allocated in 4-GPR granularity
 351
 352         buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
 353         buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256
 354         buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*2
 355         buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*3
 356
 357
 358
 359     /*          save LDS        */
 360     //////////////////////////////
 361
 362   L_SAVE_LDS:
 363
 364         // Change EXEC to all threads...
 365     s_mov_b32       exec_lo, 0xFFFFFFFF   //need every thread from now on
 366     s_mov_b32       exec_hi, 0xFFFFFFFF
 367
 368     s_getreg_b32    s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)             //lds_size
 369     s_and_b32       s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF                //lds_size is zero?
 370     s_cbranch_scc0  L_SAVE_LDS_DONE                                                                            //no lds used? jump to L_SAVE_DONE
 371
 372     s_barrier               //LDS is used? wait for other waves in the same TG
 373     //s_and_b32     s_save_tmp, tba_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK                //exec is still used here
 374     s_and_b32       s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK                //exec is still used here
 375     s_cbranch_scc0  L_SAVE_LDS_DONE
 376
 377         // first wave do LDS save;
 378
 379     s_lshl_b32      s_save_alloc_size, s_save_alloc_size, 6                         //LDS size in dwords = lds_size * 64dw
 380     s_lshl_b32      s_save_alloc_size, s_save_alloc_size, 2                         //LDS size in bytes
 381     s_mov_b32       s_save_buf_rsrc2,  s_save_alloc_size                            //NUM_RECORDS in bytes
 382
 383     // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG)
 384     //
 385     get_vgpr_size_bytes(s_save_mem_offset)
 386     get_sgpr_size_bytes(s_save_tmp)
 387     s_add_u32  s_save_mem_offset, s_save_mem_offset, s_save_tmp
 388     s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes()
 389
 390
 391         s_mov_b32       s_save_buf_rsrc2,  0x1000000                  //NUM_RECORDS in bytes
 392     s_mov_b32       m0, 0x0                                               //lds_offset initial value = 0
 393
 394
 395       v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0
 396       v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2     // tid
 397       v_mul_i32_i24 v2, v3, 8   // tid*8
 398       v_mov_b32 v3, 256*2
 399       s_mov_b32 m0, 0x10000
 400       s_mov_b32 s0, s_save_buf_rsrc3
 401       s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF    // disable add_tid
 402       s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000   //DFMT
 403
 404 L_SAVE_LDS_LOOP_VECTOR:
 405       ds_read_b64 v[0:1], v2    //x =LDS[a], byte address
 406       s_waitcnt lgkmcnt(0)
 407       buffer_store_dwordx2  v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1  glc:1  slc:1
 408 //      s_waitcnt vmcnt(0)
 409       v_add_u32 v2, vcc[0:1], v2, v3
 410       v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size
 411       s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR
 412
 413       // restore rsrc3
 414       s_mov_b32 s_save_buf_rsrc3, s0
 415
 416 L_SAVE_LDS_DONE:
 417
 418
 419     /*          save VGPRs  - set the Rest VGPRs        */
 420     //////////////////////////////////////////////////////////////////////////////////////
 421   L_SAVE_VGPR:
 422     // VGPR SR memory offset: 0
 423     // TODO rearrange the RSRC words to use swizzle for VGPR save...
 424
 425     s_mov_b32       s_save_mem_offset, (0+256*4)                                    // for the rest VGPRs
 426     s_mov_b32       exec_lo, 0xFFFFFFFF                                             //need every thread from now on
 427     s_mov_b32       exec_hi, 0xFFFFFFFF
 428
 429     s_getreg_b32    s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)                   //vpgr_size
 430     s_add_u32       s_save_alloc_size, s_save_alloc_size, 1
 431     s_lshl_b32      s_save_alloc_size, s_save_alloc_size, 2                         //Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)   //FIXME for GFX, zero is possible
 432     s_lshl_b32      s_save_buf_rsrc2,  s_save_alloc_size, 8                         //NUM_RECORDS in bytes (64 threads*4)
 433         s_mov_b32       s_save_buf_rsrc2,  0x1000000                                //NUM_RECORDS in bytes
 434
 435     // VGPR store using dw burst
 436     s_mov_b32         m0, 0x4   //VGPR initial index value =0
 437     s_cmp_lt_u32      m0, s_save_alloc_size
 438     s_cbranch_scc0    L_SAVE_VGPR_END
 439
 440
 441     s_set_gpr_idx_on    m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1
 442     s_add_u32       s_save_alloc_size, s_save_alloc_size, 0x1000                    //add 0x1000 since we compare m0 against it later
 443
 444   L_SAVE_VGPR_LOOP:
 445     v_mov_b32       v0, v0              //v0 = v[0+m0]
 446     v_mov_b32       v1, v1              //v0 = v[0+m0]
 447     v_mov_b32       v2, v2              //v0 = v[0+m0]
 448     v_mov_b32       v3, v3              //v0 = v[0+m0]
 449
 450         buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
 451         buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256
 452         buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*2
 453         buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*3
 454
 455     s_add_u32       m0, m0, 4                                                       //next vgpr index
 456     s_add_u32       s_save_mem_offset, s_save_mem_offset, 256*4                     //every buffer_store_dword does 256 bytes
 457     s_cmp_lt_u32    m0, s_save_alloc_size                                           //scc = (m0 < s_save_alloc_size) ? 1 : 0
 458     s_cbranch_scc1  L_SAVE_VGPR_LOOP                                                //VGPR save is complete?
 459     s_set_gpr_idx_off
 460
 461 L_SAVE_VGPR_END:
 462     s_branch    L_END_PGM
 463
 464
 465
 466 /**************************************************************************/
 467 /*                      restore routine                                   */
 468 /**************************************************************************/
 469
 470 L_RESTORE:
 471     /*      Setup Resource Contants    */
 472     s_mov_b32       s_restore_buf_rsrc0,    s_restore_spi_init_lo                                                           //base_addr_lo
 473     s_and_b32       s_restore_buf_rsrc1,    s_restore_spi_init_hi, 0x0000FFFF                                               //base_addr_hi
 474     s_or_b32        s_restore_buf_rsrc1,    s_restore_buf_rsrc1,  S_RESTORE_BUF_RSRC_WORD1_STRIDE
 475     s_mov_b32       s_restore_buf_rsrc2,    0                                                                               //NUM_RECORDS initial value = 0 (in bytes)
 476     s_mov_b32       s_restore_buf_rsrc3,    S_RESTORE_BUF_RSRC_WORD3_MISC
 477     s_and_b32       s_restore_tmp,          s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK
 478     s_lshr_b32      s_restore_tmp,          s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)       //get ATC bit into position
 479     s_or_b32        s_restore_buf_rsrc3,    s_restore_buf_rsrc3,  s_restore_tmp                                             //or ATC
 480     s_and_b32       s_restore_tmp,          s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK
 481     s_lshr_b32      s_restore_tmp,          s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)   //get MTYPE bits into position
 482     s_or_b32        s_restore_buf_rsrc3,    s_restore_buf_rsrc3,  s_restore_tmp                                             //or MTYPE
 483
 484     /*      global mem offset           */
 485 //  s_mov_b32       s_restore_mem_offset, 0x0                               //mem offset initial value = 0
 486
 487     /*      the first wave in the threadgroup    */
 488     s_and_b32       s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK
 489     s_cbranch_scc0  L_RESTORE_VGPR
 490
 491     /*          restore LDS     */
 492     //////////////////////////////
 493   L_RESTORE_LDS:
 494
 495     s_mov_b32       exec_lo, 0xFFFFFFFF                                                     //need every thread from now on   //be consistent with SAVE although can be moved ahead
 496     s_mov_b32       exec_hi, 0xFFFFFFFF
 497
 498     s_getreg_b32    s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)              //lds_size
 499     s_and_b32       s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF                  //lds_size is zero?
 500     s_cbranch_scc0  L_RESTORE_VGPR                                                          //no lds used? jump to L_RESTORE_VGPR
 501     s_lshl_b32      s_restore_alloc_size, s_restore_alloc_size, 6                           //LDS size in dwords = lds_size * 64dw
 502     s_lshl_b32      s_restore_alloc_size, s_restore_alloc_size, 2                           //LDS size in bytes
 503     s_mov_b32       s_restore_buf_rsrc2,    s_restore_alloc_size                            //NUM_RECORDS in bytes
 504
 505     // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG)
 506     //
 507     get_vgpr_size_bytes(s_restore_mem_offset)
 508     get_sgpr_size_bytes(s_restore_tmp)
 509     s_add_u32  s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
 510     s_add_u32  s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes()            //FIXME, Check if offset overflow???
 511
 512
 513         s_mov_b32       s_restore_buf_rsrc2,  0x1000000                                     //NUM_RECORDS in bytes
 514     s_mov_b32       m0, 0x0                                                                 //lds_offset initial value = 0
 515
 516   L_RESTORE_LDS_LOOP:
 517         buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1                    // first 64DW
 518         buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256         // second 64DW
 519     s_add_u32       m0, m0, 256*2                                               // 128 DW
 520     s_add_u32       s_restore_mem_offset, s_restore_mem_offset, 256*2           //mem offset increased by 128DW
 521     s_cmp_lt_u32    m0, s_restore_alloc_size                                    //scc=(m0 < s_restore_alloc_size) ? 1 : 0
 522     s_cbranch_scc1  L_RESTORE_LDS_LOOP                                                      //LDS restore is complete?
 523
 524
 525     /*          restore VGPRs       */
 526     //////////////////////////////
 527   L_RESTORE_VGPR:
 528         // VGPR SR memory offset : 0
 529     s_mov_b32       s_restore_mem_offset, 0x0
 530     s_mov_b32       exec_lo, 0xFFFFFFFF                                                     //need every thread from now on   //be consistent with SAVE although can be moved ahead
 531     s_mov_b32       exec_hi, 0xFFFFFFFF
 532
 533     s_getreg_b32    s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)    //vpgr_size
 534     s_add_u32       s_restore_alloc_size, s_restore_alloc_size, 1
 535     s_lshl_b32      s_restore_alloc_size, s_restore_alloc_size, 2                           //Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
 536     s_lshl_b32      s_restore_buf_rsrc2,  s_restore_alloc_size, 8                           //NUM_RECORDS in bytes (64 threads*4)
 537         s_mov_b32       s_restore_buf_rsrc2,  0x1000000                                     //NUM_RECORDS in bytes
 538
 539     // VGPR load using dw burst
 540     s_mov_b32       s_restore_mem_offset_save, s_restore_mem_offset     // restore start with v1, v0 will be the last
 541     s_add_u32       s_restore_mem_offset, s_restore_mem_offset, 256*4
 542     s_mov_b32       m0, 4                               //VGPR initial index value = 1
 543     s_set_gpr_idx_on  m0, 0x8                       //M0[7:0] = M0[7:0] and M0[15:12] = 0x8
 544     s_add_u32       s_restore_alloc_size, s_restore_alloc_size, 0x8000                      //add 0x8000 since we compare m0 against it later
 545
 546   L_RESTORE_VGPR_LOOP:
 547         buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
 548         buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256
 549         buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2
 550         buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3
 551     s_waitcnt       vmcnt(0)                                                                //ensure data ready
 552     v_mov_b32       v0, v0                                                                  //v[0+m0] = v0
 553     v_mov_b32       v1, v1
 554     v_mov_b32       v2, v2
 555     v_mov_b32       v3, v3
 556     s_add_u32       m0, m0, 4                                                               //next vgpr index
 557     s_add_u32       s_restore_mem_offset, s_restore_mem_offset, 256*4                           //every buffer_load_dword does 256 bytes
 558     s_cmp_lt_u32    m0, s_restore_alloc_size                                                //scc = (m0 < s_restore_alloc_size) ? 1 : 0
 559     s_cbranch_scc1  L_RESTORE_VGPR_LOOP                                                     //VGPR restore (except v0) is complete?
 560     s_set_gpr_idx_off
 561                                                                                             /* VGPR restore on v0 */
 562         buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1
 563         buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256
 564         buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256*2
 565         buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256*3
 566
 567     /*          restore SGPRs       */
 568     //////////////////////////////
 569
 570     // SGPR SR memory offset : size(VGPR)
 571     get_vgpr_size_bytes(s_restore_mem_offset)
 572     get_sgpr_size_bytes(s_restore_tmp)
 573     s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
 574     s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4     // restore SGPR from S[n] to S[0], by 16 sgprs group
 575     // TODO, change RSRC word to rearrange memory layout for SGPRS
 576
 577     s_getreg_b32    s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE)                //spgr_size
 578     s_add_u32       s_restore_alloc_size, s_restore_alloc_size, 1
 579     s_lshl_b32      s_restore_alloc_size, s_restore_alloc_size, 4                           //Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
 580
 581         s_lshl_b32      s_restore_buf_rsrc2,    s_restore_alloc_size, 2                     //NUM_RECORDS in bytes
 582         s_mov_b32       s_restore_buf_rsrc2,  0x1000000                                     //NUM_RECORDS in bytes
 583
 584     /* If 112 SGPRs ar allocated, 4 sgprs are not used TBA(108,109),TMA(110,111),
 585        However, we are safe to restore these 4 SGPRs anyway, since TBA,TMA will later be restored by HWREG
 586     */
 587     s_mov_b32 m0, s_restore_alloc_size
 588
 589  L_RESTORE_SGPR_LOOP:
 590     read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)  //PV: further performance improvement can be made
 591     s_waitcnt       lgkmcnt(0)                                                              //ensure data ready
 592
 593     s_sub_u32 m0, m0, 16    // Restore from S[n] to S[0]
 594
 595     s_movreld_b64   s0, s0      //s[0+m0] = s0
 596     s_movreld_b64   s2, s2
 597     s_movreld_b64   s4, s4
 598     s_movreld_b64   s6, s6
 599     s_movreld_b64   s8, s8
 600     s_movreld_b64   s10, s10
 601     s_movreld_b64   s12, s12
 602     s_movreld_b64   s14, s14
 603
 604     s_cmp_eq_u32    m0, 0               //scc = (m0 < s_restore_alloc_size) ? 1 : 0
 605     s_cbranch_scc0  L_RESTORE_SGPR_LOOP             //SGPR restore (except s0) is complete?
 606
 607     /*      restore HW registers    */
 608     //////////////////////////////
 609   L_RESTORE_HWREG:
 610
 611     // HWREG SR memory offset : size(VGPR)+size(SGPR)
 612     get_vgpr_size_bytes(s_restore_mem_offset)
 613     get_sgpr_size_bytes(s_restore_tmp)
 614     s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
 615
 616
 617     s_mov_b32       s_restore_buf_rsrc2, 0x4                                                //NUM_RECORDS   in bytes
 618         s_mov_b32       s_restore_buf_rsrc2,  0x1000000                                     //NUM_RECORDS in bytes
 619
 620     read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset)                    //M0
 621     read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset)             //PC
 622     read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset)
 623     read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset)               //EXEC
 624     read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset)
 625     read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset)                //STATUS
 626     read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset)               //TRAPSTS
 627     read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset)                   //XNACK_MASK_LO
 628     read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset)                   //XNACK_MASK_HI
 629     read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset)              //MODE
 630     read_hwreg_from_mem(tba_lo, s_restore_buf_rsrc0, s_restore_mem_offset)                      //TBA_LO
 631     read_hwreg_from_mem(tba_hi, s_restore_buf_rsrc0, s_restore_mem_offset)                      //TBA_HI
 632
 633     s_waitcnt       lgkmcnt(0)                                                                                      //from now on, it is safe to restore STATUS and IB_STS
 634
 635     s_mov_b32       m0,         s_restore_m0
 636     s_mov_b32       exec_lo,    s_restore_exec_lo
 637     s_mov_b32       exec_hi,    s_restore_exec_hi
 638
 639     s_and_b32       s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts
 640     s_setreg_b32    hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0
 641     s_and_b32       s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts
 642     s_lshr_b32      s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT
 643     s_setreg_b32    hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0
 644     //s_setreg_b32  hwreg(HW_REG_TRAPSTS),  s_restore_trapsts      //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore
 645     s_setreg_b32    hwreg(HW_REG_MODE),     s_restore_mode
 646     //reuse s_restore_m0 as a temp register
 647     s_and_b32       s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK
 648     s_lshr_b32      s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT
 649     s_lshl_b32      s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT
 650     s_mov_b32       s_restore_tmp, 0x0                                                                              //IB_STS is zero
 651     s_or_b32        s_restore_tmp, s_restore_tmp, s_restore_m0
 652     s_and_b32       s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK
 653     s_lshr_b32      s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
 654     s_lshl_b32      s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT
 655     s_or_b32        s_restore_tmp, s_restore_tmp, s_restore_m0
 656     s_and_b32       s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK
 657     s_lshr_b32      s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT
 658     s_setreg_b32    hwreg(HW_REG_IB_STS),   s_restore_tmp
 659
 660     s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff      //pc[47:32]        //Do it here in order not to affect STATUS
 661     s_and_b64    exec, exec, exec  // Restore STATUS.EXECZ, not writable by s_setreg_b32
 662     s_and_b64    vcc, vcc, vcc  // Restore STATUS.VCCZ, not writable by s_setreg_b32
 663     set_status_without_spi_prio(s_restore_status, s_restore_tmp) // SCC is included, which is changed by previous salu
 664
 665     s_barrier                                                   //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time
 666
 667 //  s_rfe_b64 s_restore_pc_lo                                   //Return to the main shader program and resume execution
 668     s_rfe_restore_b64  s_restore_pc_lo, s_restore_m0            // s_restore_m0[0] is used to set STATUS.inst_atc
 669
 670
 671 /**************************************************************************/
 672 /*                      the END                                           */
 673 /**************************************************************************/
 674 L_END_PGM:
 675     s_endpgm
 676
 677 end
 678
 679
 680 /**************************************************************************/
 681 /*                      the helper functions                              */
 682 /**************************************************************************/
 683
 684 //Only for save hwreg to mem
 685 function write_hwreg_to_mem(s, s_rsrc, s_mem_offset)
 686         s_mov_b32 exec_lo, m0                   //assuming exec_lo is not needed anymore from this point on
 687         s_mov_b32 m0, s_mem_offset
 688         s_buffer_store_dword s, s_rsrc, m0      glc:1
 689         s_add_u32       s_mem_offset, s_mem_offset, 4
 690         s_mov_b32   m0, exec_lo
 691 end
 692
 693
 694 // HWREG are saved before SGPRs, so all HWREG could be use.
 695 function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset)
 696
 697         s_buffer_store_dwordx4 s[0], s_rsrc, 0  glc:1
 698         s_buffer_store_dwordx4 s[4], s_rsrc, 16  glc:1
 699         s_buffer_store_dwordx4 s[8], s_rsrc, 32  glc:1
 700         s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1
 701         s_add_u32       s_rsrc[0], s_rsrc[0], 4*16
 702         s_addc_u32      s_rsrc[1], s_rsrc[1], 0x0             // +scc
 703 end
 704
 705
 706 function read_hwreg_from_mem(s, s_rsrc, s_mem_offset)
 707     s_buffer_load_dword s, s_rsrc, s_mem_offset     glc:1
 708     s_add_u32       s_mem_offset, s_mem_offset, 4
 709 end
 710
 711 function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset)
 712     s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset      glc:1
 713     s_sub_u32       s_mem_offset, s_mem_offset, 4*16
 714 end
 715
 716
 717
 718 function get_lds_size_bytes(s_lds_size_byte)
 719     // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW
 720     s_getreg_b32   s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)          // lds_size
 721     s_lshl_b32     s_lds_size_byte, s_lds_size_byte, 8                      //LDS size in dwords = lds_size * 64 *4Bytes    // granularity 64DW
 722 end
 723
 724 function get_vgpr_size_bytes(s_vgpr_size_byte)
 725     s_getreg_b32   s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)  //vpgr_size
 726     s_add_u32      s_vgpr_size_byte, s_vgpr_size_byte, 1
 727     s_lshl_b32     s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4   (non-zero value)   //FIXME for GFX, zero is possible
 728 end
 729
 730 function get_sgpr_size_bytes(s_sgpr_size_byte)
 731     s_getreg_b32   s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE)  //spgr_size
 732     s_add_u32      s_sgpr_size_byte, s_sgpr_size_byte, 1
 733     s_lshl_b32     s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4   (non-zero value)
 734 end
 735
 736 function get_hwreg_size_bytes
 737     return 128 //HWREG size 128 bytes
 738 end
 739
 740 function set_status_without_spi_prio(status, tmp)
 741     // Do not restore STATUS.SPI_PRIO since scheduler may have raised it.
 742     s_lshr_b32      tmp, status, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT
 743     s_setreg_b32    hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE), tmp
 744     s_nop           0x2 // avoid S_SETREG => S_SETREG hazard
 745     s_setreg_b32    hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE), status
 746 end