drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dal_asic_id.h"
  29 #include "dc_types.h"
  30 #include "dccg.h"
  31 #include "clk_mgr_internal.h"
  32
  33 #include "dce100/dce_clk_mgr.h"
  34 #include "dce110/dce110_clk_mgr.h"
  35 #include "dce112/dce112_clk_mgr.h"
  36 #include "dce120/dce120_clk_mgr.h"
  37 #include "dcn10/rv1_clk_mgr.h"
  38 #include "dcn10/rv2_clk_mgr.h"
  39 #include "dcn20/dcn20_clk_mgr.h"
  40 #include "dcn21/rn_clk_mgr.h"
  41
  42
  43 int clk_mgr_helper_get_active_display_cnt(
  44                 struct dc *dc,
  45                 struct dc_state *context)
  46 {
  47         int i, display_count;
  48
  49         display_count = 0;
  50         for (i = 0; i < context->stream_count; i++) {
  51                 const struct dc_stream_state *stream = context->streams[i];
  52
  53                 /*
  54                  * Only notify active stream or virtual stream.
  55                  * Need to notify virtual stream to work around
  56                  * headless case. HPD does not fire when system is in
  57                  * S0i2.
  58                  */
  59                 if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)
  60                         display_count++;
  61         }
  62
  63         return display_count;
  64 }
  65
  66 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
  67 {
  68         struct dc_link *edp_link = get_edp_link(dc);
  69
  70         if (dc->hwss.exit_optimized_pwr_state)
  71                 dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
  72
  73         if (edp_link) {
  74                 clk_mgr->psr_allow_active_cache = edp_link->psr_allow_active;
  75                 dc_link_set_psr_allow_active(edp_link, false, false);
  76         }
  77
  78 }
  79
  80 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
  81 {
  82         struct dc_link *edp_link = get_edp_link(dc);
  83
  84         if (edp_link)
  85                 dc_link_set_psr_allow_active(edp_link, clk_mgr->psr_allow_active_cache, false);
  86
  87         if (dc->hwss.optimize_pwr_state)
  88                 dc->hwss.optimize_pwr_state(dc, dc->current_state);
  89
  90 }
  91
  92 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
  93 {
  94         struct hw_asic_id asic_id = ctx->asic_id;
  95
  96         struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
  97
  98         if (clk_mgr == NULL) {
  99                 BREAK_TO_DEBUGGER();
 100                 return NULL;
 101         }
 102
 103         switch (asic_id.chip_family) {
 104         case FAMILY_CI:
 105         case FAMILY_KV:
 106                 dce_clk_mgr_construct(ctx, clk_mgr);
 107                 break;
 108         case FAMILY_CZ:
 109                 dce110_clk_mgr_construct(ctx, clk_mgr);
 110                 break;
 111         case FAMILY_VI:
 112                 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
 113                                 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
 114                         dce_clk_mgr_construct(ctx, clk_mgr);
 115                         break;
 116                 }
 117                 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
 118                                 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
 119                                 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
 120                         dce112_clk_mgr_construct(ctx, clk_mgr);
 121                         break;
 122                 }
 123                 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) {
 124                         dce112_clk_mgr_construct(ctx, clk_mgr);
 125                         break;
 126                 }
 127                 break;
 128         case FAMILY_AI:
 129                 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
 130                         dce121_clk_mgr_construct(ctx, clk_mgr);
 131                 else
 132                         dce120_clk_mgr_construct(ctx, clk_mgr);
 133                 break;
 134
 135 #if defined(CONFIG_DRM_AMD_DC_DCN)
 136         case FAMILY_RV:
 137                 if (ASICREV_IS_DALI(asic_id.hw_internal_rev) ||
 138                                 ASICREV_IS_POLLOCK(asic_id.hw_internal_rev)) {
 139                         /* TEMP: this check has to come before ASICREV_IS_RENOIR */
 140                         /* which also incorrectly returns true for Dali/Pollock*/
 141                         rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
 142                         break;
 143                 }
 144                 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
 145                         rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 146                         break;
 147                 }
 148                 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
 149                         rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
 150                         break;
 151                 }
 152                 if (ASICREV_IS_RAVEN(asic_id.hw_internal_rev) ||
 153                                 ASICREV_IS_PICASSO(asic_id.hw_internal_rev)) {
 154                         rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);
 155                         break;
 156                 }
 157                 break;
 158
 159         case FAMILY_NV:
 160                 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 161                 break;
 162 #endif  /* Family RV and NV*/
 163
 164         default:
 165                 ASSERT(0); /* Unknown Asic */
 166                 break;
 167         }
 168
 169         return &clk_mgr->base;
 170 }
 171
 172 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
 173 {
 174         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 175
 176         kfree(clk_mgr);
 177 }
 178