drivers/gpu/drm/amd/display/dc/dc.h

   1 /*
   2  * Copyright 2012-14 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef DC_INTERFACE_H_
  27 #define DC_INTERFACE_H_
  28
  29 #include "dc_types.h"
  30 #include "grph_object_defs.h"
  31 #include "logger_types.h"
  32 #include "gpio_types.h"
  33 #include "link_service_types.h"
  34 #include "grph_object_ctrl_defs.h"
  35 #include <inc/hw/opp.h>
  36
  37 #include "inc/hw_sequencer.h"
  38 #include "inc/compressor.h"
  39 #include "inc/hw/dmcu.h"
  40 #include "dml/display_mode_lib.h"
  41
  42 #define DC_VER "3.2.68"
  43
  44 #define MAX_SURFACES 3
  45 #define MAX_PLANES 6
  46 #define MAX_STREAMS 6
  47 #define MAX_SINKS_PER_LINK 4
  48
  49 /*******************************************************************************
  50  * Display Core Interfaces
  51  ******************************************************************************/
  52 struct dc_versions {
  53         const char *dc_ver;
  54         struct dmcu_version dmcu_version;
  55 };
  56
  57 enum dp_protocol_version {
  58         DP_VERSION_1_4,
  59 };
  60
  61 enum dc_plane_type {
  62         DC_PLANE_TYPE_INVALID,
  63         DC_PLANE_TYPE_DCE_RGB,
  64         DC_PLANE_TYPE_DCE_UNDERLAY,
  65         DC_PLANE_TYPE_DCN_UNIVERSAL,
  66 };
  67
  68 struct dc_plane_cap {
  69         enum dc_plane_type type;
  70         uint32_t blends_with_above : 1;
  71         uint32_t blends_with_below : 1;
  72         uint32_t per_pixel_alpha : 1;
  73         struct {
  74                 uint32_t argb8888 : 1;
  75                 uint32_t nv12 : 1;
  76                 uint32_t fp16 : 1;
  77                 uint32_t p010 : 1;
  78                 uint32_t ayuv : 1;
  79         } pixel_format_support;
  80         // max upscaling factor x1000
  81         // upscaling factors are always >= 1
  82         // for example, 1080p -> 8K is 4.0, or 4000 raw value
  83         struct {
  84                 uint32_t argb8888;
  85                 uint32_t nv12;
  86                 uint32_t fp16;
  87         } max_upscale_factor;
  88         // max downscale factor x1000
  89         // downscale factors are always <= 1
  90         // for example, 8K -> 1080p is 0.25, or 250 raw value
  91         struct {
  92                 uint32_t argb8888;
  93                 uint32_t nv12;
  94                 uint32_t fp16;
  95         } max_downscale_factor;
  96 };
  97
  98 struct dc_caps {
  99         uint32_t max_streams;
 100         uint32_t max_links;
 101         uint32_t max_audios;
 102         uint32_t max_slave_planes;
 103         uint32_t max_planes;
 104         uint32_t max_downscale_ratio;
 105         uint32_t i2c_speed_in_khz;
 106         uint32_t dmdata_alloc_size;
 107         unsigned int max_cursor_size;
 108         unsigned int max_video_width;
 109         int linear_pitch_alignment;
 110         bool dcc_const_color;
 111         bool dynamic_audio;
 112         bool is_apu;
 113         bool dual_link_dvi;
 114         bool post_blend_color_processing;
 115         bool force_dp_tps4_for_cp2520;
 116         bool disable_dp_clk_share;
 117         bool psp_setup_panel_mode;
 118         bool extended_aux_timeout_support;
 119         bool dmcub_support;
 120         bool hw_3d_lut;
 121         enum dp_protocol_version max_dp_protocol_version;
 122         struct dc_plane_cap planes[MAX_PLANES];
 123 };
 124
 125 struct dc_bug_wa {
 126         bool no_connect_phy_config;
 127         bool dedcn20_305_wa;
 128         bool skip_clock_update;
 129 };
 130
 131 struct dc_dcc_surface_param {
 132         struct dc_size surface_size;
 133         enum surface_pixel_format format;
 134         enum swizzle_mode_values swizzle_mode;
 135         enum dc_scan_direction scan;
 136 };
 137
 138 struct dc_dcc_setting {
 139         unsigned int max_compressed_blk_size;
 140         unsigned int max_uncompressed_blk_size;
 141         bool independent_64b_blks;
 142 };
 143
 144 struct dc_surface_dcc_cap {
 145         union {
 146                 struct {
 147                         struct dc_dcc_setting rgb;
 148                 } grph;
 149
 150                 struct {
 151                         struct dc_dcc_setting luma;
 152                         struct dc_dcc_setting chroma;
 153                 } video;
 154         };
 155
 156         bool capable;
 157         bool const_color_support;
 158 };
 159
 160 struct dc_static_screen_params {
 161         struct {
 162                 bool force_trigger;
 163                 bool cursor_update;
 164                 bool surface_update;
 165                 bool overlay_update;
 166         } triggers;
 167         unsigned int num_frames;
 168 };
 169
 170
 171 /* Surface update type is used by dc_update_surfaces_and_stream
 172  * The update type is determined at the very beginning of the function based
 173  * on parameters passed in and decides how much programming (or updating) is
 174  * going to be done during the call.
 175  *
 176  * UPDATE_TYPE_FAST is used for really fast updates that do not require much
 177  * logical calculations or hardware register programming. This update MUST be
 178  * ISR safe on windows. Currently fast update will only be used to flip surface
 179  * address.
 180  *
 181  * UPDATE_TYPE_MED is used for slower updates which require significant hw
 182  * re-programming however do not affect bandwidth consumption or clock
 183  * requirements. At present, this is the level at which front end updates
 184  * that do not require us to run bw_calcs happen. These are in/out transfer func
 185  * updates, viewport offset changes, recout size changes and pixel depth changes.
 186  * This update can be done at ISR, but we want to minimize how often this happens.
 187  *
 188  * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
 189  * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
 190  * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
 191  * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
 192  * a full update. This cannot be done at ISR level and should be a rare event.
 193  * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
 194  * underscan we don't expect to see this call at all.
 195  */
 196
 197 enum surface_update_type {
 198         UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
 199         UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
 200         UPDATE_TYPE_FULL, /* may need to shuffle resources */
 201 };
 202
 203 /* Forward declaration*/
 204 struct dc;
 205 struct dc_plane_state;
 206 struct dc_state;
 207
 208
 209 struct dc_cap_funcs {
 210         bool (*get_dcc_compression_cap)(const struct dc *dc,
 211                         const struct dc_dcc_surface_param *input,
 212                         struct dc_surface_dcc_cap *output);
 213 };
 214
 215 struct link_training_settings;
 216
 217
 218 /* Structure to hold configuration flags set by dm at dc creation. */
 219 struct dc_config {
 220         bool gpu_vm_support;
 221         bool disable_disp_pll_sharing;
 222         bool fbc_support;
 223         bool optimize_edp_link_rate;
 224         bool disable_fractional_pwm;
 225         bool allow_seamless_boot_optimization;
 226         bool power_down_display_on_boot;
 227         bool edp_not_connected;
 228         bool force_enum_edp;
 229         bool forced_clocks;
 230         bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well
 231         bool multi_mon_pp_mclk_switch;
 232 };
 233
 234 enum visual_confirm {
 235         VISUAL_CONFIRM_DISABLE = 0,
 236         VISUAL_CONFIRM_SURFACE = 1,
 237         VISUAL_CONFIRM_HDR = 2,
 238         VISUAL_CONFIRM_MPCTREE = 4,
 239 };
 240
 241 enum dcc_option {
 242         DCC_ENABLE = 0,
 243         DCC_DISABLE = 1,
 244         DCC_HALF_REQ_DISALBE = 2,
 245 };
 246
 247 enum pipe_split_policy {
 248         MPC_SPLIT_DYNAMIC = 0,
 249         MPC_SPLIT_AVOID = 1,
 250         MPC_SPLIT_AVOID_MULT_DISP = 2,
 251 };
 252
 253 enum wm_report_mode {
 254         WM_REPORT_DEFAULT = 0,
 255         WM_REPORT_OVERRIDE = 1,
 256 };
 257 enum dtm_pstate{
 258         dtm_level_p0 = 0,/*highest voltage*/
 259         dtm_level_p1,
 260         dtm_level_p2,
 261         dtm_level_p3,
 262         dtm_level_p4,/*when active_display_count = 0*/
 263 };
 264
 265 enum dcn_pwr_state {
 266         DCN_PWR_STATE_UNKNOWN = -1,
 267         DCN_PWR_STATE_MISSION_MODE = 0,
 268         DCN_PWR_STATE_LOW_POWER = 3,
 269 };
 270
 271 /*
 272  * For any clocks that may differ per pipe
 273  * only the max is stored in this structure
 274  */
 275 struct dc_clocks {
 276         int dispclk_khz;
 277         int dppclk_khz;
 278         int dcfclk_khz;
 279         int socclk_khz;
 280         int dcfclk_deep_sleep_khz;
 281         int fclk_khz;
 282         int phyclk_khz;
 283         int dramclk_khz;
 284         bool p_state_change_support;
 285         enum dcn_pwr_state pwr_state;
 286         /*
 287          * Elements below are not compared for the purposes of
 288          * optimization required
 289          */
 290         bool prev_p_state_change_support;
 291         enum dtm_pstate dtm_level;
 292         int max_supported_dppclk_khz;
 293         int max_supported_dispclk_khz;
 294         int bw_dppclk_khz; /*a copy of dppclk_khz*/
 295         int bw_dispclk_khz;
 296 };
 297
 298 struct dc_bw_validation_profile {
 299         bool enable;
 300
 301         unsigned long long total_ticks;
 302         unsigned long long voltage_level_ticks;
 303         unsigned long long watermark_ticks;
 304         unsigned long long rq_dlg_ticks;
 305
 306         unsigned long long total_count;
 307         unsigned long long skip_fast_count;
 308         unsigned long long skip_pass_count;
 309         unsigned long long skip_fail_count;
 310 };
 311
 312 #define BW_VAL_TRACE_SETUP() \
 313                 unsigned long long end_tick = 0; \
 314                 unsigned long long voltage_level_tick = 0; \
 315                 unsigned long long watermark_tick = 0; \
 316                 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
 317                                 dm_get_timestamp(dc->ctx) : 0
 318
 319 #define BW_VAL_TRACE_COUNT() \
 320                 if (dc->debug.bw_val_profile.enable) \
 321                         dc->debug.bw_val_profile.total_count++
 322
 323 #define BW_VAL_TRACE_SKIP(status) \
 324                 if (dc->debug.bw_val_profile.enable) { \
 325                         if (!voltage_level_tick) \
 326                                 voltage_level_tick = dm_get_timestamp(dc->ctx); \
 327                         dc->debug.bw_val_profile.skip_ ## status ## _count++; \
 328                 }
 329
 330 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
 331                 if (dc->debug.bw_val_profile.enable) \
 332                         voltage_level_tick = dm_get_timestamp(dc->ctx)
 333
 334 #define BW_VAL_TRACE_END_WATERMARKS() \
 335                 if (dc->debug.bw_val_profile.enable) \
 336                         watermark_tick = dm_get_timestamp(dc->ctx)
 337
 338 #define BW_VAL_TRACE_FINISH() \
 339                 if (dc->debug.bw_val_profile.enable) { \
 340                         end_tick = dm_get_timestamp(dc->ctx); \
 341                         dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
 342                         dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
 343                         if (watermark_tick) { \
 344                                 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
 345                                 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
 346                         } \
 347                 }
 348
 349 struct dc_debug_options {
 350         enum visual_confirm visual_confirm;
 351         bool sanity_checks;
 352         bool max_disp_clk;
 353         bool surface_trace;
 354         bool timing_trace;
 355         bool clock_trace;
 356         bool validation_trace;
 357         bool bandwidth_calcs_trace;
 358         int max_downscale_src_width;
 359
 360         /* stutter efficiency related */
 361         bool disable_stutter;
 362         bool use_max_lb;
 363         enum dcc_option disable_dcc;
 364         enum pipe_split_policy pipe_split_policy;
 365         bool force_single_disp_pipe_split;
 366         bool voltage_align_fclk;
 367
 368         bool disable_dfs_bypass;
 369         bool disable_dpp_power_gate;
 370         bool disable_hubp_power_gate;
 371         bool disable_dsc_power_gate;
 372         int dsc_min_slice_height_override;
 373         int dsc_bpp_increment_div;
 374         bool native422_support;
 375         bool disable_pplib_wm_range;
 376         enum wm_report_mode pplib_wm_report_mode;
 377         unsigned int min_disp_clk_khz;
 378         unsigned int min_dpp_clk_khz;
 379         int sr_exit_time_dpm0_ns;
 380         int sr_enter_plus_exit_time_dpm0_ns;
 381         int sr_exit_time_ns;
 382         int sr_enter_plus_exit_time_ns;
 383         int urgent_latency_ns;
 384         uint32_t underflow_assert_delay_us;
 385         int percent_of_ideal_drambw;
 386         int dram_clock_change_latency_ns;
 387         bool optimized_watermark;
 388         int always_scale;
 389         bool disable_pplib_clock_request;
 390         bool disable_clock_gate;
 391         bool disable_dmcu;
 392         bool disable_psr;
 393         bool force_abm_enable;
 394         bool disable_stereo_support;
 395         bool vsr_support;
 396         bool performance_trace;
 397         bool az_endpoint_mute_only;
 398         bool always_use_regamma;
 399         bool p010_mpo_support;
 400         bool recovery_enabled;
 401         bool avoid_vbios_exec_table;
 402         bool scl_reset_length10;
 403         bool hdmi20_disable;
 404         bool skip_detection_link_training;
 405         bool remove_disconnect_edp;
 406         unsigned int force_odm_combine; //bit vector based on otg inst
 407         unsigned int force_fclk_khz;
 408         bool disable_tri_buf;
 409         bool dmub_offload_enabled;
 410         bool dmcub_emulation;
 411         bool dmub_command_table; /* for testing only */
 412         struct dc_bw_validation_profile bw_val_profile;
 413         bool disable_fec;
 414         bool disable_48mhz_pwrdwn;
 415         /* This forces a hard min on the DCFCLK requested to SMU/PP
 416          * watermarks are not affected.
 417          */
 418         unsigned int force_min_dcfclk_mhz;
 419         bool disable_timing_sync;
 420         bool cm_in_bypass;
 421         int force_clock_mode;/*every mode change.*/
 422
 423         bool nv12_iflip_vm_wa;
 424         bool disable_dram_clock_change_vactive_support;
 425         bool validate_dml_output;
 426         bool enable_dmcub_surface_flip;
 427         bool usbc_combo_phy_reset_wa;
 428 };
 429
 430 struct dc_debug_data {
 431         uint32_t ltFailCount;
 432         uint32_t i2cErrorCount;
 433         uint32_t auxErrorCount;
 434 };
 435
 436 struct dc_phy_addr_space_config {
 437         struct {
 438                 uint64_t start_addr;
 439                 uint64_t end_addr;
 440                 uint64_t fb_top;
 441                 uint64_t fb_offset;
 442                 uint64_t fb_base;
 443                 uint64_t agp_top;
 444                 uint64_t agp_bot;
 445                 uint64_t agp_base;
 446         } system_aperture;
 447
 448         struct {
 449                 uint64_t page_table_start_addr;
 450                 uint64_t page_table_end_addr;
 451                 uint64_t page_table_base_addr;
 452         } gart_config;
 453
 454         bool valid;
 455         uint64_t page_table_default_page_addr;
 456 };
 457
 458 struct dc_virtual_addr_space_config {
 459         uint64_t        page_table_base_addr;
 460         uint64_t        page_table_start_addr;
 461         uint64_t        page_table_end_addr;
 462         uint32_t        page_table_block_size_in_bytes;
 463         uint8_t         page_table_depth; // 1 = 1 level, 2 = 2 level, etc.  0 = invalid
 464 };
 465
 466 struct dc_bounding_box_overrides {
 467         int sr_exit_time_ns;
 468         int sr_enter_plus_exit_time_ns;
 469         int urgent_latency_ns;
 470         int percent_of_ideal_drambw;
 471         int dram_clock_change_latency_ns;
 472         /* This forces a hard min on the DCFCLK we use
 473          * for DML.  Unlike the debug option for forcing
 474          * DCFCLK, this override affects watermark calculations
 475          */
 476         int min_dcfclk_mhz;
 477 };
 478
 479 struct dc_state;
 480 struct resource_pool;
 481 struct dce_hwseq;
 482 struct gpu_info_soc_bounding_box_v1_0;
 483 struct dc {
 484         struct dc_versions versions;
 485         struct dc_caps caps;
 486         struct dc_cap_funcs cap_funcs;
 487         struct dc_config config;
 488         struct dc_debug_options debug;
 489         struct dc_bounding_box_overrides bb_overrides;
 490         struct dc_bug_wa work_arounds;
 491         struct dc_context *ctx;
 492         struct dc_phy_addr_space_config vm_pa_config;
 493
 494         uint8_t link_count;
 495         struct dc_link *links[MAX_PIPES * 2];
 496
 497         struct dc_state *current_state;
 498         struct resource_pool *res_pool;
 499
 500         struct clk_mgr *clk_mgr;
 501
 502         /* Display Engine Clock levels */
 503         struct dm_pp_clock_levels sclk_lvls;
 504
 505         /* Inputs into BW and WM calculations. */
 506         struct bw_calcs_dceip *bw_dceip;
 507         struct bw_calcs_vbios *bw_vbios;
 508 #ifdef CONFIG_DRM_AMD_DC_DCN
 509         struct dcn_soc_bounding_box *dcn_soc;
 510         struct dcn_ip_params *dcn_ip;
 511         struct display_mode_lib dml;
 512 #endif
 513
 514         /* HW functions */
 515         struct hw_sequencer_funcs hwss;
 516         struct dce_hwseq *hwseq;
 517
 518         /* Require to optimize clocks and bandwidth for added/removed planes */
 519         bool optimized_required;
 520
 521         /* Require to maintain clocks and bandwidth for UEFI enabled HW */
 522         int optimize_seamless_boot_streams;
 523
 524         /* FBC compressor */
 525         struct compressor *fbc_compressor;
 526
 527         struct dc_debug_data debug_data;
 528
 529         const char *build_id;
 530         struct vm_helper *vm_helper;
 531         const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
 532 };
 533
 534 enum frame_buffer_mode {
 535         FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
 536         FRAME_BUFFER_MODE_ZFB_ONLY,
 537         FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
 538 } ;
 539
 540 struct dchub_init_data {
 541         int64_t zfb_phys_addr_base;
 542         int64_t zfb_mc_base_addr;
 543         uint64_t zfb_size_in_byte;
 544         enum frame_buffer_mode fb_mode;
 545         bool dchub_initialzied;
 546         bool dchub_info_valid;
 547 };
 548
 549 struct dc_init_data {
 550         struct hw_asic_id asic_id;
 551         void *driver; /* ctx */
 552         struct cgs_device *cgs_device;
 553         struct dc_bounding_box_overrides bb_overrides;
 554
 555         int num_virtual_links;
 556         /*
 557          * If 'vbios_override' not NULL, it will be called instead
 558          * of the real VBIOS. Intended use is Diagnostics on FPGA.
 559          */
 560         struct dc_bios *vbios_override;
 561         enum dce_environment dce_environment;
 562
 563         struct dmub_offload_funcs *dmub_if;
 564         struct dc_reg_helper_state *dmub_offload;
 565
 566         struct dc_config flags;
 567         uint32_t log_mask;
 568         /**
 569          * gpu_info FW provided soc bounding box struct or 0 if not
 570          * available in FW
 571          */
 572         const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
 573 };
 574
 575 struct dc_callback_init {
 576 #ifdef CONFIG_DRM_AMD_DC_HDCP
 577         struct cp_psp cp_psp;
 578 #else
 579         uint8_t reserved;
 580 #endif
 581 };
 582
 583 struct dc *dc_create(const struct dc_init_data *init_params);
 584 void dc_hardware_init(struct dc *dc);
 585
 586 int dc_get_vmid_use_vector(struct dc *dc);
 587 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
 588 /* Returns the number of vmids supported */
 589 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
 590 void dc_init_callbacks(struct dc *dc,
 591                 const struct dc_callback_init *init_params);
 592 void dc_deinit_callbacks(struct dc *dc);
 593 void dc_destroy(struct dc **dc);
 594
 595 /*******************************************************************************
 596  * Surface Interfaces
 597  ******************************************************************************/
 598
 599 enum {
 600         TRANSFER_FUNC_POINTS = 1025
 601 };
 602
 603 struct dc_hdr_static_metadata {
 604         /* display chromaticities and white point in units of 0.00001 */
 605         unsigned int chromaticity_green_x;
 606         unsigned int chromaticity_green_y;
 607         unsigned int chromaticity_blue_x;
 608         unsigned int chromaticity_blue_y;
 609         unsigned int chromaticity_red_x;
 610         unsigned int chromaticity_red_y;
 611         unsigned int chromaticity_white_point_x;
 612         unsigned int chromaticity_white_point_y;
 613
 614         uint32_t min_luminance;
 615         uint32_t max_luminance;
 616         uint32_t maximum_content_light_level;
 617         uint32_t maximum_frame_average_light_level;
 618 };
 619
 620 enum dc_transfer_func_type {
 621         TF_TYPE_PREDEFINED,
 622         TF_TYPE_DISTRIBUTED_POINTS,
 623         TF_TYPE_BYPASS,
 624         TF_TYPE_HWPWL
 625 };
 626
 627 struct dc_transfer_func_distributed_points {
 628         struct fixed31_32 red[TRANSFER_FUNC_POINTS];
 629         struct fixed31_32 green[TRANSFER_FUNC_POINTS];
 630         struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
 631
 632         uint16_t end_exponent;
 633         uint16_t x_point_at_y1_red;
 634         uint16_t x_point_at_y1_green;
 635         uint16_t x_point_at_y1_blue;
 636 };
 637
 638 enum dc_transfer_func_predefined {
 639         TRANSFER_FUNCTION_SRGB,
 640         TRANSFER_FUNCTION_BT709,
 641         TRANSFER_FUNCTION_PQ,
 642         TRANSFER_FUNCTION_LINEAR,
 643         TRANSFER_FUNCTION_UNITY,
 644         TRANSFER_FUNCTION_HLG,
 645         TRANSFER_FUNCTION_HLG12,
 646         TRANSFER_FUNCTION_GAMMA22,
 647         TRANSFER_FUNCTION_GAMMA24,
 648         TRANSFER_FUNCTION_GAMMA26
 649 };
 650
 651
 652 struct dc_transfer_func {
 653         struct kref refcount;
 654         enum dc_transfer_func_type type;
 655         enum dc_transfer_func_predefined tf;
 656         /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
 657         uint32_t sdr_ref_white_level;
 658         struct dc_context *ctx;
 659         union {
 660                 struct pwl_params pwl;
 661                 struct dc_transfer_func_distributed_points tf_pts;
 662         };
 663 };
 664
 665
 666 union dc_3dlut_state {
 667         struct {
 668                 uint32_t initialized:1;         /*if 3dlut is went through color module for initialization */
 669                 uint32_t rmu_idx_valid:1;       /*if mux settings are valid*/
 670                 uint32_t rmu_mux_num:3;         /*index of mux to use*/
 671                 uint32_t mpc_rmu0_mux:4;        /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
 672                 uint32_t mpc_rmu1_mux:4;
 673                 uint32_t mpc_rmu2_mux:4;
 674                 uint32_t reserved:15;
 675         } bits;
 676         uint32_t raw;
 677 };
 678
 679
 680 struct dc_3dlut {
 681         struct kref refcount;
 682         struct tetrahedral_params lut_3d;
 683         struct fixed31_32 hdr_multiplier;
 684         bool initialized; /*remove after diag fix*/
 685         union dc_3dlut_state state;
 686         struct dc_context *ctx;
 687 };
 688 /*
 689  * This structure is filled in by dc_surface_get_status and contains
 690  * the last requested address and the currently active address so the called
 691  * can determine if there are any outstanding flips
 692  */
 693 struct dc_plane_status {
 694         struct dc_plane_address requested_address;
 695         struct dc_plane_address current_address;
 696         bool is_flip_pending;
 697         bool is_right_eye;
 698 };
 699
 700 union surface_update_flags {
 701
 702         struct {
 703                 uint32_t addr_update:1;
 704                 /* Medium updates */
 705                 uint32_t dcc_change:1;
 706                 uint32_t color_space_change:1;
 707                 uint32_t horizontal_mirror_change:1;
 708                 uint32_t per_pixel_alpha_change:1;
 709                 uint32_t global_alpha_change:1;
 710                 uint32_t hdr_mult:1;
 711                 uint32_t rotation_change:1;
 712                 uint32_t swizzle_change:1;
 713                 uint32_t scaling_change:1;
 714                 uint32_t position_change:1;
 715                 uint32_t in_transfer_func_change:1;
 716                 uint32_t input_csc_change:1;
 717                 uint32_t coeff_reduction_change:1;
 718                 uint32_t output_tf_change:1;
 719                 uint32_t pixel_format_change:1;
 720                 uint32_t plane_size_change:1;
 721
 722                 /* Full updates */
 723                 uint32_t new_plane:1;
 724                 uint32_t bpp_change:1;
 725                 uint32_t gamma_change:1;
 726                 uint32_t bandwidth_change:1;
 727                 uint32_t clock_change:1;
 728                 uint32_t stereo_format_change:1;
 729                 uint32_t full_update:1;
 730         } bits;
 731
 732         uint32_t raw;
 733 };
 734
 735 struct dc_plane_state {
 736         struct dc_plane_address address;
 737         struct dc_plane_flip_time time;
 738         bool triplebuffer_flips;
 739         struct scaling_taps scaling_quality;
 740         struct rect src_rect;
 741         struct rect dst_rect;
 742         struct rect clip_rect;
 743
 744         struct plane_size plane_size;
 745         union dc_tiling_info tiling_info;
 746
 747         struct dc_plane_dcc_param dcc;
 748
 749         struct dc_gamma *gamma_correction;
 750         struct dc_transfer_func *in_transfer_func;
 751         struct dc_bias_and_scale *bias_and_scale;
 752         struct dc_csc_transform input_csc_color_matrix;
 753         struct fixed31_32 coeff_reduction_factor;
 754         struct fixed31_32 hdr_mult;
 755
 756         // TODO: No longer used, remove
 757         struct dc_hdr_static_metadata hdr_static_ctx;
 758
 759         enum dc_color_space color_space;
 760
 761         struct dc_3dlut *lut3d_func;
 762         struct dc_transfer_func *in_shaper_func;
 763         struct dc_transfer_func *blend_tf;
 764
 765         enum surface_pixel_format format;
 766         enum dc_rotation_angle rotation;
 767         enum plane_stereo_format stereo_format;
 768
 769         bool is_tiling_rotated;
 770         bool per_pixel_alpha;
 771         bool global_alpha;
 772         int  global_alpha_value;
 773         bool visible;
 774         bool flip_immediate;
 775         bool horizontal_mirror;
 776         int layer_index;
 777
 778         union surface_update_flags update_flags;
 779         /* private to DC core */
 780         struct dc_plane_status status;
 781         struct dc_context *ctx;
 782
 783         /* HACK: Workaround for forcing full reprogramming under some conditions */
 784         bool force_full_update;
 785
 786         /* private to dc_surface.c */
 787         enum dc_irq_source irq_source;
 788         struct kref refcount;
 789 };
 790
 791 struct dc_plane_info {
 792         struct plane_size plane_size;
 793         union dc_tiling_info tiling_info;
 794         struct dc_plane_dcc_param dcc;
 795         enum surface_pixel_format format;
 796         enum dc_rotation_angle rotation;
 797         enum plane_stereo_format stereo_format;
 798         enum dc_color_space color_space;
 799         bool horizontal_mirror;
 800         bool visible;
 801         bool per_pixel_alpha;
 802         bool global_alpha;
 803         int  global_alpha_value;
 804         bool input_csc_enabled;
 805         int layer_index;
 806 };
 807
 808 struct dc_scaling_info {
 809         struct rect src_rect;
 810         struct rect dst_rect;
 811         struct rect clip_rect;
 812         struct scaling_taps scaling_quality;
 813 };
 814
 815 struct dc_surface_update {
 816         struct dc_plane_state *surface;
 817
 818         /* isr safe update parameters.  null means no updates */
 819         const struct dc_flip_addrs *flip_addr;
 820         const struct dc_plane_info *plane_info;
 821         const struct dc_scaling_info *scaling_info;
 822         struct fixed31_32 hdr_mult;
 823         /* following updates require alloc/sleep/spin that is not isr safe,
 824          * null means no updates
 825          */
 826         const struct dc_gamma *gamma;
 827         const struct dc_transfer_func *in_transfer_func;
 828
 829         const struct dc_csc_transform *input_csc_color_matrix;
 830         const struct fixed31_32 *coeff_reduction_factor;
 831         const struct dc_transfer_func *func_shaper;
 832         const struct dc_3dlut *lut3d_func;
 833         const struct dc_transfer_func *blend_tf;
 834 };
 835
 836 /*
 837  * Create a new surface with default parameters;
 838  */
 839 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
 840 const struct dc_plane_status *dc_plane_get_status(
 841                 const struct dc_plane_state *plane_state);
 842
 843 void dc_plane_state_retain(struct dc_plane_state *plane_state);
 844 void dc_plane_state_release(struct dc_plane_state *plane_state);
 845
 846 void dc_gamma_retain(struct dc_gamma *dc_gamma);
 847 void dc_gamma_release(struct dc_gamma **dc_gamma);
 848 struct dc_gamma *dc_create_gamma(void);
 849
 850 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
 851 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
 852 struct dc_transfer_func *dc_create_transfer_func(void);
 853
 854 struct dc_3dlut *dc_create_3dlut_func(void);
 855 void dc_3dlut_func_release(struct dc_3dlut *lut);
 856 void dc_3dlut_func_retain(struct dc_3dlut *lut);
 857 /*
 858  * This structure holds a surface address.  There could be multiple addresses
 859  * in cases such as Stereo 3D, Planar YUV, etc.  Other per-flip attributes such
 860  * as frame durations and DCC format can also be set.
 861  */
 862 struct dc_flip_addrs {
 863         struct dc_plane_address address;
 864         unsigned int flip_timestamp_in_us;
 865         bool flip_immediate;
 866         /* TODO: add flip duration for FreeSync */
 867 };
 868
 869 bool dc_post_update_surfaces_to_stream(
 870                 struct dc *dc);
 871
 872 #include "dc_stream.h"
 873
 874 /*
 875  * Structure to store surface/stream associations for validation
 876  */
 877 struct dc_validation_set {
 878         struct dc_stream_state *stream;
 879         struct dc_plane_state *plane_states[MAX_SURFACES];
 880         uint8_t plane_count;
 881 };
 882
 883 bool dc_validate_seamless_boot_timing(const struct dc *dc,
 884                                 const struct dc_sink *sink,
 885                                 struct dc_crtc_timing *crtc_timing);
 886
 887 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
 888
 889 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
 890
 891 bool dc_set_generic_gpio_for_stereo(bool enable,
 892                 struct gpio_service *gpio_service);
 893
 894 /*
 895  * fast_validate: we return after determining if we can support the new state,
 896  * but before we populate the programming info
 897  */
 898 enum dc_status dc_validate_global_state(
 899                 struct dc *dc,
 900                 struct dc_state *new_ctx,
 901                 bool fast_validate);
 902
 903
 904 void dc_resource_state_construct(
 905                 const struct dc *dc,
 906                 struct dc_state *dst_ctx);
 907
 908 void dc_resource_state_copy_construct(
 909                 const struct dc_state *src_ctx,
 910                 struct dc_state *dst_ctx);
 911
 912 void dc_resource_state_copy_construct_current(
 913                 const struct dc *dc,
 914                 struct dc_state *dst_ctx);
 915
 916 void dc_resource_state_destruct(struct dc_state *context);
 917
 918 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
 919
 920 /*
 921  * TODO update to make it about validation sets
 922  * Set up streams and links associated to drive sinks
 923  * The streams parameter is an absolute set of all active streams.
 924  *
 925  * After this call:
 926  *   Phy, Encoder, Timing Generator are programmed and enabled.
 927  *   New streams are enabled with blank stream; no memory read.
 928  */
 929 bool dc_commit_state(struct dc *dc, struct dc_state *context);
 930
 931
 932 struct dc_state *dc_create_state(struct dc *dc);
 933 struct dc_state *dc_copy_state(struct dc_state *src_ctx);
 934 void dc_retain_state(struct dc_state *context);
 935 void dc_release_state(struct dc_state *context);
 936
 937 /*******************************************************************************
 938  * Link Interfaces
 939  ******************************************************************************/
 940
 941 struct dpcd_caps {
 942         union dpcd_rev dpcd_rev;
 943         union max_lane_count max_ln_count;
 944         union max_down_spread max_down_spread;
 945         union dprx_feature dprx_feature;
 946
 947         /* valid only for eDP v1.4 or higher*/
 948         uint8_t edp_supported_link_rates_count;
 949         enum dc_link_rate edp_supported_link_rates[8];
 950
 951         /* dongle type (DP converter, CV smart dongle) */
 952         enum display_dongle_type dongle_type;
 953         /* branch device or sink device */
 954         bool is_branch_dev;
 955         /* Dongle's downstream count. */
 956         union sink_count sink_count;
 957         /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
 958         indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
 959         struct dc_dongle_caps dongle_caps;
 960
 961         uint32_t sink_dev_id;
 962         int8_t sink_dev_id_str[6];
 963         int8_t sink_hw_revision;
 964         int8_t sink_fw_revision[2];
 965
 966         uint32_t branch_dev_id;
 967         int8_t branch_dev_name[6];
 968         int8_t branch_hw_revision;
 969         int8_t branch_fw_revision[2];
 970
 971         bool allow_invalid_MSA_timing_param;
 972         bool panel_mode_edp;
 973         bool dpcd_display_control_capable;
 974         bool ext_receiver_cap_field_present;
 975         union dpcd_fec_capability fec_cap;
 976         struct dpcd_dsc_capabilities dsc_caps;
 977         struct dc_lttpr_caps lttpr_caps;
 978
 979 };
 980
 981 #include "dc_link.h"
 982
 983 /*******************************************************************************
 984  * Sink Interfaces - A sink corresponds to a display output device
 985  ******************************************************************************/
 986
 987 struct dc_container_id {
 988         // 128bit GUID in binary form
 989         unsigned char  guid[16];
 990         // 8 byte port ID -> ELD.PortID
 991         unsigned int   portId[2];
 992         // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
 993         unsigned short manufacturerName;
 994         // 2 byte product code -> ELD.ProductCode
 995         unsigned short productCode;
 996 };
 997
 998
 999 struct dc_sink_dsc_caps {
1000         // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
1001         // 'false' if they are sink's DSC caps
1002         bool is_virtual_dpcd_dsc;
1003         struct dsc_dec_dpcd_caps dsc_dec_caps;
1004 };
1005
1006 /*
1007  * The sink structure contains EDID and other display device properties
1008  */
1009 struct dc_sink {
1010         enum signal_type sink_signal;
1011         struct dc_edid dc_edid; /* raw edid */
1012         struct dc_edid_caps edid_caps; /* parse display caps */
1013         struct dc_container_id *dc_container_id;
1014         uint32_t dongle_max_pix_clk;
1015         void *priv;
1016         struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1017         bool converter_disable_audio;
1018
1019         struct dc_sink_dsc_caps sink_dsc_caps;
1020
1021         /* private to DC core */
1022         struct dc_link *link;
1023         struct dc_context *ctx;
1024
1025         uint32_t sink_id;
1026
1027         /* private to dc_sink.c */
1028         // refcount must be the last member in dc_sink, since we want the
1029         // sink structure to be logically cloneable up to (but not including)
1030         // refcount
1031         struct kref refcount;
1032 };
1033
1034 void dc_sink_retain(struct dc_sink *sink);
1035 void dc_sink_release(struct dc_sink *sink);
1036
1037 struct dc_sink_init_data {
1038         enum signal_type sink_signal;
1039         struct dc_link *link;
1040         uint32_t dongle_max_pix_clk;
1041         bool converter_disable_audio;
1042 };
1043
1044 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1045
1046 /* Newer interfaces  */
1047 struct dc_cursor {
1048         struct dc_plane_address address;
1049         struct dc_cursor_attributes attributes;
1050 };
1051
1052
1053 /*******************************************************************************
1054  * Interrupt interfaces
1055  ******************************************************************************/
1056 enum dc_irq_source dc_interrupt_to_irq_source(
1057                 struct dc *dc,
1058                 uint32_t src_id,
1059                 uint32_t ext_id);
1060 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1061 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1062 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1063                 struct dc *dc, uint32_t link_index);
1064
1065 /*******************************************************************************
1066  * Power Interfaces
1067  ******************************************************************************/
1068
1069 void dc_set_power_state(
1070                 struct dc *dc,
1071                 enum dc_acpi_cm_power_state power_state);
1072 void dc_resume(struct dc *dc);
1073 unsigned int dc_get_current_backlight_pwm(struct dc *dc);
1074 unsigned int dc_get_target_backlight_pwm(struct dc *dc);
1075
1076 bool dc_is_dmcu_initialized(struct dc *dc);
1077 bool dc_is_hw_initialized(struct dc *dc);
1078
1079 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1080 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1081 /*******************************************************************************
1082  * DSC Interfaces
1083  ******************************************************************************/
1084 #include "dc_dsc.h"
1085 #endif /* DC_INTERFACE_H_ */