drivers/gpu/drm/amd/display/dc/dc_dsc.h

   1 #ifndef DC_DSC_H_
   2 #define DC_DSC_H_
   3 /*
   4  * Copyright 2019 Advanced Micro Devices, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Author: AMD
  25  */
  26
  27 /* put it here temporarily until linux has the new addresses official defined */
  28 /* DP Extended DSC Capabilities */
  29 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0  0x0a0   /* DP 1.4a SCR */
  30 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
  31 #define DP_DSC_BRANCH_MAX_LINE_WIDTH        0x0a2
  32 #include "dc_types.h"
  33
  34 struct dc_dsc_bw_range {
  35         uint32_t min_kbps; /* Bandwidth if min_target_bpp_x16 is used */
  36         uint32_t min_target_bpp_x16;
  37         uint32_t max_kbps; /* Bandwidth if max_target_bpp_x16 is used */
  38         uint32_t max_target_bpp_x16;
  39         uint32_t stream_kbps; /* Uncompressed stream bandwidth */
  40 };
  41
  42 struct display_stream_compressor {
  43         const struct dsc_funcs *funcs;
  44         struct dc_context *ctx;
  45         int inst;
  46 };
  47
  48 struct dc_dsc_policy {
  49         bool use_min_slices_h;
  50         int max_slices_h; // Maximum available if 0
  51         int min_slice_height; // Must not be less than 8
  52         uint32_t max_target_bpp;
  53         uint32_t min_target_bpp;
  54 };
  55
  56 bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
  57                 const uint8_t *dpcd_dsc_basic_data,
  58                 const uint8_t *dpcd_dsc_ext_data,
  59                 struct dsc_dec_dpcd_caps *dsc_sink_caps);
  60
  61 bool dc_dsc_compute_bandwidth_range(
  62                 const struct display_stream_compressor *dsc,
  63                 const uint32_t dsc_min_slice_height_override,
  64                 const uint32_t min_bpp,
  65                 const uint32_t max_bpp,
  66                 const struct dsc_dec_dpcd_caps *dsc_sink_caps,
  67                 const struct dc_crtc_timing *timing,
  68                 struct dc_dsc_bw_range *range);
  69
  70 bool dc_dsc_compute_config(
  71                 const struct display_stream_compressor *dsc,
  72                 const struct dsc_dec_dpcd_caps *dsc_sink_caps,
  73                 const uint32_t dsc_min_slice_height_override,
  74                 uint32_t target_bandwidth_kbps,
  75                 const struct dc_crtc_timing *timing,
  76                 struct dc_dsc_config *dsc_cfg);
  77
  78 void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
  79                 struct dc_dsc_policy *policy);
  80
  81 void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);
  82
  83 #endif