drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #ifndef __DCE_HWSEQ_H__
  26 #define __DCE_HWSEQ_H__
  27
  28 #include "dc_types.h"
  29
  30 #define BL_REG_LIST()\
  31         SR(LVTMA_PWRSEQ_CNTL), \
  32         SR(LVTMA_PWRSEQ_STATE)
  33
  34 #define HWSEQ_DCEF_REG_LIST_DCE8() \
  35         .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
  36         .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
  37         .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \
  38         .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \
  39         .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \
  40         .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL
  41
  42 #define HWSEQ_DCEF_REG_LIST() \
  43         SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
  44         SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
  45         SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
  46         SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
  47         SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
  48         SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
  49         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
  50
  51 #define HWSEQ_BLND_REG_LIST() \
  52         SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
  53         SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
  54         SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
  55         SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
  56         SRII(BLND_V_UPDATE_LOCK, BLND, 4), \
  57         SRII(BLND_V_UPDATE_LOCK, BLND, 5), \
  58         SRII(BLND_CONTROL, BLND, 0), \
  59         SRII(BLND_CONTROL, BLND, 1), \
  60         SRII(BLND_CONTROL, BLND, 2), \
  61         SRII(BLND_CONTROL, BLND, 3), \
  62         SRII(BLND_CONTROL, BLND, 4), \
  63         SRII(BLND_CONTROL, BLND, 5)
  64
  65 #define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \
  66         SRII(PIXEL_RATE_CNTL, blk, inst), \
  67         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst)
  68
  69 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
  70         SRII(PIXEL_RATE_CNTL, blk, 0), \
  71         SRII(PIXEL_RATE_CNTL, blk, 1), \
  72         SRII(PIXEL_RATE_CNTL, blk, 2), \
  73         SRII(PIXEL_RATE_CNTL, blk, 3), \
  74         SRII(PIXEL_RATE_CNTL, blk, 4), \
  75         SRII(PIXEL_RATE_CNTL, blk, 5)
  76
  77 #define HWSEQ_PHYPLL_REG_LIST(blk) \
  78         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
  79         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \
  80         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \
  81         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
  82         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
  83         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
  84
  85 #define HWSEQ_DCE11_REG_LIST_BASE() \
  86         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
  87         SR(DCFEV_CLOCK_CONTROL), \
  88         SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
  89         SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
  90         SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
  91         SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
  92         SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
  93         SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
  94         SRII(BLND_CONTROL, BLND, 0),\
  95         SRII(BLND_CONTROL, BLND, 1),\
  96         SR(BLNDV_CONTROL),\
  97         HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\
  98         BL_REG_LIST()
  99
 100 #define HWSEQ_DCE8_REG_LIST() \
 101         HWSEQ_DCEF_REG_LIST_DCE8(), \
 102         HWSEQ_BLND_REG_LIST(), \
 103         HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\
 104         BL_REG_LIST()
 105
 106 #define HWSEQ_DCE10_REG_LIST() \
 107         HWSEQ_DCEF_REG_LIST(), \
 108         HWSEQ_BLND_REG_LIST(), \
 109         HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
 110         BL_REG_LIST()
 111
 112 #define HWSEQ_ST_REG_LIST() \
 113         HWSEQ_DCE11_REG_LIST_BASE(), \
 114         .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \
 115         .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \
 116         .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \
 117         .BLND_CONTROL[2] = mmBLNDV_CONTROL
 118
 119 #define HWSEQ_CZ_REG_LIST() \
 120         HWSEQ_DCE11_REG_LIST_BASE(), \
 121         SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
 122         SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
 123         SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
 124         SRII(BLND_CONTROL, BLND, 2), \
 125         .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \
 126         .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \
 127         .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
 128         .BLND_CONTROL[3] = mmBLNDV_CONTROL
 129
 130 #define HWSEQ_DCE120_REG_LIST() \
 131         HWSEQ_DCE10_REG_LIST(), \
 132         HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
 133         HWSEQ_PHYPLL_REG_LIST(CRTC), \
 134         SR(DCHUB_FB_LOCATION),\
 135         SR(DCHUB_AGP_BASE),\
 136         SR(DCHUB_AGP_BOT),\
 137         SR(DCHUB_AGP_TOP), \
 138         BL_REG_LIST()
 139
 140 #define HWSEQ_VG20_REG_LIST() \
 141         HWSEQ_DCE120_REG_LIST(),\
 142         MMHUB_SR(MC_VM_XGMI_LFB_CNTL)
 143
 144 #define HWSEQ_DCE112_REG_LIST() \
 145         HWSEQ_DCE10_REG_LIST(), \
 146         HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
 147         HWSEQ_PHYPLL_REG_LIST(CRTC), \
 148         BL_REG_LIST()
 149
 150 #define HWSEQ_DCN_REG_LIST()\
 151         SR(REFCLK_CNTL), \
 152         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 153         SR(DIO_MEM_PWR_CTRL), \
 154         SR(DCCG_GATE_DISABLE_CNTL), \
 155         SR(DCCG_GATE_DISABLE_CNTL2), \
 156         SR(DCFCLK_CNTL),\
 157         SR(DCFCLK_CNTL), \
 158         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
 159
 160
 161 #define MMHUB_DCN_REG_LIST()\
 162         /* todo:  get these from GVM instead of reading registers ourselves */\
 163         MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
 164         MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
 165         MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
 166         MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
 167         MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
 168         MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
 169         MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
 170         MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
 171         MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
 172         MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
 173         MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
 174         MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
 175
 176
 177 #define HWSEQ_DCN1_REG_LIST()\
 178         HWSEQ_DCN_REG_LIST(), \
 179         MMHUB_DCN_REG_LIST(), \
 180         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
 181         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
 182         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
 183         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
 184         SR(DCHUBBUB_SDPIF_FB_BASE),\
 185         SR(DCHUBBUB_SDPIF_FB_OFFSET),\
 186         SR(DCHUBBUB_SDPIF_AGP_BASE),\
 187         SR(DCHUBBUB_SDPIF_AGP_BOT),\
 188         SR(DCHUBBUB_SDPIF_AGP_TOP),\
 189         SR(DOMAIN0_PG_CONFIG), \
 190         SR(DOMAIN1_PG_CONFIG), \
 191         SR(DOMAIN2_PG_CONFIG), \
 192         SR(DOMAIN3_PG_CONFIG), \
 193         SR(DOMAIN4_PG_CONFIG), \
 194         SR(DOMAIN5_PG_CONFIG), \
 195         SR(DOMAIN6_PG_CONFIG), \
 196         SR(DOMAIN7_PG_CONFIG), \
 197         SR(DOMAIN0_PG_STATUS), \
 198         SR(DOMAIN1_PG_STATUS), \
 199         SR(DOMAIN2_PG_STATUS), \
 200         SR(DOMAIN3_PG_STATUS), \
 201         SR(DOMAIN4_PG_STATUS), \
 202         SR(DOMAIN5_PG_STATUS), \
 203         SR(DOMAIN6_PG_STATUS), \
 204         SR(DOMAIN7_PG_STATUS), \
 205         SR(D1VGA_CONTROL), \
 206         SR(D2VGA_CONTROL), \
 207         SR(D3VGA_CONTROL), \
 208         SR(D4VGA_CONTROL), \
 209         SR(VGA_TEST_CONTROL), \
 210         SR(DC_IP_REQUEST_CNTL), \
 211         BL_REG_LIST()
 212
 213 #define HWSEQ_DCN2_REG_LIST()\
 214         HWSEQ_DCN_REG_LIST(), \
 215         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
 216         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
 217         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
 218         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
 219         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
 220         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \
 221         SR(MICROSECOND_TIME_BASE_DIV), \
 222         SR(MILLISECOND_TIME_BASE_DIV), \
 223         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 224         SR(RBBMIF_TIMEOUT_DIS), \
 225         SR(RBBMIF_TIMEOUT_DIS_2), \
 226         SR(DCHUBBUB_CRC_CTRL), \
 227         SR(DPP_TOP0_DPP_CRC_CTRL), \
 228         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 229         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 230         SR(MPC_CRC_CTRL), \
 231         SR(MPC_CRC_RESULT_GB), \
 232         SR(MPC_CRC_RESULT_C), \
 233         SR(MPC_CRC_RESULT_AR), \
 234         SR(DOMAIN0_PG_CONFIG), \
 235         SR(DOMAIN1_PG_CONFIG), \
 236         SR(DOMAIN2_PG_CONFIG), \
 237         SR(DOMAIN3_PG_CONFIG), \
 238         SR(DOMAIN4_PG_CONFIG), \
 239         SR(DOMAIN5_PG_CONFIG), \
 240         SR(DOMAIN6_PG_CONFIG), \
 241         SR(DOMAIN7_PG_CONFIG), \
 242         SR(DOMAIN8_PG_CONFIG), \
 243         SR(DOMAIN9_PG_CONFIG), \
 244 /*      SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\
 245 /*      SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\
 246         SR(DOMAIN16_PG_CONFIG), \
 247         SR(DOMAIN17_PG_CONFIG), \
 248         SR(DOMAIN18_PG_CONFIG), \
 249         SR(DOMAIN19_PG_CONFIG), \
 250         SR(DOMAIN20_PG_CONFIG), \
 251         SR(DOMAIN21_PG_CONFIG), \
 252         SR(DOMAIN0_PG_STATUS), \
 253         SR(DOMAIN1_PG_STATUS), \
 254         SR(DOMAIN2_PG_STATUS), \
 255         SR(DOMAIN3_PG_STATUS), \
 256         SR(DOMAIN4_PG_STATUS), \
 257         SR(DOMAIN5_PG_STATUS), \
 258         SR(DOMAIN6_PG_STATUS), \
 259         SR(DOMAIN7_PG_STATUS), \
 260         SR(DOMAIN8_PG_STATUS), \
 261         SR(DOMAIN9_PG_STATUS), \
 262         SR(DOMAIN10_PG_STATUS), \
 263         SR(DOMAIN11_PG_STATUS), \
 264         SR(DOMAIN16_PG_STATUS), \
 265         SR(DOMAIN17_PG_STATUS), \
 266         SR(DOMAIN18_PG_STATUS), \
 267         SR(DOMAIN19_PG_STATUS), \
 268         SR(DOMAIN20_PG_STATUS), \
 269         SR(DOMAIN21_PG_STATUS), \
 270         SR(D1VGA_CONTROL), \
 271         SR(D2VGA_CONTROL), \
 272         SR(D3VGA_CONTROL), \
 273         SR(D4VGA_CONTROL), \
 274         SR(D5VGA_CONTROL), \
 275         SR(D6VGA_CONTROL), \
 276         SR(DC_IP_REQUEST_CNTL), \
 277         BL_REG_LIST()
 278
 279 #define HWSEQ_DCN21_REG_LIST()\
 280         HWSEQ_DCN_REG_LIST(), \
 281         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
 282         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
 283         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
 284         HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
 285         MMHUB_DCN_REG_LIST(), \
 286         SR(MICROSECOND_TIME_BASE_DIV), \
 287         SR(MILLISECOND_TIME_BASE_DIV), \
 288         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 289         SR(RBBMIF_TIMEOUT_DIS), \
 290         SR(RBBMIF_TIMEOUT_DIS_2), \
 291         SR(DCHUBBUB_CRC_CTRL), \
 292         SR(DPP_TOP0_DPP_CRC_CTRL), \
 293         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 294         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 295         SR(MPC_CRC_CTRL), \
 296         SR(MPC_CRC_RESULT_GB), \
 297         SR(MPC_CRC_RESULT_C), \
 298         SR(MPC_CRC_RESULT_AR), \
 299         SR(DOMAIN0_PG_CONFIG), \
 300         SR(DOMAIN1_PG_CONFIG), \
 301         SR(DOMAIN2_PG_CONFIG), \
 302         SR(DOMAIN3_PG_CONFIG), \
 303         SR(DOMAIN4_PG_CONFIG), \
 304         SR(DOMAIN5_PG_CONFIG), \
 305         SR(DOMAIN6_PG_CONFIG), \
 306         SR(DOMAIN7_PG_CONFIG), \
 307         SR(DOMAIN16_PG_CONFIG), \
 308         SR(DOMAIN17_PG_CONFIG), \
 309         SR(DOMAIN18_PG_CONFIG), \
 310         SR(DOMAIN0_PG_STATUS), \
 311         SR(DOMAIN1_PG_STATUS), \
 312         SR(DOMAIN2_PG_STATUS), \
 313         SR(DOMAIN3_PG_STATUS), \
 314         SR(DOMAIN4_PG_STATUS), \
 315         SR(DOMAIN5_PG_STATUS), \
 316         SR(DOMAIN6_PG_STATUS), \
 317         SR(DOMAIN7_PG_STATUS), \
 318         SR(DOMAIN16_PG_STATUS), \
 319         SR(DOMAIN17_PG_STATUS), \
 320         SR(DOMAIN18_PG_STATUS), \
 321         SR(D1VGA_CONTROL), \
 322         SR(D2VGA_CONTROL), \
 323         SR(D3VGA_CONTROL), \
 324         SR(D4VGA_CONTROL), \
 325         SR(D5VGA_CONTROL), \
 326         SR(D6VGA_CONTROL), \
 327         SR(DC_IP_REQUEST_CNTL), \
 328         BL_REG_LIST()
 329
 330 struct dce_hwseq_registers {
 331
 332                 /* Backlight registers */
 333         uint32_t LVTMA_PWRSEQ_CNTL;
 334         uint32_t LVTMA_PWRSEQ_STATE;
 335
 336         uint32_t DCFE_CLOCK_CONTROL[6];
 337         uint32_t DCFEV_CLOCK_CONTROL;
 338         uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
 339         uint32_t BLND_V_UPDATE_LOCK[6];
 340         uint32_t BLND_CONTROL[6];
 341         uint32_t BLNDV_CONTROL;
 342         uint32_t CRTC_H_BLANK_START_END[6];
 343         uint32_t PIXEL_RATE_CNTL[6];
 344         uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
 345         /*DCHUB*/
 346         uint32_t DCHUB_FB_LOCATION;
 347         uint32_t DCHUB_AGP_BASE;
 348         uint32_t DCHUB_AGP_BOT;
 349         uint32_t DCHUB_AGP_TOP;
 350
 351         uint32_t REFCLK_CNTL;
 352
 353         uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
 354         uint32_t DCHUBBUB_SDPIF_FB_BASE;
 355         uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
 356         uint32_t DCHUBBUB_SDPIF_AGP_BASE;
 357         uint32_t DCHUBBUB_SDPIF_AGP_BOT;
 358         uint32_t DCHUBBUB_SDPIF_AGP_TOP;
 359         uint32_t DC_IP_REQUEST_CNTL;
 360         uint32_t DOMAIN0_PG_CONFIG;
 361         uint32_t DOMAIN1_PG_CONFIG;
 362         uint32_t DOMAIN2_PG_CONFIG;
 363         uint32_t DOMAIN3_PG_CONFIG;
 364         uint32_t DOMAIN4_PG_CONFIG;
 365         uint32_t DOMAIN5_PG_CONFIG;
 366         uint32_t DOMAIN6_PG_CONFIG;
 367         uint32_t DOMAIN7_PG_CONFIG;
 368         uint32_t DOMAIN8_PG_CONFIG;
 369         uint32_t DOMAIN9_PG_CONFIG;
 370         uint32_t DOMAIN10_PG_CONFIG;
 371         uint32_t DOMAIN11_PG_CONFIG;
 372         uint32_t DOMAIN16_PG_CONFIG;
 373         uint32_t DOMAIN17_PG_CONFIG;
 374         uint32_t DOMAIN18_PG_CONFIG;
 375         uint32_t DOMAIN19_PG_CONFIG;
 376         uint32_t DOMAIN20_PG_CONFIG;
 377         uint32_t DOMAIN21_PG_CONFIG;
 378         uint32_t DOMAIN0_PG_STATUS;
 379         uint32_t DOMAIN1_PG_STATUS;
 380         uint32_t DOMAIN2_PG_STATUS;
 381         uint32_t DOMAIN3_PG_STATUS;
 382         uint32_t DOMAIN4_PG_STATUS;
 383         uint32_t DOMAIN5_PG_STATUS;
 384         uint32_t DOMAIN6_PG_STATUS;
 385         uint32_t DOMAIN7_PG_STATUS;
 386         uint32_t DOMAIN8_PG_STATUS;
 387         uint32_t DOMAIN9_PG_STATUS;
 388         uint32_t DOMAIN10_PG_STATUS;
 389         uint32_t DOMAIN11_PG_STATUS;
 390         uint32_t DOMAIN16_PG_STATUS;
 391         uint32_t DOMAIN17_PG_STATUS;
 392         uint32_t DOMAIN18_PG_STATUS;
 393         uint32_t DOMAIN19_PG_STATUS;
 394         uint32_t DOMAIN20_PG_STATUS;
 395         uint32_t DOMAIN21_PG_STATUS;
 396         uint32_t DIO_MEM_PWR_CTRL;
 397         uint32_t DCCG_GATE_DISABLE_CNTL;
 398         uint32_t DCCG_GATE_DISABLE_CNTL2;
 399         uint32_t DCFCLK_CNTL;
 400         uint32_t MICROSECOND_TIME_BASE_DIV;
 401         uint32_t MILLISECOND_TIME_BASE_DIV;
 402         uint32_t DISPCLK_FREQ_CHANGE_CNTL;
 403         uint32_t RBBMIF_TIMEOUT_DIS;
 404         uint32_t RBBMIF_TIMEOUT_DIS_2;
 405         uint32_t DCHUBBUB_CRC_CTRL;
 406         uint32_t DPP_TOP0_DPP_CRC_CTRL;
 407         uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;
 408         uint32_t DPP_TOP0_DPP_CRC_VAL_B_A;
 409         uint32_t MPC_CRC_CTRL;
 410         uint32_t MPC_CRC_RESULT_GB;
 411         uint32_t MPC_CRC_RESULT_C;
 412         uint32_t MPC_CRC_RESULT_AR;
 413         uint32_t D1VGA_CONTROL;
 414         uint32_t D2VGA_CONTROL;
 415         uint32_t D3VGA_CONTROL;
 416         uint32_t D4VGA_CONTROL;
 417         uint32_t D5VGA_CONTROL;
 418         uint32_t D6VGA_CONTROL;
 419         uint32_t VGA_TEST_CONTROL;
 420         /* MMHUB registers. read only. temporary hack */
 421         uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
 422         uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 423         uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32;
 424         uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32;
 425         uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32;
 426         uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32;
 427         uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32;
 428         uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32;
 429         uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
 430         uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
 431         uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;
 432         uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;
 433         uint32_t MC_VM_XGMI_LFB_CNTL;
 434         uint32_t AZALIA_AUDIO_DTO;
 435         uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
 436 };
 437  /* set field name */
 438 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
 439         .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
 440
 441 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\
 442         .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix
 443
 444
 445 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
 446         HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
 447         SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
 448
 449 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
 450         HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
 451         HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
 452         HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
 453         HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\
 454         HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\
 455         HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\
 456         HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\
 457         HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
 458         HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
 459
 460 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\
 461         HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
 462         HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
 463
 464 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\
 465         HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
 466         HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
 467
 468 #define HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)\
 469         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
 470         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
 471         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
 472         HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
 473
 474 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
 475         .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
 476         HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
 477         HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
 478         HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
 479         HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
 480         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
 481         HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
 482
 483 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
 484         HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
 485         HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
 486         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
 487         HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
 488
 489 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
 490         HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
 491         SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
 492         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
 493
 494 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
 495         HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
 496         HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
 497
 498 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
 499         SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
 500         SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
 501         SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
 502         SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
 503         SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
 504
 505 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
 506         HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
 507         HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
 508         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
 509         HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
 510         HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh),\
 511         HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
 512
 513 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\
 514         HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\
 515         HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\
 516         HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh)
 517
 518 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
 519         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
 520         HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
 521         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
 522         HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \
 523         HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
 524
 525 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
 526         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 527         HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \
 528         HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
 529         HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
 530         HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
 531         HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
 532         HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \
 533         /* todo:  get these from GVM instead of reading registers ourselves */\
 534         HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
 535         HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
 536         HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
 537         HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
 538         HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\
 539         HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\
 540         HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\
 541         HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\
 542         HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\
 543         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
 544         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
 545         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
 546         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
 547         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
 548         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
 549         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
 550         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
 551         HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
 552         HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
 553         HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
 554         HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
 555         HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
 556         HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
 557         HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
 558         HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
 559         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
 560         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
 561         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
 562         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
 563         HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
 564         HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
 565         HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
 566         HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
 567         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 568         HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
 569         HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\
 570         HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
 571         HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
 572         HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
 573         HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
 574         HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
 575
 576 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
 577         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 578         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 579         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
 580         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
 581         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
 582         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
 583         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
 584         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
 585         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
 586         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
 587         HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
 588         HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
 589         HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
 590         HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
 591         HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
 592         HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
 593         HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
 594         HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
 595         HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \
 596         HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \
 597         HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \
 598         HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \
 599         HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \
 600         HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \
 601         HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \
 602         HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \
 603         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
 604         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
 605         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
 606         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
 607         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
 608         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
 609         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \
 610         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \
 611         HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \
 612         HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \
 613         HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \
 614         HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \
 615         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
 616         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
 617         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
 618         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
 619         HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
 620         HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
 621         HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
 622         HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
 623         HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \
 624         HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \
 625         HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \
 626         HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \
 627         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
 628         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
 629         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
 630         HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \
 631         HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \
 632         HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \
 633         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 634         HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
 635
 636 #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\
 637         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 638         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 639         HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
 640         HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
 641         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
 642         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
 643         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
 644         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
 645         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
 646         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
 647         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
 648         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
 649         HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
 650         HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
 651         HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
 652         HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
 653         HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
 654         HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
 655         HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
 656         HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
 657         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
 658         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
 659         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
 660         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
 661         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
 662         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
 663         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
 664         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
 665         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
 666         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
 667         HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
 668         HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
 669         HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
 670         HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
 671         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
 672         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
 673         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
 674         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 675         HWSEQ_LVTMA_MASK_SH_LIST(mask_sh), \
 676         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
 677         HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
 678
 679 #define HWSEQ_REG_FIELD_LIST(type) \
 680         type DCFE_CLOCK_ENABLE; \
 681         type DCFEV_CLOCK_ENABLE; \
 682         type DC_MEM_GLOBAL_PWR_REQ_DIS; \
 683         type BLND_DCP_GRPH_V_UPDATE_LOCK; \
 684         type BLND_SCL_V_UPDATE_LOCK; \
 685         type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
 686         type BLND_BLND_V_UPDATE_LOCK; \
 687         type BLND_V_UPDATE_LOCK_MODE; \
 688         type BLND_FEEDTHROUGH_EN; \
 689         type BLND_ALPHA_MODE; \
 690         type BLND_MODE; \
 691         type BLND_MULTIPLIED_MODE; \
 692         type DP_DTO0_ENABLE; \
 693         type PIXEL_RATE_SOURCE; \
 694         type PHYPLL_PIXEL_RATE_SOURCE; \
 695         type PIXEL_RATE_PLL_SOURCE; \
 696         /* todo:  get these from GVM instead of reading registers ourselves */\
 697         type PAGE_DIRECTORY_ENTRY_HI32;\
 698         type PAGE_DIRECTORY_ENTRY_LO32;\
 699         type LOGICAL_PAGE_NUMBER_HI4;\
 700         type LOGICAL_PAGE_NUMBER_LO32;\
 701         type PHYSICAL_PAGE_ADDR_HI4;\
 702         type PHYSICAL_PAGE_ADDR_LO32;\
 703         type PHYSICAL_PAGE_NUMBER_MSB;\
 704         type PHYSICAL_PAGE_NUMBER_LSB;\
 705         type LOGICAL_ADDR; \
 706         type PF_LFB_REGION;\
 707         type PF_MAX_REGION;\
 708         type ENABLE_L1_TLB;\
 709         type SYSTEM_ACCESS_MODE;\
 710         type LVTMA_BLON;\
 711         type LVTMA_DIGON;\
 712         type LVTMA_DIGON_OVRD;\
 713         type LVTMA_PWRSEQ_TARGET_STATE_R;
 714
 715 #define HWSEQ_DCN_REG_FIELD_LIST(type) \
 716         type HUBP_VTG_SEL; \
 717         type HUBP_CLOCK_ENABLE; \
 718         type DPP_CLOCK_ENABLE; \
 719         type SDPIF_FB_BASE;\
 720         type SDPIF_FB_OFFSET;\
 721         type SDPIF_AGP_BASE;\
 722         type SDPIF_AGP_BOT;\
 723         type SDPIF_AGP_TOP;\
 724         type FB_TOP;\
 725         type FB_BASE;\
 726         type FB_OFFSET;\
 727         type AGP_BASE;\
 728         type AGP_BOT;\
 729         type AGP_TOP;\
 730         type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
 731         type OPP_PIPE_CLOCK_EN;\
 732         type IP_REQUEST_EN; \
 733         type DOMAIN0_POWER_FORCEON; \
 734         type DOMAIN0_POWER_GATE; \
 735         type DOMAIN1_POWER_FORCEON; \
 736         type DOMAIN1_POWER_GATE; \
 737         type DOMAIN2_POWER_FORCEON; \
 738         type DOMAIN2_POWER_GATE; \
 739         type DOMAIN3_POWER_FORCEON; \
 740         type DOMAIN3_POWER_GATE; \
 741         type DOMAIN4_POWER_FORCEON; \
 742         type DOMAIN4_POWER_GATE; \
 743         type DOMAIN5_POWER_FORCEON; \
 744         type DOMAIN5_POWER_GATE; \
 745         type DOMAIN6_POWER_FORCEON; \
 746         type DOMAIN6_POWER_GATE; \
 747         type DOMAIN7_POWER_FORCEON; \
 748         type DOMAIN7_POWER_GATE; \
 749         type DOMAIN8_POWER_FORCEON; \
 750         type DOMAIN8_POWER_GATE; \
 751         type DOMAIN9_POWER_FORCEON; \
 752         type DOMAIN9_POWER_GATE; \
 753         type DOMAIN10_POWER_FORCEON; \
 754         type DOMAIN10_POWER_GATE; \
 755         type DOMAIN11_POWER_FORCEON; \
 756         type DOMAIN11_POWER_GATE; \
 757         type DOMAIN16_POWER_FORCEON; \
 758         type DOMAIN16_POWER_GATE; \
 759         type DOMAIN17_POWER_FORCEON; \
 760         type DOMAIN17_POWER_GATE; \
 761         type DOMAIN18_POWER_FORCEON; \
 762         type DOMAIN18_POWER_GATE; \
 763         type DOMAIN19_POWER_FORCEON; \
 764         type DOMAIN19_POWER_GATE; \
 765         type DOMAIN20_POWER_FORCEON; \
 766         type DOMAIN20_POWER_GATE; \
 767         type DOMAIN21_POWER_FORCEON; \
 768         type DOMAIN21_POWER_GATE; \
 769         type DOMAIN0_PGFSM_PWR_STATUS; \
 770         type DOMAIN1_PGFSM_PWR_STATUS; \
 771         type DOMAIN2_PGFSM_PWR_STATUS; \
 772         type DOMAIN3_PGFSM_PWR_STATUS; \
 773         type DOMAIN4_PGFSM_PWR_STATUS; \
 774         type DOMAIN5_PGFSM_PWR_STATUS; \
 775         type DOMAIN6_PGFSM_PWR_STATUS; \
 776         type DOMAIN7_PGFSM_PWR_STATUS; \
 777         type DOMAIN8_PGFSM_PWR_STATUS; \
 778         type DOMAIN9_PGFSM_PWR_STATUS; \
 779         type DOMAIN10_PGFSM_PWR_STATUS; \
 780         type DOMAIN11_PGFSM_PWR_STATUS; \
 781         type DOMAIN16_PGFSM_PWR_STATUS; \
 782         type DOMAIN17_PGFSM_PWR_STATUS; \
 783         type DOMAIN18_PGFSM_PWR_STATUS; \
 784         type DOMAIN19_PGFSM_PWR_STATUS; \
 785         type DOMAIN20_PGFSM_PWR_STATUS; \
 786         type DOMAIN21_PGFSM_PWR_STATUS; \
 787         type DCFCLK_GATE_DIS; \
 788         type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
 789         type VGA_TEST_ENABLE; \
 790         type VGA_TEST_RENDER_START; \
 791         type D1VGA_MODE_ENABLE; \
 792         type D2VGA_MODE_ENABLE; \
 793         type D3VGA_MODE_ENABLE; \
 794         type D4VGA_MODE_ENABLE; \
 795         type AZALIA_AUDIO_DTO_MODULE;
 796
 797 struct dce_hwseq_shift {
 798         HWSEQ_REG_FIELD_LIST(uint8_t)
 799         HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
 800 };
 801
 802 struct dce_hwseq_mask {
 803         HWSEQ_REG_FIELD_LIST(uint32_t)
 804         HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
 805 };
 806
 807
 808 enum blnd_mode {
 809         BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
 810         BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
 811         BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
 812 };
 813
 814 struct dce_hwseq;
 815 struct pipe_ctx;
 816 struct clock_source;
 817
 818 void dce_enable_fe_clock(struct dce_hwseq *hwss,
 819                 unsigned int inst, bool enable);
 820
 821 void dce_pipe_control_lock(struct dc *dc,
 822                 struct pipe_ctx *pipe,
 823                 bool lock);
 824
 825 void dce_set_blender_mode(struct dce_hwseq *hws,
 826         unsigned int blnd_inst, enum blnd_mode mode);
 827
 828 void dce_clock_gating_power_up(struct dce_hwseq *hws,
 829                 bool enable);
 830
 831 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
 832                 struct clock_source *clk_src,
 833                 unsigned int tg_inst);
 834
 835 bool dce_use_lut(enum surface_pixel_format format);
 836 #endif   /*__DCE_HWSEQ_H__*/