drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dmub_psr.h"
  27 #include "dc.h"
  28 #include "dc_dmub_srv.h"
  29 #include "../../dmub/inc/dmub_srv.h"
  30 #include "dmub_fw_state.h"
  31 #include "core_types.h"
  32 #include "ipp.h"
  33
  34 #define MAX_PIPES 6
  35
  36 /**
  37  * Get PSR state from firmware.
  38  */
  39 static void dmub_get_psr_state(uint32_t *psr_state)
  40 {
  41         // Not yet implemented
  42         // Trigger GPINT interrupt from firmware
  43 }
  44
  45 /**
  46  * Enable/Disable PSR.
  47  */
  48 static void dmub_set_psr_enable(struct dmub_psr *dmub, bool enable)
  49 {
  50         union dmub_rb_cmd cmd;
  51         struct dc_context *dc = dmub->ctx;
  52
  53         cmd.psr_enable.header.type = DMUB_CMD__PSR;
  54
  55         if (enable)
  56                 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE;
  57         else
  58                 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_DISABLE;
  59
  60         cmd.psr_enable.header.payload_bytes = 0; // Send header only
  61
  62         dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_enable.header);
  63         dc_dmub_srv_cmd_execute(dc->dmub_srv);
  64         dc_dmub_srv_wait_idle(dc->dmub_srv);
  65 }
  66
  67 /**
  68  * Set PSR level.
  69  */
  70 static void dmub_set_psr_level(struct dmub_psr *dmub, uint16_t psr_level)
  71 {
  72         union dmub_rb_cmd cmd;
  73         uint32_t psr_state = 0;
  74         struct dc_context *dc = dmub->ctx;
  75
  76         dmub_get_psr_state(&psr_state);
  77
  78         if (psr_state == 0)
  79                 return;
  80
  81         cmd.psr_set_level.header.type = DMUB_CMD__PSR;
  82         cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL;
  83         cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data);
  84         cmd.psr_set_level.psr_set_level_data.psr_level = psr_level;
  85
  86         dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_set_level.header);
  87         dc_dmub_srv_cmd_execute(dc->dmub_srv);
  88         dc_dmub_srv_wait_idle(dc->dmub_srv);
  89 }
  90
  91 /**
  92  * Setup PSR by programming phy registers and sending psr hw context values to firmware.
  93  */
  94 static bool dmub_setup_psr(struct dmub_psr *dmub,
  95                 struct dc_link *link,
  96                 struct psr_context *psr_context)
  97 {
  98         union dmub_rb_cmd cmd;
  99         struct dc_context *dc = dmub->ctx;
 100         struct dmub_cmd_psr_copy_settings_data *copy_settings_data
 101                 = &cmd.psr_copy_settings.psr_copy_settings_data;
 102         struct pipe_ctx *pipe_ctx = NULL;
 103         struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
 104
 105         for (int i = 0; i < MAX_PIPES; i++) {
 106                 if (res_ctx &&
 107                                 res_ctx->pipe_ctx[i].stream &&
 108                                 res_ctx->pipe_ctx[i].stream->link &&
 109                                 res_ctx->pipe_ctx[i].stream->link == link &&
 110                                 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
 111                         pipe_ctx = &res_ctx->pipe_ctx[i];
 112                         break;
 113                 }
 114         }
 115
 116         if (!pipe_ctx ||
 117                         !&pipe_ctx->plane_res ||
 118                         !&pipe_ctx->stream_res)
 119                 return false;
 120
 121         // Program DP DPHY fast training registers
 122         link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
 123                         psr_context->psrExitLinkTrainingRequired);
 124
 125         // Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high
 126         link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
 127                         psr_context->sdpTransmitLineNumDeadline);
 128
 129         cmd.psr_copy_settings.header.type = DMUB_CMD__PSR;
 130         cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS;
 131         cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data);
 132
 133         // Hw insts
 134         copy_settings_data->dpphy_inst                          = psr_context->phyType;
 135         copy_settings_data->aux_inst                            = psr_context->channel;
 136         copy_settings_data->digfe_inst                          = psr_context->engineId;
 137         copy_settings_data->digbe_inst                          = psr_context->transmitterId;
 138
 139         copy_settings_data->mpcc_inst                           = pipe_ctx->plane_res.mpcc_inst;
 140
 141         if (pipe_ctx->plane_res.hubp)
 142                 copy_settings_data->hubp_inst                   = pipe_ctx->plane_res.hubp->inst;
 143         else
 144                 copy_settings_data->hubp_inst                   = 0;
 145         if (pipe_ctx->plane_res.dpp)
 146                 copy_settings_data->dpp_inst                    = pipe_ctx->plane_res.dpp->inst;
 147         else
 148                 copy_settings_data->dpp_inst                    = 0;
 149         if (pipe_ctx->stream_res.opp)
 150                 copy_settings_data->opp_inst                    = pipe_ctx->stream_res.opp->inst;
 151         else
 152                 copy_settings_data->opp_inst                    = 0;
 153         if (pipe_ctx->stream_res.tg)
 154                 copy_settings_data->otg_inst                    = pipe_ctx->stream_res.tg->inst;
 155         else
 156                 copy_settings_data->otg_inst                    = 0;
 157
 158         // Misc
 159         copy_settings_data->psr_level                           = psr_context->psr_level.u32all;
 160         copy_settings_data->hyst_frames                         = psr_context->timehyst_frames;
 161         copy_settings_data->hyst_lines                          = psr_context->hyst_lines;
 162         copy_settings_data->phy_type                            = psr_context->phyType;
 163         copy_settings_data->aux_repeat                          = psr_context->aux_repeats;
 164         copy_settings_data->smu_optimizations_en        = psr_context->allow_smu_optimizations;
 165         copy_settings_data->skip_wait_for_pll_lock      = psr_context->skipPsrWaitForPllLock;
 166         copy_settings_data->frame_delay                         = psr_context->frame_delay;
 167         copy_settings_data->smu_phy_id                          = psr_context->smuPhyId;
 168         copy_settings_data->num_of_controllers          = psr_context->numberOfControllers;
 169         copy_settings_data->frame_cap_ind                       = psr_context->psrFrameCaptureIndicationReq;
 170         copy_settings_data->phy_num                                     = psr_context->frame_delay & 0x7;
 171         copy_settings_data->link_rate                           = psr_context->frame_delay & 0xF;
 172
 173         dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_copy_settings.header);
 174         dc_dmub_srv_cmd_execute(dc->dmub_srv);
 175         dc_dmub_srv_wait_idle(dc->dmub_srv);
 176
 177         return true;
 178 }
 179
 180 static const struct dmub_psr_funcs psr_funcs = {
 181         .set_psr_enable                 = dmub_set_psr_enable,
 182         .setup_psr                              = dmub_setup_psr,
 183         .get_psr_state                  = dmub_get_psr_state,
 184         .set_psr_level                  = dmub_set_psr_level,
 185 };
 186
 187 /**
 188  * Construct PSR object.
 189  */
 190 static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
 191 {
 192         psr->ctx = ctx;
 193         psr->funcs = &psr_funcs;
 194 }
 195
 196 /**
 197  * Allocate and initialize PSR object.
 198  */
 199 struct dmub_psr *dmub_psr_create(struct dc_context *ctx)
 200 {
 201         struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL);
 202
 203         if (psr == NULL) {
 204                 BREAK_TO_DEBUGGER();
 205                 return NULL;
 206         }
 207
 208         dmub_psr_construct(psr, ctx);
 209
 210         return psr;
 211 }
 212
 213 /**
 214  * Deallocate PSR object.
 215  */
 216 void dmub_psr_destroy(struct dmub_psr **dmub)
 217 {
 218         kfree(dmub);
 219         *dmub = NULL;
 220 }