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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / display / dc / dce112 / dce112_resource.c
blob700ad8b3e54b2910b16905cd46d0d8b0fe2f7391
1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30 #include "link_encoder.h"
31 #include "stream_encoder.h"
32
33 #include "resource.h"
34 #include "include/irq_service_interface.h"
35 #include "dce110/dce110_resource.h"
36 #include "dce110/dce110_timing_generator.h"
37
38 #include "irq/dce110/irq_service_dce110.h"
39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_transform.h"
41 #include "dce/dce_link_encoder.h"
42 #include "dce/dce_stream_encoder.h"
43 #include "dce/dce_audio.h"
44 #include "dce/dce_opp.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_clock_source.h"
47
48 #include "dce/dce_hwseq.h"
49 #include "dce112/dce112_hw_sequencer.h"
50 #include "dce/dce_abm.h"
51 #include "dce/dce_dmcu.h"
52 #include "dce/dce_aux.h"
53 #include "dce/dce_i2c.h"
54
55 #include "reg_helper.h"
56
57 #include "dce/dce_11_2_d.h"
58 #include "dce/dce_11_2_sh_mask.h"
59
60 #include "dce100/dce100_resource.h"
61 #define DC_LOGGER \
62 dc->ctx->logger
63
64 #ifndef mmDP_DPHY_INTERNAL_CTRL
65 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
66 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
67 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
68 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
69 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
70 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
71 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
72 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
73 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
74 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
75 #endif
76
77 #ifndef mmBIOS_SCRATCH_2
78 #define mmBIOS_SCRATCH_2 0x05CB
79 #define mmBIOS_SCRATCH_3 0x05CC
80 #define mmBIOS_SCRATCH_6 0x05CF
81 #endif
82
83 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
84 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
85 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
86 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
87 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
88 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
89 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
90 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
91 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
92 #endif
93
94 #ifndef mmDP_DPHY_FAST_TRAINING
95 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
96 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
97 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
98 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
99 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
100 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
101 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
102 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
103 #endif
104
105 enum dce112_clk_src_array_id {
106 DCE112_CLK_SRC_PLL0,
107 DCE112_CLK_SRC_PLL1,
108 DCE112_CLK_SRC_PLL2,
109 DCE112_CLK_SRC_PLL3,
110 DCE112_CLK_SRC_PLL4,
111 DCE112_CLK_SRC_PLL5,
112
113 DCE112_CLK_SRC_TOTAL
114 };
115
116 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
117 {
118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
120 },
121 {
122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
124 },
125 {
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
128 },
129 {
130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
132 },
133 {
134 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
135 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
136 },
137 {
138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
139 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
140 }
141 };
142
143 /* set register offset */
144 #define SR(reg_name)\
145 .reg_name = mm ## reg_name
146
147 /* set register offset with instance */
148 #define SRI(reg_name, block, id)\
149 .reg_name = mm ## block ## id ## _ ## reg_name
150
151 static const struct dce_dmcu_registers dmcu_regs = {
152 DMCU_DCE110_COMMON_REG_LIST()
153 };
154
155 static const struct dce_dmcu_shift dmcu_shift = {
156 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
157 };
158
159 static const struct dce_dmcu_mask dmcu_mask = {
160 DMCU_MASK_SH_LIST_DCE110(_MASK)
161 };
162
163 static const struct dce_abm_registers abm_regs = {
164 ABM_DCE110_COMMON_REG_LIST()
165 };
166
167 static const struct dce_abm_shift abm_shift = {
168 ABM_MASK_SH_LIST_DCE110(__SHIFT)
169 };
170
171 static const struct dce_abm_mask abm_mask = {
172 ABM_MASK_SH_LIST_DCE110(_MASK)
173 };
174
175 static const struct dce110_aux_registers_shift aux_shift = {
176 DCE_AUX_MASK_SH_LIST(__SHIFT)
177 };
178
179 static const struct dce110_aux_registers_mask aux_mask = {
180 DCE_AUX_MASK_SH_LIST(_MASK)
181 };
182
183 #define ipp_regs(id)\
184 [id] = {\
185 IPP_DCE110_REG_LIST_DCE_BASE(id)\
186 }
187
188 static const struct dce_ipp_registers ipp_regs[] = {
189 ipp_regs(0),
190 ipp_regs(1),
191 ipp_regs(2),
192 ipp_regs(3),
193 ipp_regs(4),
194 ipp_regs(5)
195 };
196
197 static const struct dce_ipp_shift ipp_shift = {
198 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
199 };
200
201 static const struct dce_ipp_mask ipp_mask = {
202 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
203 };
204
205 #define transform_regs(id)\
206 [id] = {\
207 XFM_COMMON_REG_LIST_DCE110(id)\
208 }
209
210 static const struct dce_transform_registers xfm_regs[] = {
211 transform_regs(0),
212 transform_regs(1),
213 transform_regs(2),
214 transform_regs(3),
215 transform_regs(4),
216 transform_regs(5)
217 };
218
219 static const struct dce_transform_shift xfm_shift = {
220 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
221 };
222
223 static const struct dce_transform_mask xfm_mask = {
224 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
225 };
226
227 #define aux_regs(id)\
228 [id] = {\
229 AUX_REG_LIST(id)\
230 }
231
232 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
233 aux_regs(0),
234 aux_regs(1),
235 aux_regs(2),
236 aux_regs(3),
237 aux_regs(4),
238 aux_regs(5)
239 };
240
241 #define hpd_regs(id)\
242 [id] = {\
243 HPD_REG_LIST(id)\
244 }
245
246 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
247 hpd_regs(0),
248 hpd_regs(1),
249 hpd_regs(2),
250 hpd_regs(3),
251 hpd_regs(4),
252 hpd_regs(5)
253 };
254
255 #define link_regs(id)\
256 [id] = {\
257 LE_DCE110_REG_LIST(id)\
258 }
259
260 static const struct dce110_link_enc_registers link_enc_regs[] = {
261 link_regs(0),
262 link_regs(1),
263 link_regs(2),
264 link_regs(3),
265 link_regs(4),
266 link_regs(5),
267 link_regs(6),
268 };
269
270 #define stream_enc_regs(id)\
271 [id] = {\
272 SE_COMMON_REG_LIST(id),\
273 .TMDS_CNTL = 0,\
274 }
275
276 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
277 stream_enc_regs(0),
278 stream_enc_regs(1),
279 stream_enc_regs(2),
280 stream_enc_regs(3),
281 stream_enc_regs(4),
282 stream_enc_regs(5)
283 };
284
285 static const struct dce_stream_encoder_shift se_shift = {
286 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
287 };
288
289 static const struct dce_stream_encoder_mask se_mask = {
290 SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
291 };
292
293 #define opp_regs(id)\
294 [id] = {\
295 OPP_DCE_112_REG_LIST(id),\
296 }
297
298 static const struct dce_opp_registers opp_regs[] = {
299 opp_regs(0),
300 opp_regs(1),
301 opp_regs(2),
302 opp_regs(3),
303 opp_regs(4),
304 opp_regs(5)
305 };
306
307 static const struct dce_opp_shift opp_shift = {
308 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
309 };
310
311 static const struct dce_opp_mask opp_mask = {
312 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
313 };
314
315 #define aux_engine_regs(id)\
316 [id] = {\
317 AUX_COMMON_REG_LIST(id), \
318 .AUX_RESET_MASK = 0 \
319 }
320
321 static const struct dce110_aux_registers aux_engine_regs[] = {
322 aux_engine_regs(0),
323 aux_engine_regs(1),
324 aux_engine_regs(2),
325 aux_engine_regs(3),
326 aux_engine_regs(4),
327 aux_engine_regs(5)
328 };
329
330 #define audio_regs(id)\
331 [id] = {\
332 AUD_COMMON_REG_LIST(id)\
333 }
334
335 static const struct dce_audio_registers audio_regs[] = {
336 audio_regs(0),
337 audio_regs(1),
338 audio_regs(2),
339 audio_regs(3),
340 audio_regs(4),
341 audio_regs(5)
342 };
343
344 static const struct dce_audio_shift audio_shift = {
345 AUD_COMMON_MASK_SH_LIST(__SHIFT)
346 };
347
348 static const struct dce_audio_mask audio_mask = {
349 AUD_COMMON_MASK_SH_LIST(_MASK)
350 };
351
352 #define clk_src_regs(index, id)\
353 [index] = {\
354 CS_COMMON_REG_LIST_DCE_112(id),\
355 }
356
357 static const struct dce110_clk_src_regs clk_src_regs[] = {
358 clk_src_regs(0, A),
359 clk_src_regs(1, B),
360 clk_src_regs(2, C),
361 clk_src_regs(3, D),
362 clk_src_regs(4, E),
363 clk_src_regs(5, F)
364 };
365
366 static const struct dce110_clk_src_shift cs_shift = {
367 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
368 };
369
370 static const struct dce110_clk_src_mask cs_mask = {
371 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
372 };
373
374 static const struct bios_registers bios_regs = {
375 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
376 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
377 };
378
379 static const struct resource_caps polaris_10_resource_cap = {
380 .num_timing_generator = 6,
381 .num_audio = 6,
382 .num_stream_encoder = 6,
383 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
384 .num_ddc = 6,
385 };
386
387 static const struct resource_caps polaris_11_resource_cap = {
388 .num_timing_generator = 5,
389 .num_audio = 5,
390 .num_stream_encoder = 5,
391 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
392 .num_ddc = 5,
393 };
394
395 static const struct dc_plane_cap plane_cap = {
396 .type = DC_PLANE_TYPE_DCE_RGB,
397
398 .pixel_format_support = {
399 .argb8888 = true,
400 .nv12 = false,
401 .fp16 = false
402 },
403
404 .max_upscale_factor = {
405 .argb8888 = 16000,
406 .nv12 = 1,
407 .fp16 = 1
408 },
409
410 .max_downscale_factor = {
411 .argb8888 = 250,
412 .nv12 = 1,
413 .fp16 = 1
414 }
415 };
416
417 #define CTX ctx
418 #define REG(reg) mm ## reg
419
420 #ifndef mmCC_DC_HDMI_STRAPS
421 #define mmCC_DC_HDMI_STRAPS 0x4819
422 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
423 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
424 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
425 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
426 #endif
427
428 static int map_transmitter_id_to_phy_instance(
429 enum transmitter transmitter)
430 {
431 switch (transmitter) {
432 case TRANSMITTER_UNIPHY_A:
433 return 0;
434 break;
435 case TRANSMITTER_UNIPHY_B:
436 return 1;
437 break;
438 case TRANSMITTER_UNIPHY_C:
439 return 2;
440 break;
441 case TRANSMITTER_UNIPHY_D:
442 return 3;
443 break;
444 case TRANSMITTER_UNIPHY_E:
445 return 4;
446 break;
447 case TRANSMITTER_UNIPHY_F:
448 return 5;
449 break;
450 case TRANSMITTER_UNIPHY_G:
451 return 6;
452 break;
453 default:
454 ASSERT(0);
455 return 0;
456 }
457 }
458
459 static void read_dce_straps(
460 struct dc_context *ctx,
461 struct resource_straps *straps)
462 {
463 REG_GET_2(CC_DC_HDMI_STRAPS,
464 HDMI_DISABLE, &straps->hdmi_disable,
465 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
466
467 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
468 }
469
470 static struct audio *create_audio(
471 struct dc_context *ctx, unsigned int inst)
472 {
473 return dce_audio_create(ctx, inst,
474 &audio_regs[inst], &audio_shift, &audio_mask);
475 }
476
477
478 static struct timing_generator *dce112_timing_generator_create(
479 struct dc_context *ctx,
480 uint32_t instance,
481 const struct dce110_timing_generator_offsets *offsets)
482 {
483 struct dce110_timing_generator *tg110 =
484 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
485
486 if (!tg110)
487 return NULL;
488
489 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
490 return &tg110->base;
491 }
492
493 static struct stream_encoder *dce112_stream_encoder_create(
494 enum engine_id eng_id,
495 struct dc_context *ctx)
496 {
497 struct dce110_stream_encoder *enc110 =
498 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
499
500 if (!enc110)
501 return NULL;
502
503 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
504 &stream_enc_regs[eng_id],
505 &se_shift, &se_mask);
506 return &enc110->base;
507 }
508
509 #define SRII(reg_name, block, id)\
510 .reg_name[id] = mm ## block ## id ## _ ## reg_name
511
512 static const struct dce_hwseq_registers hwseq_reg = {
513 HWSEQ_DCE112_REG_LIST()
514 };
515
516 static const struct dce_hwseq_shift hwseq_shift = {
517 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
518 };
519
520 static const struct dce_hwseq_mask hwseq_mask = {
521 HWSEQ_DCE112_MASK_SH_LIST(_MASK)
522 };
523
524 static struct dce_hwseq *dce112_hwseq_create(
525 struct dc_context *ctx)
526 {
527 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
528
529 if (hws) {
530 hws->ctx = ctx;
531 hws->regs = &hwseq_reg;
532 hws->shifts = &hwseq_shift;
533 hws->masks = &hwseq_mask;
534 }
535 return hws;
536 }
537
538 static const struct resource_create_funcs res_create_funcs = {
539 .read_dce_straps = read_dce_straps,
540 .create_audio = create_audio,
541 .create_stream_encoder = dce112_stream_encoder_create,
542 .create_hwseq = dce112_hwseq_create,
543 };
544
545 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
546 static const struct dce_mem_input_registers mi_regs[] = {
547 mi_inst_regs(0),
548 mi_inst_regs(1),
549 mi_inst_regs(2),
550 mi_inst_regs(3),
551 mi_inst_regs(4),
552 mi_inst_regs(5),
553 };
554
555 static const struct dce_mem_input_shift mi_shifts = {
556 MI_DCE11_2_MASK_SH_LIST(__SHIFT)
557 };
558
559 static const struct dce_mem_input_mask mi_masks = {
560 MI_DCE11_2_MASK_SH_LIST(_MASK)
561 };
562
563 static struct mem_input *dce112_mem_input_create(
564 struct dc_context *ctx,
565 uint32_t inst)
566 {
567 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
568 GFP_KERNEL);
569
570 if (!dce_mi) {
571 BREAK_TO_DEBUGGER();
572 return NULL;
573 }
574
575 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
576 return &dce_mi->base;
577 }
578
579 static void dce112_transform_destroy(struct transform **xfm)
580 {
581 kfree(TO_DCE_TRANSFORM(*xfm));
582 *xfm = NULL;
583 }
584
585 static struct transform *dce112_transform_create(
586 struct dc_context *ctx,
587 uint32_t inst)
588 {
589 struct dce_transform *transform =
590 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
591
592 if (!transform)
593 return NULL;
594
595 dce_transform_construct(transform, ctx, inst,
596 &xfm_regs[inst], &xfm_shift, &xfm_mask);
597 transform->lb_memory_size = 0x1404; /*5124*/
598 return &transform->base;
599 }
600
601 static const struct encoder_feature_support link_enc_feature = {
602 .max_hdmi_deep_color = COLOR_DEPTH_121212,
603 .max_hdmi_pixel_clock = 600000,
604 .hdmi_ycbcr420_supported = true,
605 .dp_ycbcr420_supported = false,
606 .flags.bits.IS_HBR2_CAPABLE = true,
607 .flags.bits.IS_HBR3_CAPABLE = true,
608 .flags.bits.IS_TPS3_CAPABLE = true,
609 .flags.bits.IS_TPS4_CAPABLE = true
610 };
611
612 struct link_encoder *dce112_link_encoder_create(
613 const struct encoder_init_data *enc_init_data)
614 {
615 struct dce110_link_encoder *enc110 =
616 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
617 int link_regs_id;
618
619 if (!enc110)
620 return NULL;
621
622 link_regs_id =
623 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
624
625 dce110_link_encoder_construct(enc110,
626 enc_init_data,
627 &link_enc_feature,
628 &link_enc_regs[link_regs_id],
629 &link_enc_aux_regs[enc_init_data->channel - 1],
630 &link_enc_hpd_regs[enc_init_data->hpd_source]);
631 return &enc110->base;
632 }
633
634 static struct input_pixel_processor *dce112_ipp_create(
635 struct dc_context *ctx, uint32_t inst)
636 {
637 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
638
639 if (!ipp) {
640 BREAK_TO_DEBUGGER();
641 return NULL;
642 }
643
644 dce_ipp_construct(ipp, ctx, inst,
645 &ipp_regs[inst], &ipp_shift, &ipp_mask);
646 return &ipp->base;
647 }
648
649 struct output_pixel_processor *dce112_opp_create(
650 struct dc_context *ctx,
651 uint32_t inst)
652 {
653 struct dce110_opp *opp =
654 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
655
656 if (!opp)
657 return NULL;
658
659 dce110_opp_construct(opp,
660 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
661 return &opp->base;
662 }
663
664 struct dce_aux *dce112_aux_engine_create(
665 struct dc_context *ctx,
666 uint32_t inst)
667 {
668 struct aux_engine_dce110 *aux_engine =
669 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
670
671 if (!aux_engine)
672 return NULL;
673
674 dce110_aux_engine_construct(aux_engine, ctx, inst,
675 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
676 &aux_engine_regs[inst],
677 &aux_mask,
678 &aux_shift,
679 ctx->dc->caps.extended_aux_timeout_support);
680
681 return &aux_engine->base;
682 }
683 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
684
685 static const struct dce_i2c_registers i2c_hw_regs[] = {
686 i2c_inst_regs(1),
687 i2c_inst_regs(2),
688 i2c_inst_regs(3),
689 i2c_inst_regs(4),
690 i2c_inst_regs(5),
691 i2c_inst_regs(6),
692 };
693
694 static const struct dce_i2c_shift i2c_shifts = {
695 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
696 };
697
698 static const struct dce_i2c_mask i2c_masks = {
699 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
700 };
701
702 struct dce_i2c_hw *dce112_i2c_hw_create(
703 struct dc_context *ctx,
704 uint32_t inst)
705 {
706 struct dce_i2c_hw *dce_i2c_hw =
707 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
708
709 if (!dce_i2c_hw)
710 return NULL;
711
712 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
713 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
714
715 return dce_i2c_hw;
716 }
717 struct clock_source *dce112_clock_source_create(
718 struct dc_context *ctx,
719 struct dc_bios *bios,
720 enum clock_source_id id,
721 const struct dce110_clk_src_regs *regs,
722 bool dp_clk_src)
723 {
724 struct dce110_clk_src *clk_src =
725 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
726
727 if (!clk_src)
728 return NULL;
729
730 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
731 regs, &cs_shift, &cs_mask)) {
732 clk_src->base.dp_clk_src = dp_clk_src;
733 return &clk_src->base;
734 }
735
736 kfree(clk_src);
737 BREAK_TO_DEBUGGER();
738 return NULL;
739 }
740
741 void dce112_clock_source_destroy(struct clock_source **clk_src)
742 {
743 kfree(TO_DCE110_CLK_SRC(*clk_src));
744 *clk_src = NULL;
745 }
746
747 static void dce112_resource_destruct(struct dce110_resource_pool *pool)
748 {
749 unsigned int i;
750
751 for (i = 0; i < pool->base.pipe_count; i++) {
752 if (pool->base.opps[i] != NULL)
753 dce110_opp_destroy(&pool->base.opps[i]);
754
755 if (pool->base.transforms[i] != NULL)
756 dce112_transform_destroy(&pool->base.transforms[i]);
757
758 if (pool->base.ipps[i] != NULL)
759 dce_ipp_destroy(&pool->base.ipps[i]);
760
761 if (pool->base.mis[i] != NULL) {
762 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
763 pool->base.mis[i] = NULL;
764 }
765
766 if (pool->base.timing_generators[i] != NULL) {
767 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
768 pool->base.timing_generators[i] = NULL;
769 }
770 }
771
772 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
773 if (pool->base.engines[i] != NULL)
774 dce110_engine_destroy(&pool->base.engines[i]);
775 if (pool->base.hw_i2cs[i] != NULL) {
776 kfree(pool->base.hw_i2cs[i]);
777 pool->base.hw_i2cs[i] = NULL;
778 }
779 if (pool->base.sw_i2cs[i] != NULL) {
780 kfree(pool->base.sw_i2cs[i]);
781 pool->base.sw_i2cs[i] = NULL;
782 }
783 }
784
785 for (i = 0; i < pool->base.stream_enc_count; i++) {
786 if (pool->base.stream_enc[i] != NULL)
787 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
788 }
789
790 for (i = 0; i < pool->base.clk_src_count; i++) {
791 if (pool->base.clock_sources[i] != NULL) {
792 dce112_clock_source_destroy(&pool->base.clock_sources[i]);
793 }
794 }
795
796 if (pool->base.dp_clock_source != NULL)
797 dce112_clock_source_destroy(&pool->base.dp_clock_source);
798
799 for (i = 0; i < pool->base.audio_count; i++) {
800 if (pool->base.audios[i] != NULL) {
801 dce_aud_destroy(&pool->base.audios[i]);
802 }
803 }
804
805 if (pool->base.abm != NULL)
806 dce_abm_destroy(&pool->base.abm);
807
808 if (pool->base.dmcu != NULL)
809 dce_dmcu_destroy(&pool->base.dmcu);
810
811 if (pool->base.irqs != NULL) {
812 dal_irq_service_destroy(&pool->base.irqs);
813 }
814 }
815
816 static struct clock_source *find_matching_pll(
817 struct resource_context *res_ctx,
818 const struct resource_pool *pool,
819 const struct dc_stream_state *const stream)
820 {
821 switch (stream->link->link_enc->transmitter) {
822 case TRANSMITTER_UNIPHY_A:
823 return pool->clock_sources[DCE112_CLK_SRC_PLL0];
824 case TRANSMITTER_UNIPHY_B:
825 return pool->clock_sources[DCE112_CLK_SRC_PLL1];
826 case TRANSMITTER_UNIPHY_C:
827 return pool->clock_sources[DCE112_CLK_SRC_PLL2];
828 case TRANSMITTER_UNIPHY_D:
829 return pool->clock_sources[DCE112_CLK_SRC_PLL3];
830 case TRANSMITTER_UNIPHY_E:
831 return pool->clock_sources[DCE112_CLK_SRC_PLL4];
832 case TRANSMITTER_UNIPHY_F:
833 return pool->clock_sources[DCE112_CLK_SRC_PLL5];
834 default:
835 return NULL;
836 };
837
838 return 0;
839 }
840
841 static enum dc_status build_mapped_resource(
842 const struct dc *dc,
843 struct dc_state *context,
844 struct dc_stream_state *stream)
845 {
846 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
847
848 if (!pipe_ctx)
849 return DC_ERROR_UNEXPECTED;
850
851 dce110_resource_build_pipe_hw_param(pipe_ctx);
852
853 resource_build_info_frame(pipe_ctx);
854
855 return DC_OK;
856 }
857
858 bool dce112_validate_bandwidth(
859 struct dc *dc,
860 struct dc_state *context,
861 bool fast_validate)
862 {
863 bool result = false;
864
865 DC_LOG_BANDWIDTH_CALCS(
866 "%s: start",
867 __func__);
868
869 if (bw_calcs(
870 dc->ctx,
871 dc->bw_dceip,
872 dc->bw_vbios,
873 context->res_ctx.pipe_ctx,
874 dc->res_pool->pipe_count,
875 &context->bw_ctx.bw.dce))
876 result = true;
877
878 if (!result)
879 DC_LOG_BANDWIDTH_VALIDATION(
880 "%s: Bandwidth validation failed!",
881 __func__);
882
883 if (memcmp(&dc->current_state->bw_ctx.bw.dce,
884 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
885
886 DC_LOG_BANDWIDTH_CALCS(
887 "%s: finish,\n"
888 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
889 "stutMark_b: %d stutMark_a: %d\n"
890 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
891 "stutMark_b: %d stutMark_a: %d\n"
892 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
893 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
894 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
895 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
896 ,
897 __func__,
898 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
899 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
900 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
901 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
902 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
903 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
904 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
905 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
906 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
907 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
908 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
909 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
910 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
911 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
912 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
913 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
914 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
915 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
916 context->bw_ctx.bw.dce.stutter_mode_enable,
917 context->bw_ctx.bw.dce.cpuc_state_change_enable,
918 context->bw_ctx.bw.dce.cpup_state_change_enable,
919 context->bw_ctx.bw.dce.nbp_state_change_enable,
920 context->bw_ctx.bw.dce.all_displays_in_sync,
921 context->bw_ctx.bw.dce.dispclk_khz,
922 context->bw_ctx.bw.dce.sclk_khz,
923 context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
924 context->bw_ctx.bw.dce.yclk_khz,
925 context->bw_ctx.bw.dce.blackout_recovery_time_us);
926 }
927 return result;
928 }
929
930 enum dc_status resource_map_phy_clock_resources(
931 const struct dc *dc,
932 struct dc_state *context,
933 struct dc_stream_state *stream)
934 {
935
936 /* acquire new resources */
937 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
938 &context->res_ctx, stream);
939
940 if (!pipe_ctx)
941 return DC_ERROR_UNEXPECTED;
942
943 if (dc_is_dp_signal(pipe_ctx->stream->signal)
944 || dc_is_virtual_signal(pipe_ctx->stream->signal))
945 pipe_ctx->clock_source =
946 dc->res_pool->dp_clock_source;
947 else
948 pipe_ctx->clock_source = find_matching_pll(
949 &context->res_ctx, dc->res_pool,
950 stream);
951
952 if (pipe_ctx->clock_source == NULL)
953 return DC_NO_CLOCK_SOURCE_RESOURCE;
954
955 resource_reference_clock_source(
956 &context->res_ctx,
957 dc->res_pool,
958 pipe_ctx->clock_source);
959
960 return DC_OK;
961 }
962
963 static bool dce112_validate_surface_sets(
964 struct dc_state *context)
965 {
966 int i;
967
968 for (i = 0; i < context->stream_count; i++) {
969 if (context->stream_status[i].plane_count == 0)
970 continue;
971
972 if (context->stream_status[i].plane_count > 1)
973 return false;
974
975 if (context->stream_status[i].plane_states[0]->format
976 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
977 return false;
978 }
979
980 return true;
981 }
982
983 enum dc_status dce112_add_stream_to_ctx(
984 struct dc *dc,
985 struct dc_state *new_ctx,
986 struct dc_stream_state *dc_stream)
987 {
988 enum dc_status result = DC_ERROR_UNEXPECTED;
989
990 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
991
992 if (result == DC_OK)
993 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
994
995
996 if (result == DC_OK)
997 result = build_mapped_resource(dc, new_ctx, dc_stream);
998
999 return result;
1000 }
1001
1002 enum dc_status dce112_validate_global(
1003 struct dc *dc,
1004 struct dc_state *context)
1005 {
1006 if (!dce112_validate_surface_sets(context))
1007 return DC_FAIL_SURFACE_VALIDATE;
1008
1009 return DC_OK;
1010 }
1011
1012 static void dce112_destroy_resource_pool(struct resource_pool **pool)
1013 {
1014 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1015
1016 dce112_resource_destruct(dce110_pool);
1017 kfree(dce110_pool);
1018 *pool = NULL;
1019 }
1020
1021 static const struct resource_funcs dce112_res_pool_funcs = {
1022 .destroy = dce112_destroy_resource_pool,
1023 .link_enc_create = dce112_link_encoder_create,
1024 .validate_bandwidth = dce112_validate_bandwidth,
1025 .validate_plane = dce100_validate_plane,
1026 .add_stream_to_ctx = dce112_add_stream_to_ctx,
1027 .validate_global = dce112_validate_global,
1028 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1029 };
1030
1031 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1032 {
1033 struct dm_pp_clock_levels_with_latency eng_clks = {0};
1034 struct dm_pp_clock_levels_with_latency mem_clks = {0};
1035 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
1036 struct dm_pp_clock_levels clks = {0};
1037 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
1038
1039 if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
1040 memory_type_multiplier = MEMORY_TYPE_HBM;
1041
1042 /*do system clock TODO PPLIB: after PPLIB implement,
1043 * then remove old way
1044 */
1045 if (!dm_pp_get_clock_levels_by_type_with_latency(
1046 dc->ctx,
1047 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1048 &eng_clks)) {
1049
1050 /* This is only for temporary */
1051 dm_pp_get_clock_levels_by_type(
1052 dc->ctx,
1053 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1054 &clks);
1055 /* convert all the clock fro kHz to fix point mHz */
1056 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1057 clks.clocks_in_khz[clks.num_levels-1], 1000);
1058 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
1059 clks.clocks_in_khz[clks.num_levels/8], 1000);
1060 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
1061 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1062 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
1063 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1064 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
1065 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1066 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
1067 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1068 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
1069 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1070 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
1071 clks.clocks_in_khz[0], 1000);
1072
1073 /*do memory clock*/
1074 dm_pp_get_clock_levels_by_type(
1075 dc->ctx,
1076 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1077 &clks);
1078
1079 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1080 clks.clocks_in_khz[0] * memory_type_multiplier, 1000);
1081 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1082 clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier,
1083 1000);
1084 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1085 clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,
1086 1000);
1087
1088 return;
1089 }
1090
1091 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
1092 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1093 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
1094 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
1095 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
1096 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
1097 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
1098 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
1099 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
1100 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
1101 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
1102 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
1103 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1104 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
1105 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1106 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
1107 eng_clks.data[0].clocks_in_khz, 1000);
1108
1109 /*do memory clock*/
1110 dm_pp_get_clock_levels_by_type_with_latency(
1111 dc->ctx,
1112 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1113 &mem_clks);
1114
1115 /* we don't need to call PPLIB for validation clock since they
1116 * also give us the highest sclk and highest mclk (UMA clock).
1117 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
1118 * YCLK = UMACLK*m_memoryTypeMultiplier
1119 */
1120 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1121 mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
1122 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1123 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
1124 1000);
1125 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1126 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
1127 1000);
1128
1129 /* Now notify PPLib/SMU about which Watermarks sets they should select
1130 * depending on DPM state they are in. And update BW MGR GFX Engine and
1131 * Memory clock member variables for Watermarks calculations for each
1132 * Watermark Set
1133 */
1134 clk_ranges.num_wm_sets = 4;
1135 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1136 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1137 eng_clks.data[0].clocks_in_khz;
1138 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1139 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1140 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1141 mem_clks.data[0].clocks_in_khz;
1142 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1143 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1144
1145 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1146 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1147 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1148 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1149 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1150 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1151 mem_clks.data[0].clocks_in_khz;
1152 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1153 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1154
1155 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1156 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1157 eng_clks.data[0].clocks_in_khz;
1158 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1159 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1160 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1161 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1162 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1163 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1164
1165 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1166 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1167 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1168 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1169 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1170 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1171 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1172 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1173 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1174
1175 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1176 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1177 }
1178
1179 const struct resource_caps *dce112_resource_cap(
1180 struct hw_asic_id *asic_id)
1181 {
1182 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1183 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
1184 return &polaris_11_resource_cap;
1185 else
1186 return &polaris_10_resource_cap;
1187 }
1188
1189 static bool dce112_resource_construct(
1190 uint8_t num_virtual_links,
1191 struct dc *dc,
1192 struct dce110_resource_pool *pool)
1193 {
1194 unsigned int i;
1195 struct dc_context *ctx = dc->ctx;
1196
1197 ctx->dc_bios->regs = &bios_regs;
1198
1199 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1200 pool->base.funcs = &dce112_res_pool_funcs;
1201
1202 /*************************************************
1203 * Resource + asic cap harcoding *
1204 *************************************************/
1205 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1206 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1207 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1208 dc->caps.max_downscale_ratio = 200;
1209 dc->caps.i2c_speed_in_khz = 100;
1210 dc->caps.max_cursor_size = 128;
1211 dc->caps.dual_link_dvi = true;
1212 dc->caps.extended_aux_timeout_support = false;
1213
1214 /*************************************************
1215 * Create resources *
1216 *************************************************/
1217
1218 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1219 dce112_clock_source_create(
1220 ctx, ctx->dc_bios,
1221 CLOCK_SOURCE_COMBO_PHY_PLL0,
1222 &clk_src_regs[0], false);
1223 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1224 dce112_clock_source_create(
1225 ctx, ctx->dc_bios,
1226 CLOCK_SOURCE_COMBO_PHY_PLL1,
1227 &clk_src_regs[1], false);
1228 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1229 dce112_clock_source_create(
1230 ctx, ctx->dc_bios,
1231 CLOCK_SOURCE_COMBO_PHY_PLL2,
1232 &clk_src_regs[2], false);
1233 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1234 dce112_clock_source_create(
1235 ctx, ctx->dc_bios,
1236 CLOCK_SOURCE_COMBO_PHY_PLL3,
1237 &clk_src_regs[3], false);
1238 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1239 dce112_clock_source_create(
1240 ctx, ctx->dc_bios,
1241 CLOCK_SOURCE_COMBO_PHY_PLL4,
1242 &clk_src_regs[4], false);
1243 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1244 dce112_clock_source_create(
1245 ctx, ctx->dc_bios,
1246 CLOCK_SOURCE_COMBO_PHY_PLL5,
1247 &clk_src_regs[5], false);
1248 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1249
1250 pool->base.dp_clock_source = dce112_clock_source_create(
1251 ctx, ctx->dc_bios,
1252 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
1253
1254
1255 for (i = 0; i < pool->base.clk_src_count; i++) {
1256 if (pool->base.clock_sources[i] == NULL) {
1257 dm_error("DC: failed to create clock sources!\n");
1258 BREAK_TO_DEBUGGER();
1259 goto res_create_fail;
1260 }
1261 }
1262
1263 pool->base.dmcu = dce_dmcu_create(ctx,
1264 &dmcu_regs,
1265 &dmcu_shift,
1266 &dmcu_mask);
1267 if (pool->base.dmcu == NULL) {
1268 dm_error("DC: failed to create dmcu!\n");
1269 BREAK_TO_DEBUGGER();
1270 goto res_create_fail;
1271 }
1272
1273 pool->base.abm = dce_abm_create(ctx,
1274 &abm_regs,
1275 &abm_shift,
1276 &abm_mask);
1277 if (pool->base.abm == NULL) {
1278 dm_error("DC: failed to create abm!\n");
1279 BREAK_TO_DEBUGGER();
1280 goto res_create_fail;
1281 }
1282
1283 {
1284 struct irq_service_init_data init_data;
1285 init_data.ctx = dc->ctx;
1286 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1287 if (!pool->base.irqs)
1288 goto res_create_fail;
1289 }
1290
1291 for (i = 0; i < pool->base.pipe_count; i++) {
1292 pool->base.timing_generators[i] =
1293 dce112_timing_generator_create(
1294 ctx,
1295 i,
1296 &dce112_tg_offsets[i]);
1297 if (pool->base.timing_generators[i] == NULL) {
1298 BREAK_TO_DEBUGGER();
1299 dm_error("DC: failed to create tg!\n");
1300 goto res_create_fail;
1301 }
1302
1303 pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1304 if (pool->base.mis[i] == NULL) {
1305 BREAK_TO_DEBUGGER();
1306 dm_error(
1307 "DC: failed to create memory input!\n");
1308 goto res_create_fail;
1309 }
1310
1311 pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1312 if (pool->base.ipps[i] == NULL) {
1313 BREAK_TO_DEBUGGER();
1314 dm_error(
1315 "DC:failed to create input pixel processor!\n");
1316 goto res_create_fail;
1317 }
1318
1319 pool->base.transforms[i] = dce112_transform_create(ctx, i);
1320 if (pool->base.transforms[i] == NULL) {
1321 BREAK_TO_DEBUGGER();
1322 dm_error(
1323 "DC: failed to create transform!\n");
1324 goto res_create_fail;
1325 }
1326
1327 pool->base.opps[i] = dce112_opp_create(
1328 ctx,
1329 i);
1330 if (pool->base.opps[i] == NULL) {
1331 BREAK_TO_DEBUGGER();
1332 dm_error(
1333 "DC:failed to create output pixel processor!\n");
1334 goto res_create_fail;
1335 }
1336 }
1337
1338 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1339 pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1340 if (pool->base.engines[i] == NULL) {
1341 BREAK_TO_DEBUGGER();
1342 dm_error(
1343 "DC:failed to create aux engine!!\n");
1344 goto res_create_fail;
1345 }
1346 pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1347 if (pool->base.hw_i2cs[i] == NULL) {
1348 BREAK_TO_DEBUGGER();
1349 dm_error(
1350 "DC:failed to create i2c engine!!\n");
1351 goto res_create_fail;
1352 }
1353 pool->base.sw_i2cs[i] = NULL;
1354 }
1355
1356 if (!resource_construct(num_virtual_links, dc, &pool->base,
1357 &res_create_funcs))
1358 goto res_create_fail;
1359
1360 dc->caps.max_planes = pool->base.pipe_count;
1361
1362 for (i = 0; i < dc->caps.max_planes; ++i)
1363 dc->caps.planes[i] = plane_cap;
1364
1365 /* Create hardware sequencer */
1366 dce112_hw_sequencer_construct(dc);
1367
1368 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1369
1370 bw_calcs_data_update_from_pplib(dc);
1371
1372 return true;
1373
1374 res_create_fail:
1375 dce112_resource_destruct(pool);
1376 return false;
1377 }
1378
1379 struct resource_pool *dce112_create_resource_pool(
1380 uint8_t num_virtual_links,
1381 struct dc *dc)
1382 {
1383 struct dce110_resource_pool *pool =
1384 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1385
1386 if (!pool)
1387 return NULL;
1388
1389 if (dce112_resource_construct(num_virtual_links, dc, pool))
1390 return &pool->base;
1391
1392 kfree(pool);
1393 BREAK_TO_DEBUGGER();
1394 return NULL;
1395 }
Linux with added FPC-III support